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path: root/hw/intc/loongarch_ipi.c
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2023-06-16hw/intc: Set physical cpuid route for LoongArch ipi deviceTianrui Zhao
LoongArch ipi device uses physical cpuid to route to different vcpus rather logical cpuid, and the physical cpuid is the same with cpuid in acpi dsdt and srat table. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Tianrui Zhao <zhaotianrui@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230613120552.2471420-3-zhaotianrui@loongson.cn>
2023-06-05hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxesJiaxun Yang
As per "Loongson 3A5000/3B5000 Processor Reference Manual", Loongson 3A5000's IPI implementation have 4 mailboxes per core. However, in 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device"), the number of IPI mailboxes was reduced to one, which mismatches actual hardware. It won't affect LoongArch based system as LoongArch boot code only uses the first mailbox, however MIPS based Loongson boot code uses all 4 mailboxes. Fixes Coverity CID: 1512452, 1512453 Fixes: 78464f023b54 ("hw/loongarch/virt: Modify ipi as percpu device") Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230521102307.87081-2-jiaxun.yang@flygoat.com> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-05-15hw/intc: Add NULL pointer check on LoongArch ipi deviceSong Gao
When ipi mailbox is used, cpu_index is decoded from iocsr register. cpu maybe does not exist. This patch adds NULL pointer check on ipi device. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230512100421.1867848-4-gaosong@loongson.cn>
2023-05-15hw/loongarch/virt: Modify ipi as percpu deviceSong Gao
ipi is used to communicate between cpus, this patch modified loongarch ipi device as percpu device, so that there are 2 MemoryRegions with ipi device, rather than 2*cpus MemoryRegions, which may be large than QDEV_MAX_MMIO if more cpus are added on loongarch virt machine. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230512100421.1867848-2-gaosong@loongson.cn>
2023-05-15loongarch: mark loongarch_ipi_iocsr re-entrnacy safeAlexander Bulekov
loongarch_ipi_iocsr MRs rely on re-entrant IO through the ipi_send function. As such, mark these MRs re-entrancy-safe. Fixes: a2e1753b80 ("memory: prevent dma-reentracy issues") Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230506112145.3563708-1-alxndr@bu.edu> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-05-06hw/intc: don't use target_ulong for LoongArch ipiAlex Bennée
The calling function is already working with hwaddr and uint64_t so lets avoid bringing target_ulong in if we don't need to. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230404132711.2563638-1-alex.bennee@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
2022-10-17hw/intc: Fix LoongArch ipi device emulationXiaojuan Yang
In ipi_send function, it should not to set irq before writing data to dest cpu iocsr space, as the irq will trigger after data writing. When call this function 'address_space_stl()', it will trigger loongarch_ipi_writel(), the addr arg is 0x1008 ('CORE_SET_OFF'), and qemu_irq_raise will be called in this case. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220930095139.867115-3-yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2022-07-05hw/intc/loongarch_ipi: Fix mail send and any send functionXiaojuan Yang
By the document of ipi mailsend device, byte is written only when the mask bit is 0. The original code discards mask bit and overwrite the data always, this patch fixes the issue. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Message-Id: <20220705064901.2353349-3-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-05hw/intc/loongarch_ipi: Fix ipi device access of 64bitsXiaojuan Yang
In general loongarch ipi device, 32bit registers is emulated, however for anysend/mailsend device only 64bit register access is supported. So separate the ipi memory region into two regions, including 32 bits and 64 bits. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Message-Id: <20220705064901.2353349-2-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06hw/loongarch: Add LoongArch ipi interrupt support(IPI)Xiaojuan Yang
This patch realize the IPI interrupt controller. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-32-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>