slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Collapse)	Author
2016-07-19	arm_gicv3: Add assert()s to tell Coverity that offsets are aligned	Peter Maydell
	Coverity complains that the GICR_IPRIORITYR case in gicv3_readl() can overflow an array, because it doesn't know that the offsets passed to that function must be word aligned. Add some assert()s which hopefully tell Coverity that this isn't possible. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1468261372-17508-1-git-send-email-peter.maydell@linaro.org
2016-06-20	hw/intc/arm_gicv3: Fix compilation with simple trace backend	Peter Maydell
	Fix missing includes of qemu/log.h, which broke compilation with the simple trace backend (the default backend pulls in log.h implicitly via trace.h). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <sergey.fedorov@linaro.org> Tested-by: Sergey Fedorov <sergey.fedorov@linaro.org> Message-id: 1466416634-9798-1-git-send-email-peter.maydell@linaro.org
2016-06-17	hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers	Peter Maydell
	Implement the registers in the GICv3 CPU interface which generate new SGI interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-18-git-send-email-peter.maydell@linaro.org
2016-06-17	hw/intc/arm_gicv3: Implement gicv3_set_irq()	Peter Maydell
	Implement the code which updates the GIC state when an interrupt input into the GIC is asserted. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1465915112-29272-15-git-send-email-peter.maydell@linaro.org
2016-06-17	hw/intc/arm_gicv3: Implement GICv3 redistributor registers	Shlomo Pongratz
	Implement the redistributor registers of a GICv3. Signed-off-by: Shlomo Pongratz <shlomo.pongratz@huawei.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Tested-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1465915112-29272-13-git-send-email-peter.maydell@linaro.org [PMM: significantly overhauled/rewritten: * use the new data structures * restructure register read/write to handle different width accesses natively, since almost all registers are 32-bit only, rather than implementing everything as byte accesses * implemented security extension support ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>