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path: root/hw/intc/arm_gicv3_cpuif.c
AgeCommit message (Expand)Author
2022-11-14hw/intc/arm_gicv3: fix prio masking on pmr writeJens Wiklander
2022-06-08Fix 'writeable' typosPeter Maydell
2022-05-19hw/intc/arm_gicv3: Provide ich_num_aprs()Peter Maydell
2022-05-19hw/intc/arm_gicv3: Use correct number of priority bits for the CPUPeter Maydell
2022-05-19hw/intc/arm_gicv3: Support configurable number of physical priority bitsPeter Maydell
2022-05-19hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1Peter Maydell
2022-05-19hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parametersPeter Maydell
2022-05-05target/arm: Replace sentinels with ARRAY_SIZE in cpregs.hRichard Henderson
2022-05-05target/arm: Split out cpregs.hRichard Henderson
2022-04-22hw/intc/arm_gicv3: Update ID and feature registers for GICv4Peter Maydell
2022-04-22hw/intc/arm_gicv3_cpuif: Don't recalculate maintenance irq unnecessarilyPeter Maydell
2022-04-22hw/intc/arm_gicv3_cpuif: Support vLPIsPeter Maydell
2022-04-22hw/intc/arm_gicv3_cpuif: Split "update vIRQ/vFIQ" from gicv3_cpuif_virt_update()Peter Maydell
2022-03-07hw/intc/arm_gicv3_cpuif: Fix register names in ICV_HPPIR read trace eventPeter Maydell
2021-12-15hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.cPhilippe Mathieu-Daudé
2021-12-07gicv3: fix ICH_MISR's LRENP computationDamien Hedde
2021-11-29hw/intc/arm_gicv3: fix handling of LPIs in list registersPeter Maydell
2021-11-26hw/intc/arm_gicv3: Add new gicv3_intid_is_special() functionPeter Maydell
2021-09-20hw/intc: Set GIC maintenance interrupt level to only 0 or 1Shashi Mallela
2021-09-13hw/intc: GICv3 redistributor ITS processingShashi Mallela
2021-07-09hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_writeRicardo Koller
2021-06-15hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writesJean-Philippe Brucker
2021-05-25hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logicPeter Maydell
2020-11-02hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts workPeter Maydell
2020-01-17arm/gicv3: update virtual irq state after IAR register readJeff Kubascik
2019-08-16Include hw/irq.h a lot lessMarkus Armbruster
2019-05-23hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3Peter Maydell
2019-05-23hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}Peter Maydell
2018-12-13target/arm: Introduce arm_hcr_el2_effRichard Henderson
2018-08-14target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO}Peter Maydell
2018-07-24hw/intc/arm_gicv3: Check correct HCR_EL2 bit when routing IRQPeter Maydell
2018-05-31hw/intc/arm_gicv3: Fix APxR<n> register dispatchingJan Kiszka
2018-04-26target/arm: Fetch GICv3 state directly from CPUARMStateAaron Lindsay
2018-03-23hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accessesPeter Maydell
2017-06-07arm_gicv3: Fix ICC_BPR1 reset value when EL3 not implementedPeter Maydell
2017-06-02hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1Peter Maydell
2017-06-02hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimumPeter Maydell
2017-06-02hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1Peter Maydell
2017-02-28target-arm: Add GICv3CPUState in CPUARMState structVijaya Kumar K
2017-02-24tcg: drop global lock during TCG code executionJan Kiszka
2017-01-27arm_gicv3: Fix broken logic in ELRSR calculationPeter Maydell
2017-01-20hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regsPeter Maydell
2017-01-20hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()Peter Maydell
2017-01-20hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IARPeter Maydell
2017-01-20hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registersPeter Maydell
2017-01-20hw/intc/arm_gicv3: Implement ICV_ registers which are just accessorsPeter Maydell
2017-01-20hw/intc/arm_gicv3: Add accessors for ICH_ system registersPeter Maydell
2017-01-20hw/intc/gicv3: Add data fields for virtualization supportPeter Maydell
2016-12-27hw/intc/arm_gicv3: Remove incorrect usage of fieldoffsetPeter Maydell
2016-10-17hw/intc/arm_gicv3: Fix ICC register tracepointsPeter Maydell
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