Age | Commit message (Expand) | Author |
2018-12-13 | target/arm: Introduce arm_hcr_el2_eff | Richard Henderson |
2018-08-14 | target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO} | Peter Maydell |
2018-07-24 | hw/intc/arm_gicv3: Check correct HCR_EL2 bit when routing IRQ | Peter Maydell |
2018-05-31 | hw/intc/arm_gicv3: Fix APxR<n> register dispatching | Jan Kiszka |
2018-04-26 | target/arm: Fetch GICv3 state directly from CPUARMState | Aaron Lindsay |
2018-03-23 | hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses | Peter Maydell |
2017-06-07 | arm_gicv3: Fix ICC_BPR1 reset value when EL3 not implemented | Peter Maydell |
2017-06-02 | hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1 | Peter Maydell |
2017-06-02 | hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum | Peter Maydell |
2017-06-02 | hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1 | Peter Maydell |
2017-02-28 | target-arm: Add GICv3CPUState in CPUARMState struct | Vijaya Kumar K |
2017-02-24 | tcg: drop global lock during TCG code execution | Jan Kiszka |
2017-01-27 | arm_gicv3: Fix broken logic in ELRSR calculation | Peter Maydell |
2017-01-20 | hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs | Peter Maydell |
2017-01-20 | hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update() | Peter Maydell |
2017-01-20 | hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR | Peter Maydell |
2017-01-20 | hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers | Peter Maydell |
2017-01-20 | hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors | Peter Maydell |
2017-01-20 | hw/intc/arm_gicv3: Add accessors for ICH_ system registers | Peter Maydell |
2017-01-20 | hw/intc/gicv3: Add data fields for virtualization support | Peter Maydell |
2016-12-27 | hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset | Peter Maydell |
2016-10-17 | hw/intc/arm_gicv3: Fix ICC register tracepoints | Peter Maydell |
2016-06-27 | hw/intc/arm_gicv3: Add missing break | Shannon Zhao |
2016-06-17 | hw/intc/arm_gicv3: Add IRQ handling CPU interface registers | Peter Maydell |
2016-06-17 | hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers | Peter Maydell |
2016-06-17 | hw/intc/arm_gicv3: Implement gicv3_cpuif_update() | Peter Maydell |
2016-06-17 | hw/intc/arm_gicv3: Implement GICv3 CPU interface registers | Peter Maydell |