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2024-07-09aspeed/soc: set dma64 property for AST2700 ftgmac100Jamin Lin
ASPEED AST2700 SOC is a 64 bits quad core CPUs (Cortex-a35) And the base address of dram is "0x4 00000000" which is 64bits address. Set dma64 property for ftgmac100 model to support 64bits dram address DMA. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-07-03Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Richard Henderson
into staging virtio: features,fixes A bunch of improvements: - vhost dirty log is now only scanned once, not once per device - virtio and vhost now support VIRTIO_F_NOTIFICATION_DATA - cxl gained DCD emulation support - pvpanic gained shutdown support - beginning of patchset for Generic Port Affinity Structure - s3 support - friendlier error messages when boot fails on some illegal configs - for vhost-user, VHOST_USER_SET_LOG_BASE is now only sent once - part of vhost-user support for any POSIX system - not yet enabled due to qtest failures - sr-iov VF setup code has been reworked significantly - new tests, particularly for risc-v ACPI - bugfixes Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmaF068PHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRp+DMIAMC//mBXIZlPprfhb5cuZklxYi31Acgu5TUr # njqjCkN+mFhXXZuc3B67xmrQ066IEPtsbzCjSnzuU41YK4tjvO1g+LgYJBv41G16 # va2k8vFM5pdvRA+UC9li1CCIPxiEcszxOdzZemj3szWLVLLUmwsc5OZLWWeFA5m8 # vXrrT9miODUz3z8/Xn/TVpxnmD6glKYIRK/IJRzzC4Qqqwb5H3ji/BJV27cDUtdC # w6ns5RYIj5j4uAiG8wQNDggA1bMsTxFxThRDUwxlxaIwAcexrf1oRnxGRePA7PVG # BXrt5yodrZYR2sR6svmOOIF3wPMUDKdlAItTcEgYyxaVo5rAdpc= # =p9h4 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 03 Jul 2024 03:41:51 PM PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [undefined] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (85 commits) hw/pci: Replace -1 with UINT32_MAX for romsize pcie_sriov: Register VFs after migration pcie_sriov: Remove num_vfs from PCIESriovPF pcie_sriov: Release VFs failed to realize pcie_sriov: Reuse SR-IOV VF device instances pcie_sriov: Ensure VF function number does not overflow pcie_sriov: Do not manually unrealize hw/ppc/spapr_pci: Do not reject VFs created after a PF hw/ppc/spapr_pci: Do not create DT for disabled PCI device hw/pci: Rename has_power to enabled virtio-iommu: Clear IOMMUDevice when VFIO device is unplugged virtio: remove virtio_tswap16s() call in vring_packed_event_read() hw/cxl/events: Mark cxl-add-dynamic-capacity and cxl-release-dynamic-capcity unstable hw/cxl/events: Improve QMP interfaces and documentation for add/release dynamic capacity. tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs meson.build: Add RISC-V to the edk2-target list tests/data/acpi/virt: Move ARM64 ACPI tables under aarch64/${machine} path tests/data/acpi: Move x86 ACPI tables under x86/${machine} path tests/qtest/bios-tables-test.c: Set "arch" for x86 tests ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-03hw/arm/virt-acpi-build: Fix id_count in build_iort_id_mappingNicolin Chen
It's observed that Linux kernel booting with the VM reports a "conflicting mapping for input ID" FW_BUG. The IORT doc defines "Number of IDs" to be "the number of IDs in the range minus one", while virt-acpi-build.c simply stores the number of IDs in the id_count without the "minus one". Meanwhile, some of the callers pass in a 0xFFFF following the spec. So, this is a mismatch between the function and its callers. Fix build_iort_id_mapping() by internally subtracting one from the pass-in @id_count. Accordingly make sure that all existing callers pass in a value without the "minus one", i.e. change all 0xFFFFs to 0x10000s. Also, add a few lines of comments to highlight this change along with the referencing document for this build_iort_id_mapping(). Fixes: 42e0f050e3a5 ("hw/arm/virt-acpi-build: Add IORT support to bypass SMMUv3") Suggested-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Message-Id: <20240619201243.936819-1-nicolinc@nvidia.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-07-03hw/arm/virt-acpi-build: Drop local iort_node_offsetNicolin Chen
Both the other two callers of build_iort_id_mapping() just directly pass in the IORT_NODE_OFFSET macro. Keeping a "const uint32_t" local variable storing the same value doesn't have any gain. Simplify this by replacing the only place using this local variable with the macro directly. Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Message-Id: <20240619001708.926511-1-nicolinc@nvidia.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2024-07-02Merge tag 'pull-aspeed-20240702' of https://github.com/legoater/qemu into ↵Richard Henderson
staging aspeed queue: * Coverity fixes * Deprecation of tacoma-bmc machine * Buffer overflow fix in GPIO model * Minor cleanup # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmaDs3QACgkQUaNDx8/7 # 7KEc/BAAj5AS3rLm3NPpU13y1P1hcjuSm1/PVGTJQH+m4K9UaAkJ8VhRB0Y/rdU6 # ygGhKaCHyk96+I49Csz886YU9Wg9qnxaYJAbornHZJVGNy5tuVpQKM20kfgN3XFN # ENJR3e+J6Ye7kCtR1ujcf0mydWDaDyq0i82ykURsudcQLMnGq1gBQGadYjt1hJoN # F9HDPgUJ8/wjQnG8BomsrnuvUSpRTbGNV66FNxXdQ6C6d6OTKQfNnXXqrKO+8QPK # B5XB9FjTk017DUog1jdE1SaEMowml8CmUhjMwLHOcyWhcZpEk90aMX8cQhefUs9y # O6kNin2UYEjcTHA/lyfMQJQMNDDZTE32MyP1LwRE/5ZiHqrT7ViqNvZSPBGBueUz # 9B0xiQTuYqcRqlwgyU73DvnTgrsKFdKQSldj5dXYVnWCKeKY/sCWApHMJxN9xMCA # Uw1E4QfCLkd+TM6DoJAkBHWFsgi44Aym11VU4VviGNRNTgmTptgQzmHiYGNFiGZG # OypVPM8Ti6UeVnW65l9J9f7xA0jDB+XQjhCCaoax9GlUMA4C4/Aln5OXXxIWRWFd # XA3Gn3c/S2j7rMqdfAk68xDHuAJ3wShHlw6HLRd1Xki05WFTeLj1lejLHMdfpNmr # DkQimzHShBqZzZGxc7FsO0keGY8kyIJkZhbCCbZrFXJXQGRdBao= # =LxwO # -----END PGP SIGNATURE----- # gpg: Signature made Tue 02 Jul 2024 12:59:48 AM PDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20240702' of https://github.com/legoater/qemu: hw/net:ftgmac100: fix coding style aspeed/sdmc: Remove extra R_MAIN_STATUS case aspeed/soc: Fix possible divide by zero aspeed/sdmc: Check RAM size value at realize time aspeed: Deprecate the tacoma-bmc machine hw/gpio/aspeed: Add reg_table_count to AspeedGPIOClass Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-02Merge tag 'hw-misc-20240702' of https://github.com/philmd/qemu into stagingRichard Henderson
Misc HW patches queue - Prevent NULL deref in sPAPR network model (Oleg) - Automatic deprecation of versioned machine types (Daniel) - Correct 'dump-guest-core' property name in hint (Akihiko) - Prevent IRQ leak in MacIO IDE model (Mark) - Remove dead #ifdef'ry related to unsupported macOS 12.0 (Akihiko) - Remove "hw/hw.h" where unnecessary (Thomas) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmaDiSQACgkQ4+MsLN6t # wN4jmBAA2kxwFAGbKvokANDAZBwWmJdnuIPcqS+jdo/wCuQXOo1ROADd3NFlgQWx # z1xOv/LiAmQiUeeiP+nlA8gWCdW93PErU07og1p1+N2D1sBO6oG5QDlT/tTFuEGd # IL21jG2xWkEemd3PSN2pHKrytpS0e4S0cNZIKgTUTKdv+Mb2ZEiQi7K4zUTjcmjz # nlsSjTXdyKBmoiqNGhITWfbR2IUWjtCpzUO44ceqXd5HDpvfGhpKI7Uwun1W2xNU # yw1XrAFd64Qhd/lvc28G1DLfDdtRIoaRGxgLzQbU6621s0o50Ecs6TNHseuUAKvd # tQhOtM8IEuZ6jVw8nswCPIcJyjbeY29kjI4WmD2weF1fZbDey6Emlrf+dkJUIuCb # TximyTXw3rb1nREUVsEQLF69BKjTjE5+ETaplcTWGHCoH2+uA/5MqygalTH1Ub9W # TwVWSUwpNvIJ3RTsT20YVowkill8piF+ECldTKzJuWjqDviiJDoMm5EFdkkcUB20 # nMyhGoiXtiQ4NYU0/B6HbHOXZkqLbhWcx9G281xJ+RRwjUyVxXD3zHGR9AoOp9ls # EAo/2URJtGN95LJmzCtaD+oo0wRZ5+7lmnqHPPXkYUdwFm4bhe3dP4NggIrS0cXn # 19wvBqQuPwywxIbFEu6327YtfPRcImWIlFthWnm9lUyDmbOqDKw= # =fLCx # -----END PGP SIGNATURE----- # gpg: Signature made Mon 01 Jul 2024 09:59:16 PM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'hw-misc-20240702' of https://github.com/philmd/qemu: (22 commits) Remove inclusion of hw/hw.h from files that don't need it net/vmnet: Drop ifdef for macOS versions older than 12.0 block/file-posix: Drop ifdef for macOS versions older than 12.0 audio: Drop ifdef for macOS versions older than 12.0 hvf: Drop ifdef for macOS versions older than 12.0 hw/ide/macio: switch from using qemu_allocate_irq() to qdev input GPIOs system/physmem: Fix reference to dump-guest-core docs: document special exception for machine type deprecation & removal hw/i386: remove obsolete manual deprecation reason string of i440fx machines hw/ppc: remove obsolete manual deprecation reason string of spapr machines hw: skip registration of outdated versioned machine types hw: set deprecation info for all versioned machine types include/hw: temporarily disable deletion of versioned machine types include/hw: add macros for deprecation & removal of versioned machines hw/i386: convert 'q35' machine definitions to use new macros hw/i386: convert 'i440fx' machine definitions to use new macros hw/m68k: convert 'virt' machine definitions to use new macros hw/ppc: convert 'spapr' machine definitions to use new macros hw/s390x: convert 'ccw' machine definitions to use new macros hw/arm: convert 'virt' machine definitions to use new macros ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-02aspeed/soc: Fix possible divide by zeroJamin Lin
Coverity reports a possible DIVIDE_BY_ZERO issue regarding the "ram_size" object property. This can not happen because RAM has predefined valid sizes per SoC. Nevertheless, add a test to close the issue. Fixes: Coverity CID 1547113 Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> [ clg: Rewrote commit log ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-07-02aspeed: Deprecate the tacoma-bmc machineCédric Le Goater
The tacoma-bmc machine was a board including an AST2600 SoC based BMC and a witherspoon like OpenPOWER system. It was used for bring up of the AST2600 SoC in labs. It can be easily replaced by the rainier-bmc machine which is part of a real product offering. Signed-off-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-07-02hw: skip registration of outdated versioned machine typesDaniel P. Berrangé
This calls the MACHINE_VER_DELETION() macro in the machine type registration method, so that when a versioned machine type reaches the end of its life, it is no longer registered with QOM and thus cannot be used. The actual definition of the machine type should be deleted at this point, but experience shows that can easily be forgotten. By skipping registration the manual code deletion task can be done at any later date. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240620165742.1711389-12-berrange@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-07-02hw: set deprecation info for all versioned machine typesDaniel P. Berrangé
This calls the MACHINE_VER_DEPRECATION() macro in the definition of all machine type classes which support versioning. This ensures that they will automatically get deprecation info set when they reach the appropriate point in their lifecycle. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240620165742.1711389-11-berrange@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-07-02hw/arm: convert 'virt' machine definitions to use new macrosDaniel P. Berrangé
This changes the DEFINE_VIRT_MACHINE macro to use the common helpers for constructing versioned symbol names and strings, bringing greater consistency across targets. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240620165742.1711389-3-berrange@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-07-01hw/arm/xilinx_zynq: Add boot-mode propertySai Pavan Boddu
Read boot-mode value as machine property and propagate that to SLCR.BOOT_MODE register. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20240621125906.1300995-3-sai.pavan.boddu@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-07-01hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdevNicolin Chen
The caller of smmu_iommu_mr wants to get sdev for smmuv3_flush_config(). Do it directly instead of bridging with an iommu mr pointer. Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Message-id: 20240619002218.926674-1-nicolinc@nvidia.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-07-01hw/misc: Implement mailbox properties for customer OTP and device specific ↵Rayhan Faizel
private keys Four mailbox properties are implemented as follows: 1. Customer OTP: GET_CUSTOMER_OTP and SET_CUSTOMER_OTP 2. Device-specific private key: GET_PRIVATE_KEY and SET_PRIVATE_KEY. The customer OTP is located in the rows 36-43. The device-specific private key is located in the rows 56-63. The customer OTP can be locked with the magic numbers 0xffffffff 0xaffe0000 when running the SET_CUSTOMER_OTP mailbox command. Bit 6 of row 32 indicates this lock, which is undocumented. The lock also applies to the device-specific private key. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-07-01hw/arm: Connect OTP device to BCM2835Rayhan Faizel
Replace stubbed OTP memory region with the new OTP device. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-06-30hw/arm/bcm2836: Remove unusued struct 'BCM283XClass'Dr. David Alan Gilbert
This struct has been unused since Commit f932093ae165 ("hw/arm/bcm2836: Split out common part of BCM283X classes") Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-06-21hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machineXiong Yining
Enable CPU cluster support on SbsaQemu platform, so that users can specify a 4-level CPU hierarchy sockets/clusters/cores/threads. And this topology can be passed to the firmware through /cpus/topology Device Tree. Signed-off-by: Xiong Yining <xiongyining1480@phytium.com.cn> Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20240607103825.1295328-2-xiongyining1480@phytium.com.cn Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-06-21hw/arm/virt: Avoid unexpected warning from Linux guest on host with Fujitsu CPUsZhenyu Zhang
Multiple warning messages and corresponding backtraces are observed when Linux guest is booted on the host with Fujitsu CPUs. One of them is shown as below. [ 0.032443] ------------[ cut here ]------------ [ 0.032446] uart-pl011 9000000.pl011: ARCH_DMA_MINALIGN smaller than CTR_EL0.CWG (128 < 256) [ 0.032454] WARNING: CPU: 0 PID: 1 at arch/arm64/mm/dma-mapping.c:54 arch_setup_dma_ops+0xbc/0xcc [ 0.032470] Modules linked in: [ 0.032475] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.14.0-452.el9.aarch64 [ 0.032481] Hardware name: linux,dummy-virt (DT) [ 0.032484] pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 0.032490] pc : arch_setup_dma_ops+0xbc/0xcc [ 0.032496] lr : arch_setup_dma_ops+0xbc/0xcc [ 0.032501] sp : ffff80008003b860 [ 0.032503] x29: ffff80008003b860 x28: 0000000000000000 x27: ffffaae4b949049c [ 0.032510] x26: 0000000000000000 x25: 0000000000000000 x24: 0000000000000000 [ 0.032517] x23: 0000000000000100 x22: 0000000000000000 x21: 0000000000000000 [ 0.032523] x20: 0000000100000000 x19: ffff2f06c02ea400 x18: ffffffffffffffff [ 0.032529] x17: 00000000208a5f76 x16: 000000006589dbcb x15: ffffaae4ba071c89 [ 0.032535] x14: 0000000000000000 x13: ffffaae4ba071c84 x12: 455f525443206e61 [ 0.032541] x11: 68742072656c6c61 x10: 0000000000000029 x9 : ffffaae4b7d21da4 [ 0.032547] x8 : 0000000000000029 x7 : 4c414e494d5f414d x6 : 0000000000000029 [ 0.032553] x5 : 000000000000000f x4 : ffffaae4b9617a00 x3 : 0000000000000001 [ 0.032558] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff2f06c029be40 [ 0.032564] Call trace: [ 0.032566] arch_setup_dma_ops+0xbc/0xcc [ 0.032572] of_dma_configure_id+0x138/0x300 [ 0.032591] amba_dma_configure+0x34/0xc0 [ 0.032600] really_probe+0x78/0x3dc [ 0.032614] __driver_probe_device+0x108/0x160 [ 0.032619] driver_probe_device+0x44/0x114 [ 0.032624] __device_attach_driver+0xb8/0x14c [ 0.032629] bus_for_each_drv+0x88/0xe4 [ 0.032634] __device_attach+0xb0/0x1e0 [ 0.032638] device_initial_probe+0x18/0x20 [ 0.032643] bus_probe_device+0xa8/0xb0 [ 0.032648] device_add+0x4b4/0x6c0 [ 0.032652] amba_device_try_add.part.0+0x48/0x360 [ 0.032657] amba_device_add+0x104/0x144 [ 0.032662] of_amba_device_create.isra.0+0x100/0x1c4 [ 0.032666] of_platform_bus_create+0x294/0x35c [ 0.032669] of_platform_populate+0x5c/0x150 [ 0.032672] of_platform_default_populate_init+0xd0/0xec [ 0.032697] do_one_initcall+0x4c/0x2e0 [ 0.032701] do_initcalls+0x100/0x13c [ 0.032707] kernel_init_freeable+0x1c8/0x21c [ 0.032712] kernel_init+0x28/0x140 [ 0.032731] ret_from_fork+0x10/0x20 [ 0.032735] ---[ end trace 0000000000000000 ]--- In Linux, a check is applied to every device which is exposed through device-tree node. The warning message is raised when the device isn't DMA coherent and the cache line size is larger than ARCH_DMA_MINALIGN (128 bytes). The cache line is sorted from CTR_EL0[CWG], which corresponds to 256 bytes on the guest CPUs. The DMA coherent capability is claimed through 'dma-coherent' in their device-tree nodes or parent nodes. This happens even when the device doesn't implement or use DMA at all, for legacy reasons. Fix the issue by adding 'dma-coherent' property to the device-tree root node, meaning all devices are capable of DMA coherent by default. This both suppresses the spurious kernel warnings and also guards against possible future QEMU bugs where we add a DMA-capable device and forget to mark it as dma-coherent. Signed-off-by: Zhenyu Zhang <zhenyzha@redhat.com> Reviewed-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Donald Dutile <ddutile@redhat.com Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-id: 20240612020506.307793-1-zhenyzha@redhat.com [PMM: tweaked commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-06-21hw/arm/virt: allow creation of a second NonSecure UARTPeter Maydell
For some use-cases, it is helpful to have more than one UART available to the guest. If the second UART slot is not already used for a TrustZone Secure-World-only UART, create it as a NonSecure UART only when the user provides a serial backend (e.g. via a second -serial command line option). This avoids problems where existing guest software only expects a single UART, and gets confused by the second UART in the DTB. The major example of this is older EDK2 firmware, which will send the GRUB bootloader output to UART1 and the guest serial output to UART0. Users who want to use both UARTs with a guest setup including EDK2 are advised to update to EDK2 release edk2-stable202311 or newer. (The prebuilt EDK2 blobs QEMU upstream provides are new enough.) The relevant EDK2 changes are the ones described here: https://bugzilla.tianocore.org/show_bug.cgi?id=4577 Inspired-by: Axel Heider <axel.heider@hensoldt.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240610162343.2131524-4-peter.maydell@linaro.org
2024-06-21hw/arm/virt: Rename VIRT_UART and VIRT_SECURE_UART to VIRT_UART[01]Peter Maydell
We're going to make the second UART not always a secure-only device. Rename the constants VIRT_UART and VIRT_SECURE_UART to VIRT_UART0 and VIRT_UART1 accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240610162343.2131524-3-peter.maydell@linaro.org
2024-06-21hw/arm/virt: Add serial aliases in DTBPeter Maydell
If there is more than one UART in the DTB, then there is no guarantee on which order a guest is supposed to initialise them. The standard solution to this is "serialN" entries in the "/aliases" node of the dtb which give the nodename of the UARTs. At the moment we only have two UARTs in the DTB when one is for the Secure world and one for the Non-Secure world, so this isn't really a problem. However if we want to add a second NS UART we'll need the aliases to ensure guests pick the right one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240610162343.2131524-2-peter.maydell@linaro.org
2024-06-21hw/arm/xilinx_zynq: Fix IRQ/FIQ routingSebastian Huber
Fix the system bus interrupt line to CPU core assignment. Fixes: ddcf58e044ce0 ("hw/arm/xilinx_zynq: Support up to two CPU cores") Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240610052906.4432-1-sebastian.huber@embedded-brains.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-06-21hw/arm/sbsa-ref: switch to 1GHz timer frequencyMarcin Juszkiewicz
Updated firmware for QEMU CI is already in merge queue so we can move platform to be future proof. All supported cpus work fine with 1GHz timer frequency when firmware is fresh enough. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20240531093729.220758-2-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-06-19hw/mem/pc-dimm: Remove legacy_align argument from pc_dimm_pre_plug()Philippe Mathieu-Daudé
'legacy_align' is always NULL, remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-15-philmd@linaro.org>
2024-06-19hw/smbios: Remove 'uuid_encoded' argument from smbios_set_defaults()Philippe Mathieu-Daudé
'uuid_encoded' is always true, remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240617071118.60464-12-philmd@linaro.org>
2024-06-16aspeed/soc: fix incorrect dram size for AST2700Jamin Lin
AST2700 dram size calculation is not back compatible AST2600. According to the DDR capacity hardware behavior, if users write the data to the address which is beyond the ram size, it would write the data to the "address % ram_size". For example: a. sdram base address "0x4 00000000" b. sdram size 1 GiB The available address range is from "0x4 00000000" to "0x4 3FFFFFFF". If users write 0x12345678 to address "0x5 00000000", the value of DRAM address 0 (base address 0x4 00000000) will be 0x12345678. Add aspeed_soc_ast2700_dram_init to calculate the dram size and add memory I/O whose address range is from "max_ram_size - ram_size" to max_ram_size and its read/write handler to emulate DDR capacity hardware behavior. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-06-16aspeed: Add an AST2700 eval boardJamin Lin
AST2700 CPU is ARM Cortex-A35 which is 64 bits. Add TARGET_AARCH64 to build this machine. According to the design of ast2700, it has a bootmcu(riscv-32) which is used for executing SPL. Then, CPUs(cortex-a35) execute u-boot, kernel and rofs. Currently, qemu not support emulate two CPU architectures at the same machine. Therefore, qemu will only support to emulate CPU(cortex-a35) side for ast2700 Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2024-06-16aspeed/soc: Add AST2700 supportJamin Lin
Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35 CPU). AST2700 SOC and its interrupt controller are too complex to handle in the common Aspeed SoC framework. We introduce a new ast2700 class with instance_init and realize handlers. AST2700 is a 64 bits quad core cpus and support 8 watchdog. Update maximum ASPEED_CPUS_NUM to 4 and ASPEED_WDTS_NUM to 8. In addition, update AspeedSocState to support scuio, sli, sliio and intc. Add TYPE_ASPEED27X0_SOC machine type. The SDMC controller is unlocked at SPL stage. At present, only supports to emulate booting start from u-boot stage. Set SDMC controller unlocked by default. In INTC, each interrupt of INT 128 to INT 136 combines 32 interrupts. It connect GICINT IRQ GPIO-OUTPUT pins to GIC device with irq 128 to 136. And, if a device irq is 128 to 136, its irq GPIO-OUTPUT pin is connected to GICINT or-gates instead of GIC device. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-06-09hw/arm: xen: Enable use of grant mappingsEdgar E. Iglesias
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-05-30arm/sbsa-ref: move to Neoverse-N2 as defaultMarcin Juszkiewicz
Moving to Neoverse-N2 gives us several cpu features to use for expanding our platform: - branch target identification - pointer authentication - RME for confidential computing - RNG for EFI_PROTOCOL_RNG - SVE being enabled by default We do not go for "max" as default to have stable set of features enabled by default. It is still supported and can be selected with "--cpu" argument. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20240523165353.6547-1-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30hw/arm/xilinx_zynq: Support up to two CPU coresSebastian Huber
The Zynq 7000 SoCs contain two Arm Cortex-A9 MPCore (the Zynq 7000S have only one core). Add support for up to two simulated cores. Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Message-id: 20240524120837.10057-3-sebastian.huber@embedded-brains.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: removed unnecessary double-cast] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-30hw/arm/xilinx_zynq: Add cache controllerSebastian Huber
The Zynq 7000 SoCs contain a CoreLink L2C-310 cache controller. Add the corresponding Qemu device to the xilinx-zynq-a9 machine. Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Message-id: 20240524120837.10057-2-sebastian.huber@embedded-brains.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28hw: arm: Remove use of tabs in some source filesTanmay Patil
Some of the source files for older devices use hardcoded tabs instead of our current coding standard's required spaces. Fix these in the following files: - hw/arm/boot.c - hw/char/omap_uart.c - hw/gpio/zaurus.c - hw/input/tsc2005.c This commit is mostly whitespace-only changes; it also adds curly-braces to some 'if' statements. This addresses part of https://gitlab.com/qemu-project/qemu/-/issues/373 but some other files remain to be handled. Signed-off-by: Tanmay Patil <tanmaynpatil105@gmail.com> Message-id: 20240508081502.88375-1-tanmaynpatil105@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28hw/arm/npcm7xx: remove setting of mp-affinityDorjoy Chowdhury
The value of the mp-affinity property being set in npcm7xx_realize is always the same as the default value it would have when arm_cpu_realizefn is called if the property is not set here. So there is no need to set the property value in npcm7xx_realize function. Signed-off-by: Dorjoy Chowdhury <dorjoychy111@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240504141733.14813-1-dorjoychy111@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-10kconfig: express dependency of individual boards on libfdtPaolo Bonzini
Now that boards are enabled by default and the "CONFIG_FOO=y" entries are gone from configs/devices/, there cannot be any more a conflicts between the default contents of configs/devices/ and a failed "depends on" clause. With this change, each individual board or target can express whether it needs FDT. It can then include the common code in the build via "select DEVICE_TREE", which will also as tell meson to link with libfdt. This allows building non-microvm x86 emulators without having libfdt available. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-05-10meson: pick libfdt from common_ss when building target-specific filesPaolo Bonzini
Avoid having to list dependencies such as libfdt twice, both on common_ss and specific_ss. Instead, just take all the dependencies in common_ss and allow the target-specific libqemu-*.fa library to use them. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-05-03arm: switch boards to "default y"Paolo Bonzini
For ARM targets, boards that require TCG are already using "default y". Switch ARM_VIRT to the same selection mechanism. No changes to generated config-devices.mak file. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-04-30hw/arm : Connect DM163 to B-L475E-IOT01AInès Varhol
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240424200929.240921-5-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hw/arm : Create Bl475eMachineStateInès Varhol
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240424200929.240921-4-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoCInès Varhol
Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC to the optional DM163 display from the board code (GPIOs outputs need to be connected to both SYSCFG inputs and DM163 inputs). STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240424200929.240921-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hw/arm/npcm7xx: Store derivative OTP fuse key in little endianPhilippe Mathieu-Daudé
Use little endian for derivative OTP fuse key. Cc: qemu-stable@nongnu.org Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model") Suggested-by: Avi Fishman <Avi.Fishman@nuvoton.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240422125813.1403-1-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM propertyPeter Maydell
Currently the sbsa_gdwt watchdog device hardcodes its frequency at 62.5MHz. In real hardware, this watchdog is supposed to be driven from the system counter, which also drives the CPU generic timers. Newer CPU types (in particular from Armv8.6) should have a CPU generic timer frequency of 1GHz, so we can't leave the watchdog on the old QEMU default of 62.5GHz. Make the frequency a QOM property so it can be set by the board, and have our only board that uses this device set that frequency to the same value it sets the CPU frequency. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240426122913.3427983-4-peter.maydell@linaro.org
2024-04-30hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHzPeter Maydell
Currently QEMU CPUs always run with a generic timer counter frequency of 62.5MHz, but ARMv8.6 CPUs will run at 1GHz. For older versions of the TF-A firmware that sbsa-ref runs, the frequency of the generic timer is hardcoded into the firmware, and so if the CPU actually has a different frequency then timers in the guest will be set incorrectly. The default frequency used by the 'max' CPU is about to change, so make the sbsa-ref board force the CPU frequency to the value which the firmware expects. Newer versions of TF-A will read the frequency from the CPU's CNTFRQ_EL0 register: https://github.com/ARM-software/arm-trusted-firmware/commit/4c77fac98dac0bebc63798aae9101ac865b87148 so in the longer term we could make this board use the 1GHz frequency. We will need to make sure we update the binaries used by our avocado test Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef before we can do that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20240426122913.3427983-3-peter.maydell@linaro.org
2024-04-25Merge tag 'hw-misc-20240425' of https://github.com/philmd/qemu into stagingRichard Henderson
Misc HW patch queue - Script to compare machines compat_props[] (Maksim) - Introduce 'module' CPU topology level (Zhao) - Various cleanups (Thomas, Zhao, Inès, Bernhard) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmYqN3wACgkQ4+MsLN6t # wN4hTw/9FHsItnEkme/864DRPSP7A9mCGa+JfzJmsL8oUb9fBjXXKm+lNchMLu3B # uvzfXB2Ea24yf5vyrldo0XlU3i/4GDvqXTI6YFYqBvitGICauYBu+6n2NZh2Y/Pn # zZCcVo167o0q7dHu2WSrZ6cSUchsF2C80HjuS07QaN2YZ7QMuN1+uqTjCQ/JHQWA # MH4xHh7cXdfCbbv8iNhMWn6sa+Bw/UyfRcc2W6w9cF5Q5cuuTshgDyd0JBOzkM1i # Mcul7TuKrSiLUeeeqfTjwtw3rtbNfkelV3ycgvgECFAlzPSjF5a6d/EGdO2zo3T/ # aFZnQBYrb4U0SzsmfXFHW7cSylIc1Jn2CCuZZBIvdVcu8TGDD5XsgZbGoCfKdWxp # l67qbQJy1Mp3LrRzygJIaxDOfE8fhhRrcIxfK/GoTHaCkqeFRkGjTeiDTVBqAES2 # zs6kUYZyG/xGaa2tsMu+HbtSO5EEqPC2QCdHayY3deW42Kwjj/HFV50Ya8YgYSVp # gEAjTDOle2dDjlkYud+ymTJz7LnGb3G7q0EZRI9DWolx/bu+uZGQqTSRRre4qFQY # SgN576hsFGN4NdM7tyJWiiqD/OC9ZeqUx3gGBtmI52Q6obBCE9hcow0fPs55Tk95 # 1YzPrt/3IoPI5ZptCoA8DFiysQ46OLtpIsQO9YcrpJmxWyLDSr0= # =tm+U # -----END PGP SIGNATURE----- # gpg: Signature made Thu 25 Apr 2024 03:59:08 AM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'hw-misc-20240425' of https://github.com/philmd/qemu: (22 commits) hw/core: Support module-id in numa configuration hw/core: Introduce module-id as the topology subindex hw/core/machine: Support modules in -smp hw/core/machine: Introduce the module as a CPU topology level hw/i386/pc_sysfw: Remove unused parameter from pc_isa_bios_init() hw/misc : Correct 5 spaces indents in stm32l4x5_exti hw/xtensa: Include missing 'exec/cpu-common.h' in 'bootparam.h' hw/elf_ops: Rename elf_ops.h -> elf_ops.h.inc hw/cxl/cxl-cdat: Make cxl_doe_cdat_init() return boolean hw/cxl/cxl-cdat: Make ct3_build_cdat() return boolean hw/cxl/cxl-cdat: Make ct3_load_cdat() return boolean hw: Add a Kconfig switch for the TYPE_CPU_CLUSTER device hw: Fix problem with the A*MPCORE switches in the Kconfig files hw/riscv/virt: Replace sprintf by g_strdup_printf hw/misc/imx: Replace sprintf() by snprintf() hw/misc/applesmc: Simplify DeviceReset handler target/i386: Move APIC related code to cpu-apic.c hw/core: Remove check on NEED_CPU_H in tcg-cpu-ops.h scripts: add script to compare compatibility properties python/qemu/machine: add method to retrieve QEMUMachine::binary field ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-25hw: Add a Kconfig switch for the TYPE_CPU_CLUSTER deviceThomas Huth
The cpu-cluster device is only needed for some few arm and riscv machines. Let's avoid compiling and linking it if it is not really necessary. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240415065655.130099-3-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-04-25hw: Fix problem with the A*MPCORE switches in the Kconfig filesThomas Huth
A9MPCORE, ARM11MPCORE and A15MPCORE are defined twice, once in hw/cpu/Kconfig and once in hw/arm/Kconfig. This is only possible by accident, since hw/cpu/Kconfig is never included from hw/Kconfig. Fix it by declaring the switches only in hw/cpu/Kconfig (since the related files reside in the hw/cpu/ folder) and by making sure that the file hw/cpu/Kconfig is now properly included from hw/Kconfig. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240415065655.130099-2-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-04-25hw/arm: Add the USART to the stm32l4x5 SoCArnaud Minier
Add the USART to the SoC and connect it to the other implemented devices. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240329174402.60382-5-arnaud.minier@telecom-paris.fr [PMM: fixed a few checkpatch nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-25hw, target: Add ResetType argument to hold and exit phase methodsPeter Maydell
We pass a ResetType argument to the Resettable class enter phase method, but we don't pass it to hold and exit, even though the callsites have it readily available. This means that if a device cared about the ResetType it would need to record it in the enter phase method to use later on. Pass the type to all three of the phase methods to avoid having to do that. Commit created with for dir in hw target include; do \ spatch --macro-file scripts/cocci-macro-file.h \ --sp-file scripts/coccinelle/reset-type.cocci \ --keep-comments --smpl-spacing --in-place \ --include-headers --dir $dir; done and no manual edits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20240412160809.1260625-5-peter.maydell@linaro.org
2024-04-25hw/arm/virt: Enable NMI support in the GIC if the CPU has FEAT_NMIJinjie Ruan
If the CPU implements FEAT_NMI, then turn on the NMI support in the GICv3 too. It's permitted to have a configuration with FEAT_NMI in the CPU (and thus NMI support in the CPU interfaces too) but no NMI support in the distributor and redistributor, but this isn't a very useful setup as it's close to having no NMI support at all. We don't need to gate the enabling of NMI in the GIC behind a machine version property, because none of our current CPUs implement FEAT_NMI, and '-cpu max' is not something we maintain migration compatibility across versions for. So we can always enable the GIC NMI support when the CPU has it. Neither hvf nor KVM support NMI in the GIC yet, so we don't enable it unless we're using TCG. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240407081733.3231820-25-ruanjinjie@huawei.com [PMM: Update comment and commit message] Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-25hw/arm/virt: Wire NMI and VINMI irq lines from GIC to CPUJinjie Ruan
Wire the new NMI and VINMI interrupt line from the GIC to each CPU if it is not GICv2. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240407081733.3231820-12-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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