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2015-06-02target-arm: Add GIC phandle to VirtBoardInfoChristoffer Dall
Instead of passing the GIC phandle around between functions, add it to the VirtBoardInfo just like we do for the clock_phandle. We are about to add the v2m phandle as well, and it's easier not having to pass around a bunch of phandles, return multiple values from functions, etc. Reviewed-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-2-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt: Enable dynamic generation of ACPI v5.1 tablesShannon Zhao
Initialize VirtGuestInfoState and register a machine_init_done notify to call virt_acpi_build(). Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-25-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT tableShannon Zhao
Add PCIe controller in ACPI DSDT table, so the guest can detect the PCIe. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-23-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate MCFG tableShannon Zhao
Generate MCFG table for PCIe controller. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-14-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate RSDP tableShannon Zhao
RSDP points to RSDT which in turn points to other tables. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-13-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate RSDT tableShannon Zhao
RSDT points to other tables FADT, MADT, GTDT. This code is shared with x86. Here we still use RSDT as UEFI puts ACPI tables below 4G address space, and UEFI ignore the RSDT or XSDT. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-12-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate GTDT tableShannon Zhao
ACPI v5.1 defines GTDT for ARM devices as a place to describe timer related information in the system. The Arch Timer interrupts must be provided for GTDT. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-11-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate MADT tableShannon Zhao
MADT describes GIC enabled ARM platforms. The GICC and GICD subtables are used to define the GIC regions. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-10-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate FADT table and update ACPI headersShannon Zhao
In the case of mach virt, it is used to set the Hardware Reduced bit and enable PSCI SMP booting through HVC. So ignore FACS and FADT points to DSDT. Update the header definitions for FADT taking into account the new additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h` Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-9-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generation of DSDT table for virt devicesShannon Zhao
DSDT consists of the usual common table header plus a definition block in AML encoding which describes all devices in the platform. After initializing DSDT with header information the namespace is created which is followed by the device encodings. The devices are described using the Resource Template for the 32-Bit Fixed Memory Range and the Extended Interrupt Descriptors. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-8-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARMShannon Zhao
Introduce a preliminary framework in virt-acpi-build.c with the main ACPI build functions. It exposes the generated ACPI contents to guest over fw_cfg. The required ACPI v5.1 tables for ARM are: - RSDP: Initial table that points to XSDT - RSDT: Points to FADT GTDT MADT tables - FADT: Generic information about the machine - GTDT: Generic timer description table - MADT: Multiple APIC description table - DSDT: Holds all information about system devices/peripherals, pointed by FADT Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1432522520-8068-5-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt: Record PCIe ranges in MemMapEntry arrayShannon Zhao
To generate ACPI table for PCIe controller, we need the base and size of the PCIe ranges. Record these ranges in MemMapEntry array, then we could share and use them for generating ACPI table. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-4-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt: Move common definitions to virt.hShannon Zhao
Move some common definitions to virt.h. These will be used by generating ACPI tables. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-3-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18arm: xlnx-ep108: Add bootloadingPeter Crosthwaite
Add bootloader support using standard ARM bootloader. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: b829abaf2b70d02b28e79301553cbd74afc416a1.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18arm: xlnx-ep108: Add external RAMPeter Crosthwaite
Zynq MPSoC supports external DDR RAM. Add a RAM at 0 to the model. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 2c25e2a4198402a6477aef2975d5df7c415dd341.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18arm: Add xlnx-ep108 machinePeter Crosthwaite
Add a machine model for the Xilinx ZynqMP SoC EP108 board. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 3896b34c862f370dc0679e4428bf3848d1f9f83c.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18arm: xlnx-zynqmp: Add UART supportPeter Crosthwaite
There are 2x Cadence UARTs in Zynq MP. Add them. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: e30795536f77599fabc1052278d846ccd52322e2.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18arm: xlnx-zynqmp: Add GEM supportPeter Crosthwaite
There are 4x Cadence GEMs in ZynqMP. Add them. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 7d3e68e5495d145255f0ee567046415e3a26d67e.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18arm: xlnx-zynqmp: Connect CPU Timers to GICPeter Crosthwaite
Connect the GPIO outputs from the individual CPUs for the timers to the GIC. Tested-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a7866a4f0c903c91fa3034210b4d2879aa4bfcb9.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18arm: xlnx-zynqmp: Add GICPeter Crosthwaite
Add the GIC and connect IRQ outputs to the CPUs. The GIC regions are under-decoded through a 64k address region so implement aliases accordingly. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5853189965728d676106d9e94e76b9bb87981cb5.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-18arm: Introduce Xilinx ZynqMP SoCPeter Crosthwaite
With quad Cortex-A53 CPUs. Use SMC PSCI, with the standard policy of secondaries starting in power-off. Tested-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/arm/highbank.c: Wire FIQ between CPU <> GICPeter Maydell
Connect FIQ output of the GIC CPU interfaces to the CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-18-git-send-email-peter.maydell@linaro.org
2015-05-12hw/arm/vexpress.c: Wire FIQ between CPU <> GICFabian Aggeler
Connect FIQ output of the GIC CPU interfaces to the CPUs. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-17-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-3-git-send-email-greg.bellows@linaro.org [PMM: minor format tweak] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/arm/virt.c: Wire FIQ between CPU <> GICGreg Bellows
Connect FIQ output of the GIC CPU interfaces to the CPUs. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-16-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-4-git-send-email-greg.bellows@linaro.org [PMM: minor format tweak] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-28Convert ffs() != 0 callers to ctz32()Stefan Hajnoczi
There are a number of ffs(3) callers that do roughly: bit = ffs(val); if (bit) { do_something(bit - 1); } This pattern can be converted to ctz32() like this: zeroes = ctz32(val); if (zeroes != 32) { do_something(zeroes); } Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-6-git-send-email-stefanha@redhat.com Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-04-28Convert (ffs(val) - 1) to ctz32(val)Stefan Hajnoczi
This commit was generated mechanically by coccinelle from the following semantic patch: @@ expression val; @@ - (ffs(val) - 1) + ctz32(val) The call sites have been audited to ensure the ffs(0) - 1 == -1 case never occurs (due to input validation, asserts, etc). Therefore we don't need to worry about the fact that ctz32(0) == 32. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-5-git-send-email-stefanha@redhat.com Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-04-28hw/arm/nseries: convert ffs(3) to ctz32()Stefan Hajnoczi
It is not clear from the code how a 0 parameter should be handled by the hardware. Keep the same behavior as ffs(0) - 1 == -1. Cc: Andrzej Zaborowski <balrog@zabor.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-3-git-send-email-stefanha@redhat.com Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2015-04-26target-arm: rename c1_coproc to cpacr_el1Sergey Fedorov
Rename the field holding CPACR_EL1 system register state in AArch64 naming style. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> [PMM: also fixed a couple of missed occurrences in cpu.c] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-26Switch non-CPU callers from ld/st*_phys to address_space_ld/st*Peter Maydell
Switch all the uses of ld/st*_phys to address_space_ld/st*, except for those cases where the address space is the CPU's (ie cs->as). This was done with the following script which generates a Coccinelle patch. A few over-80-columns lines in the result were rewrapped by hand where Coccinelle failed to do the wrapping automatically, as well as one location where it didn't put a line-continuation '\' when wrapping lines on a change made to a match inside a macro definition. ===begin=== #!/bin/sh -e # Usage: # ./ldst-phys.spatch.sh > ldst-phys.spatch # spatch -sp_file ldst-phys.spatch -dir . | sed -e '/^+/s/\t/ /g' > out.patch # patch -p1 < out.patch for FN in ub uw_le uw_be l_le l_be q_le q_be uw l q; do cat <<EOF @ cpu_matches_ld_${FN} @ expression E1,E2; identifier as; @@ ld${FN}_phys(E1->as,E2) @ other_matches_ld_${FN} depends on !cpu_matches_ld_${FN} @ expression E1,E2; @@ -ld${FN}_phys(E1,E2) +address_space_ld${FN}(E1,E2, MEMTXATTRS_UNSPECIFIED, NULL) EOF done for FN in b w_le w_be l_le l_be q_le q_be w l q; do cat <<EOF @ cpu_matches_st_${FN} @ expression E1,E2,E3; identifier as; @@ st${FN}_phys(E1->as,E2,E3) @ other_matches_st_${FN} depends on !cpu_matches_st_${FN} @ expression E1,E2,E3; @@ -st${FN}_phys(E1,E2,E3) +address_space_st${FN}(E1,E2,E3, MEMTXATTRS_UNSPECIFIED, NULL) EOF done ===endit=== Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2015-04-08arm: memory: Replace memory_region_init_ram with ↵Dirk Müller
memory_region_allocate_system_memory Commit 0b183fc871:"memory: move mem_path handling to memory_region_allocate_system_memory" split memory_region_init_ram and memory_region_init_ram_from_file. Also it moved mem-path handling a step up from memory_region_init_ram to memory_region_allocate_system_memory. Therefore for any board that uses memory_region_init_ram directly, -mem-path is not supported. Fix this by replacing memory_region_init_ram with memory_region_allocate_system_memory. Signed-off-by: Dirk Mueller <dmueller@suse.com> Message-id: CAL5wTH4UHYKpJF=dLJfFzxpufjY189chnCow47-ySuLf8GLbug@mail.gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-02Merge remote-tracking branch 'remotes/armbru/tags/pull-hw-2015-04-02' into ↵Peter Maydell
staging hw: Contain drive, serial, parallel, net misuse # gpg: Signature made Thu Apr 2 14:32:00 2015 BST using RSA key ID EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" * remotes/armbru/tags/pull-hw-2015-04-02: sysbus: Make devices picking up backends unavailable with -device sdhci: Make device "sdhci-pci" unavailable with -device hw: Mark device misusing nd_table[] FIXME hw: Mark devices picking up char backends actively FIXME hw: Mark devices picking up block backends actively FIXME Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-02sysbus: Make devices picking up backends unavailable with -deviceMarkus Armbruster
Device models aren't supposed to go on fishing expeditions for backends. They should expose suitable properties for the user to set. For onboard devices, board code sets them. A number of sysbus devices pick up block backends in their init() / instance_init() methods with drive_get_next() instead: sl-nand, milkymist-memcard, pl181, generic-sdhci. Likewise, a number of sysbus devices pick up character backends in their init() / realize() methods with qemu_char_get_next_serial(): cadence_uart, digic-uart, etraxfs,serial, lm32-juart, lm32-uart, milkymist-uart, pl011, stm32f2xx-usart, xlnx.xps-uartlite. All these mistakes are already marked FIXME. See the commit that added these FIXMEs for a more detailed explanation of what's wrong. Fortunately, only machines ppce500 and pseries-* support -device with sysbus devices, and none of the devices above is supported with these machines. Set cannot_instantiate_with_device_add_yet to preserve our luck. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2015-04-02hw: Mark device misusing nd_table[] FIXMEMarkus Armbruster
NICs defined with -net nic are for board initialization to wire up. Board code examines nd_table[] to find them, and creates devices with their qdev NIC properties set accordingly. Except "allwinner-a10" goes on a fishing expedition for NIC configuration instead of exposing the usual NIC properties for board code to set: it uses nd_table[0] in its instance_init() method. Picking up the first -net nic option's configuration that way works when the device is created by board code. But it's inappropriate for -device and device_add. Not only is it inconsistent with how the other block device models work (they get their configuration from properties "mac", "vlan", "netdev"), it breaks when nd_table[0] has been picked up by the board or a previous -device / device_add already. Example: $ qemu-system-arm -S -M cubieboard -device allwinner-a10 qemu-system-arm: -device allwinner-a10: Property 'allwinner-emac.netdev' can't take value 'hub0port0', it's in use Aborted (core dumped) It also breaks in other entertaining ways: $ qemu-system-arm -M highbank -device allwinner-a10 qemu-system-arm: -device allwinner-a10: Unsupported NIC model: xgmac $ qemu-system-arm -M highbank -net nic,model=allwinner-emac -device allwinner-a10 qemu-system-arm: Unsupported NIC model: allwinner-emac Mark the mistake with a FIXME comment. Cc: Li Guang <lig.fnst@cn.fujitsu.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2015-04-02hw: Mark devices picking up char backends actively FIXMEMarkus Armbruster
Character devices defined with -serial and -parallel are for board initialization to wire up. Board code examines serial_hds[] and parallel_hds[] to find them, and creates devices with their qdev chardev properties set accordingly. Except a few devices go on a fishing expedition for a suitable backend instead of exposing a chardev property for board code to set: they use serial_hds[] (often via qemu_char_get_next_serial()) or parallel_hds[] in their realize() or init() method to connect to a backend. Picking up backends that way works when the devices are created by board code. But it's inappropriate for -device or device_add. Not only is it inconsistent with how the other characrer device models work (they connect to a backend explicitly identified by a "chardev" property), it breaks when the backend has been picked up by the board or a previous -device / device_add already. Example: $ qemu-system-ppc64 -M bamboo -S -device i82378 -device pc87312 -device pc87312 qemu-system-ppc64: -device pc87312: Property 'isa-parallel.chardev' can't take value 'parallel0', it's in use Mark them with suitable FIXME comments. Cc: Li Guang <lig.fnst@cn.fujitsu.com> Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Cc: Antony Pavlov <antonynpavlov@gmail.com> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Cc: "Andreas Färber" <andreas.faerber@web.de> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2015-04-02hw: Mark devices picking up block backends actively FIXMEMarkus Armbruster
Drives defined with if!=none are for board initialization to wire up. Board code calls drive_get() or similar to find them, and creates devices with their qdev drive properties set accordingly. Except a few devices go on a fishing expedition for a suitable backend instead of exposing a drive property for board code to set: they call driver_get() or drive_get_next() in their realize() or init() method to implicitly connect to the "next" backend with a certain interface type. Picking up backends that way works when the devices are created by board code. But it's inappropriate for -device or device_add. Not only is this inconsistent with how the other block device models work (they connect to a backend explicitly identified by a "drive" property), it breaks when the "next" backend has been picked up by the board already. Example: $ qemu-system-arm -S -M connex -pflash flash.img -device ssi-sd Aborted (core dumped) Mark them with suitable FIXME comments. Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Cc: "Andreas Färber" <andreas.faerber@web.de> Cc: Michael Walle <michael@walle.cc> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2015-04-02hw/arm/vexpress: Don't double-free flash filenamePeter Maydell
Commits 6e05a12f8f7f and db25a1581 both attempt to fix the same "failed to free memory containing flash filename" bug, with the effect that when they were both applied we ended up freeing the memory twice. Delete the spurious extra free. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-id: 1427968334-14527-1-git-send-email-peter.maydell@linaro.org
2015-04-02hw/arm/virt: Fix corruption due to double freeShannon Zhao
As 4de9a88(hw/arm/virt: Fix memory leak reported by Coverity) and 6e05a12(arm: fix memory leak) both handle the memory leak reported by Coverity, this cause qemu corruption due to double free. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-id: 1427944026-8968-1-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-01hw/arm/virt: Fix memory leak reported by CoverityStefan Weil
As the conditional statement had to be split anyway, we can also add a better error report message. Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1426877982-3603-1-git-send-email-sw@weilnetz.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-01hw/arm/vexpress: Fix memory leak reported by CoverityStefan Weil
As the conditional statement had to be split anyway, we can also add a better error report message. Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1426877963-3556-1-git-send-email-sw@weilnetz.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-01hw/arm/highbank: Fix resource leak and wrong image loadingStefan Weil
Coverity reports a resource leak for sysboot_filename which is allocated by qemu_find_file. In addition, that name is used to get the size of the image, but a different image name was used to load it. In addition, instead of passing the maximum allowed image size the actual image size was passed to load_image_targphys. Fix all three issues. Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1426326781-2488-1-git-send-email-sw@weilnetz.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-19error: Replace error_report() & error_free() with error_report_err()zhanghailiang
This is a continuation of the work started in commit 565f65d27: "error: Use error_report_err() where appropriate" Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-03-19arm: fix memory leakGonglei
Cc: Michael Tokarev <mjt@tls.msk.ru> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-03-19arm/nseries: Fix warnings from SparseStefan Weil
Sparse report: arm/nseries.c:1406:5: warning: returning void-valued expression arm/nseries.c:1411:5: warning: returning void-valued expression Cc: Andrzej Zaborowski <balrogg@gmail.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-03-19omap: Fix warnings from SparseStefan Weil
Sparse report: arm/omap1.c:1015:9: warning: returning void-valued expression arm/omap1.c:1084:9: warning: returning void-valued expression arm/omap1.c:1178:9: warning: returning void-valued expression arm/omap1.c:1287:9: warning: returning void-valued expression arm/omap1.c:1382:9: warning: returning void-valued expression arm/omap1.c:1650:9: warning: returning void-valued expression arm/omap1.c:1778:9: warning: returning void-valued expression arm/omap1.c:1985:9: warning: returning void-valued expression arm/omap1.c:210:9: warning: returning void-valued expression arm/omap1.c:2213:9: warning: returning void-valued expression arm/omap1.c:2352:9: warning: returning void-valued expression arm/omap1.c:2447:9: warning: returning void-valued expression arm/omap1.c:2640:9: warning: returning void-valued expression arm/omap1.c:317:9: warning: returning void-valued expression arm/omap1.c:3413:13: warning: returning void-valued expression arm/omap1.c:3414:13: warning: returning void-valued expression arm/omap1.c:3415:14: warning: returning void-valued expression arm/omap1.c:3589:9: warning: returning void-valued expression arm/omap1.c:443:9: warning: returning void-valued expression arm/omap1.c:588:9: warning: returning void-valued expression arm/omap1.c:860:9: warning: returning void-valued expression arm/omap2.c:1362:9: warning: returning void-valued expression arm/omap2.c:450:9: warning: returning void-valued expression arm/omap2.c:695:9: warning: returning void-valued expression arm/omap2.c:760:9: warning: returning void-valued expression hw/char/omap_uart.c:115:9: warning: returning void-valued expression hw/display/omap_dss.c:1019:9: warning: returning void-valued expression hw/display/omap_dss.c:215:9: warning: returning void-valued expression hw/display/omap_dss.c:380:9: warning: returning void-valued expression hw/display/omap_dss.c:739:9: warning: returning void-valued expression hw/display/omap_dss.c:931:9: warning: returning void-valued expression hw/dma/omap_dma.c:139:5: warning: returning void-valued expression hw/dma/omap_dma.c:1505:9: warning: returning void-valued expression hw/dma/omap_dma.c:1860:9: warning: returning void-valued expression hw/gpio/omap_gpio.c:116:9: warning: returning void-valued expression hw/misc/omap_gpmc.c:627:9: warning: returning void-valued expression hw/misc/omap_l4.c:85:9: warning: returning void-valued expression hw/misc/omap_sdrc.c:95:9: warning: returning void-valued expression hw/misc/omap_tap.c:98:9: warning: returning void-valued expression hw/sd/omap_mmc.c:409:9: warning: returning void-valued expression hw/ssi/omap_spi.c:229:9: warning: returning void-valued expression hw/timer/omap_gptimer.c:447:9: warning: returning void-valued expression Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-03-11integrator/cp: Implement CARDIN and WPROT signalsJan Kiszka
This allows to use the SD card emulation of the board: Forward the signals from the pl181 top the CP control register emulation, report the current state via CP_INTREG, deliver CARDIN IRQ to the secondary interrupt controller and also support clearing that line via CP_INTREG. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Message-id: c55d9fb28d19ec83625cb0074b3b6f2e5958caf6.1426004843.git.jan.kiszka@siemens.com Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-11integrator/cp: Model CP control registers as sysbus deviceJan Kiszka
No new features yet, just encapsulation. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Message-id: 3829c7c7e01cd3ccf15a1198f114e4d675974ae0.1426004843.git.jan.kiszka@siemens.com Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-11netduino2: Add the Netduino 2 MachineAlistair Francis
This patch adds the Netduino 2 Machine. This is a Cortex-M3 based machine. Information can be found at: http://www.netduino.com/netduino2/specs.htm Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 5bd999824f14252c122c4501cc973cee986eadd7.1424175342.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-11stm32f205: Add the stm32f205 SoCAlistair Francis
This patch adds the stm32f205 SoC. This will be used by the Netduino 2 to create a machine. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 48d509747a1ea0d8a7d5480560495e679990f9d2.1424175342.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-11hw/arm/virt: fix cmdline parsing bug with CPU options and smp > 1Ard Biesheuvel
The recently introduced feature that allows 32 bit guests to be executed under KVM on a 64-bit host incorrectly handles the case where more than 1 cpu is specified using '-smp N' For instance, this invocation of qemu qemu-system-aarch64 -M virt -cpu cortex-a57,aarch64=off -smp 2 produces the following error qemu-system-aarch64: Expected key=value format, found aarch64 which is caused by the destructive parsing performed by cpu_common_parse_features(), resulting in subsequent attempts to parse the CPU option string (for each additional CPU) to fail. So duplicate the string before parsing it, and free it directly afterwards. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1425402380-10488-1-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-10Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
- scsi: improvements to error reporting and conversion to realize, Coverity/sparse fix for iscsi driver - RCU fallout: fix -daemonize and s390x system emulation - KVM: kvm_stat improvements and new man page - x86: SYSRET fix for VxWorks # gpg: Signature made Tue Mar 10 10:18:45 2015 GMT using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: x86: fix SS selector in SYSRET scsi: Convert remaining PCI HBAs to realize() scsi: Improve error reporting for invalid drive property hw: Propagate errors through qdev_prop_set_drive() scsi: Clean up duplicated error in legacy if=scsi code cpus: initialize cpu->memory_dispatch rcu: handle forks safely qemu-thread: do not use PTHREAD_MUTEX_ERRORCHECK kvm_stat: add kvm_stat.1 man page kvm_stat: add column headers to text UI iscsi: Fix check for username Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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