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2020-10-08hw/arm/virt: Implement kvm-steal-timeAndrew Jones
We add the kvm-steal-time CPU property and implement it for machvirt. A tiny bit of refactoring was also done to allow pmu and pvtime to use the same vcpu device helper functions. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20201001061718.101915-7-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-08hw/arm/virt: Move kvm pmu setup to virt_cpu_post_initAndrew Jones
Move the KVM PMU setup part of fdt_add_pmu_nodes() to virt_cpu_post_init(), which is a more appropriate location. Now fdt_add_pmu_nodes() is also named more appropriately, because it no longer does anything but fdt node creation. No functional change intended. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20201001061718.101915-5-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-08hw/arm/virt: Move post cpu realize check into its own functionAndrew Jones
We'll add more to this new function in coming patches so we also state the gic must be created and call it below create_gic(). No functional change intended. Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20201001061718.101915-4-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-08hw/arm/sbsa-ref : allocate IRQs for SMMUv3Graeme Gregory
Original commit did not allocate IRQs for the SMMUv3 in the irqmap effectively using irq 0->3 (shared with other devices). Assuming original intent was to allocate unique IRQs then add an allocation to the irqmap. Fixes: e9fdf453240 ("hw/arm: Add arm SBSA reference machine, devices part") Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20201007100732.4103790-3-graeme@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-08hw/arm/sbsa-ref : Fix SMMUv3 InitialisationGraeme Gregory
SMMUv3 has an error in a previous patch where an i was transposed to a 1 meaning interrupts would not have been correctly assigned to the SMMUv3 instance. Fixes: 48ba18e6d3f3 ("hw/arm/sbsa-ref: Simplify by moving the gic in the machine state") Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20201007100732.4103790-2-graeme@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20201001' into staging target-arm queue: * Make isar_feature_aa32_fp16_arith() handle M-profile * Fix SVE splice * Fix SVE LDR/STR * Remove ignore_memory_transaction_failures on the raspi2 * raspi: Various cleanup/refactoring # gpg: Signature made Thu 01 Oct 2020 15:46:47 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20201001: hw/arm/raspi: Remove use of the 'version' value in the board code hw/arm/raspi: Use RaspiProcessorId to set the firmware load address hw/arm/raspi: Introduce RaspiProcessorId enum hw/arm/raspi: Use more specific machine names hw/arm/raspi: Avoid using TypeInfo::class_data pointer hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState hw/arm/raspi: Load the firmware on the first core hw/arm/raspi: Display the board revision in the machine description hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2 hw/arm/bcm2835: Add more unimplemented peripherals hw/arm/raspi: Define various blocks base addresses target/arm: Fix SVE splice target/arm: Fix sve ldr/str target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile target/arm: Add ID register values for Cortex-M0 hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01hw/arm/raspi: Remove use of the 'version' value in the board codePhilippe Mathieu-Daudé
We expected the 'version' ID to match the board processor ID, but this is not always true (for example boards with revision id 0xa02042/0xa22042 are Raspberry Pi 2 with a BCM2837 SoC). This was not important because we were not modelling them, but since the recent refactor now allow to model these boards, it is safer to check the processor id directly. Remove the version check. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200924111808.77168-9-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01hw/arm/raspi: Use RaspiProcessorId to set the firmware load addressPhilippe Mathieu-Daudé
The firmware load address depends on the SoC ("processor id") used, not on the version of the board. Suggested-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200924111808.77168-8-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01hw/arm/raspi: Introduce RaspiProcessorId enumPhilippe Mathieu-Daudé
As we only support a reduced set of the REV_CODE_PROCESSOR id encoded in the board revision, define the PROCESSOR_ID values as an enum. We can simplify the board_soc_type and cores_count methods. Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200924111808.77168-7-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01hw/arm/raspi: Use more specific machine namesPhilippe Mathieu-Daudé
Now that we can instantiate different machines based on their board_rev register value, we can have various raspi2 and raspi3. In commit fc78a990ec103 we corrected the machine description. Correct the machine names too. For backward compatibility, add an alias to the previous generic name. Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200924111808.77168-6-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01hw/arm/raspi: Avoid using TypeInfo::class_data pointerPhilippe Mathieu-Daudé
Using class_data pointer to create a MachineClass is not the recommended way anymore. The correct way is to open-code the MachineClass::fields in the class_init() method. We can not use TYPE_RASPI_MACHINE::class_base_init() because it is called *before* each machine class_init(), therefore the board_rev field is not populated. We have to manually call raspi_machine_class_common_init() for each machine. This partly reverts commit a03bde3674e. Suggested-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200924111808.77168-5-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01hw/arm/raspi: Move arm_boot_info structure to RaspiMachineStatePhilippe Mathieu-Daudé
The arm_boot_info structure belong to the machine, move it to RaspiMachineState. Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200924111808.77168-4-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01hw/arm/raspi: Load the firmware on the first corePhilippe Mathieu-Daudé
The 'first_cpu' is more a QEMU accelerator-related concept than a variable the machine requires to use. Since the machine is aware of its CPUs, directly use the first one to load the firmware. Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200924111808.77168-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01hw/arm/raspi: Display the board revision in the machine descriptionPhilippe Mathieu-Daudé
Display the board revision in the machine description. Before: $ qemu-system-aarch64 -M help | fgrep raspi raspi2 Raspberry Pi 2B raspi3 Raspberry Pi 3B After: raspi2 Raspberry Pi 2B (revision 1.1) raspi3 Raspberry Pi 3B (revision 1.2) Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200924111808.77168-2-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2Philippe Mathieu-Daudé
Commit 1c3db49d39 added the raspi3, which uses the same peripherals than the raspi2 (but with different ARM cores). The raspi3 was introduced without the ignore_memory_transaction_failures flag. Almost 2 years later, the machine is usable running U-Boot and Linux. In commit 00cbd5bd74 we mapped a lot of unimplemented devices, commit d442d95f added thermal block and commit 0e5bbd7406 the system timer. As we are happy with the raspi3, let's remove this flag on the raspi2. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200921034729.432931-4-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-10-01hw/arm/bcm2835: Add more unimplemented peripheralsPhilippe Mathieu-Daudé
The bcm2835-v3d is used since Linux 4.7, see commit 49ac67e0c39c ("ARM: bcm2835: Add VC4 to the device tree"), and the bcm2835-txp since Linux 4.19, see commit b7dd29b401f5 ("ARM: dts: bcm283x: Add Transposer block"). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20200921034729.432931-3-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-30arm: use acpi_dsdt_add_gpexGerd Hoffmann
Fill gpex config struct from memory map, then call the new acpi_dsdt_add_gpex helper function. No functional change. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20200928104256.9241-4-kraxel@redhat.com
2020-09-30move MemMapEntryGerd Hoffmann
It is defined twice already. Move to a common header file to remove duplication and make it available to everybody. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20200928104256.9241-2-kraxel@redhat.com
2020-09-25load_elf: Remove unused address variables from callersBALATON Zoltan
Several callers of load_elf() pass pointers for lowaddr and highaddr parameters which are then not used for anything. This may stem from a misunderstanding that load_elf need a value here but in fact it can take NULL to ignore these values. Remove such unused variables and pass NULL instead from callers that don't need these. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Message-Id: <20200705174020.BDD0174633F@zero.eik.bme.hu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-22xlnx-zcu102: Register properties as class propertiesEduardo Habkost
Class properties make QOM introspection simpler and easier, as they don't require an object to be instantiated. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200921221045.699690-20-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-22qom: simplify object_find_property / object_class_find_propertyDaniel P. Berrangé
When debugging QEMU it is often useful to put a breakpoint on the error_setg_internal method impl. Unfortunately the object_property_add / object_class_property_add methods call object_property_find / object_class_property_find methods to check if a property exists already before adding the new property. As a result there are a huge number of calls to error_setg_internal on startup of most QEMU commands, making it very painful to set a breakpoint on this method. Most callers of object_find_property and object_class_find_property, however, pass in a NULL for the Error parameter. This simplifies the methods to remove the Error parameter entirely, and then adds some new wrapper methods that are able to raise an Error when needed. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200914135617.1493072-1-berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-18Use OBJECT_DECLARE_SIMPLE_TYPE when possibleEduardo Habkost
This converts existing DECLARE_INSTANCE_CHECKER usage to OBJECT_DECLARE_SIMPLE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareSimpleType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-6-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-18Use OBJECT_DECLARE_TYPE when possibleEduardo Habkost
This converts existing DECLARE_OBJ_CHECKERS usage to OBJECT_DECLARE_TYPE when possible. $ ./scripts/codeconverter/converter.py -i \ --pattern=AddObjectDeclareType $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Paul Durrant <paul@xen.org> Message-Id: <20200916182519.415636-5-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-18Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20200918' ↵Peter Maydell
into staging Aspeed patches : * Couple of cleanups * New machine properties to define the flash models # gpg: Signature made Fri 18 Sep 2020 08:23:19 BST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20200918: misc: aspeed_scu: Update AST2600 silicon id register hw/arm/aspeed: Add machine properties to define the flash models hw/arm/aspeed: Map the UART5 device unconditionally Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-18hw/arm/aspeed: Add machine properties to define the flash modelsCédric Le Goater
Some machines don't have much differences a part from the flash model being used. Introduce new machine properties to change them from the command line. For instance, to start the ast2500-evb machine with a different FMC chip and a 64M SPI chip, use : -M ast2500-evb,fmc-model=mx25l25635e,spi-model=mx66u51235f Cc: 郁雷 <yulei.sh@bytedance.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Lei YU <yulei.sh@bytedance.com> Message-Id: <20200915054859.2338477-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-09-18hw/arm/aspeed: Map the UART5 device unconditionallyPhilippe Mathieu-Daudé
The UART5 is present on the machine regardless there is a character device connected to it. Map it unconditionally. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20200905212415.760452-1-f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2020-09-17acpi: move acpi_dsdt_add_power_button() to gedGerd Hoffmann
Allow reuse for microvm. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20200915120909.20838-7-kraxel@redhat.com
2020-09-14hw/arm/npcm7xx: add board setup stub for CPU and UART clocksHavard Skinnemoen
When booting directly into a kernel, bypassing the boot loader, the CPU and UART clocks are not set up correctly. This makes the system appear very slow, and causes the initrd boot test to fail when optimization is off. The UART clock must run at 24 MHz. The default 25 MHz reference clock cannot achieve this, so switch to PLL2/2 @ 480 MHz, which works perfectly with the default /20 divider. The CPU clock should run at 800 MHz, so switch it to PLL1/2. PLL1 runs at 800 MHz by default, so we need to double the feedback divider as well to make it run at 1600 MHz (so PLL1/2 runs at 800 MHz). We don't bother checking for PLL lock because we know our emulated PLLs lock instantly. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-13-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsjHavard Skinnemoen
This allows these NPCM7xx-based boards to boot from a flash image, e.g. one built with OpenBMC. For example like this: IMAGE=${OPENBMC}/build/tmp/deploy/images/gsj/image-bmc qemu-system-arm -machine quanta-gsj -nographic \ -drive file=${IMAGE},if=mtd,bus=0,unit=0,format=raw,snapshot=on Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200911052101.2602693-12-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/ssi: NPCM7xx Flash Interface Unit device modelHavard Skinnemoen
This implements a device model for the NPCM7xx SPI flash controller. Direct reads and writes, and user-mode transactions have been tested in various modes. Protection features are not implemented yet. All the FIU instances are available in the SoC's address space, regardless of whether or not they're connected to actual flash chips. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-11-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/mem: Stubbed out NPCM7xx Memory Controller modelHavard Skinnemoen
This just implements the bare minimum to cause the boot block to skip memory initialization. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-10-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/nvram: NPCM7xx OTP device modelHavard Skinnemoen
This supports reading and writing OTP fuses and keys. Only fuse reading has been tested. Protection is not implemented. Reviewed-by: Avi Fishman <avi.fishman@nuvoton.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-9-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: Load -bios image as a boot ROM for npcm7xxHavard Skinnemoen
If a -bios option is specified on the command line, load the image into the internal ROM memory region, which contains the first instructions run by the CPU after reset. If -bios is not specified, the vbootrom included with qemu is loaded by default. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-8-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: Add two NPCM7xx-based machinesHavard Skinnemoen
This adds two new machines, both supported by OpenBMC: - npcm750-evb: Nuvoton NPCM750 Evaluation Board. - quanta-gsj: A board with a NPCM730 chip. They rely on the NPCM7xx SoC device to do the heavy lifting. They are almost completely identical at the moment, apart from the SoC type, which currently only changes the reset contents of one register (GCR.MDLR), but they might grow apart a bit more as more functionality is added. Both machines can boot the Linux kernel into /bin/sh. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-6-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: Add NPCM730 and NPCM750 SoC modelsHavard Skinnemoen
The Nuvoton NPCM7xx SoC family are used to implement Baseboard Management Controllers in servers. While the family includes four SoCs, this patch implements limited support for two of them: NPCM730 (targeted for Data Center applications) and NPCM750 (targeted for Enterprise applications). This patch includes little more than the bare minimum needed to boot a Linux kernel built with NPCM7xx support in direct-kernel mode: - Two Cortex-A9 CPU cores with built-in periperhals. - Global Configuration Registers. - Clock Management. - 3 Timer Modules with 5 timers each. - 4 serial ports. The chips themselves have a lot more features, some of which will be added to the model at a later stage. Reviewed-by: Tyrone Ting <kfting@nuvoton.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-5-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/misc: Add NPCM7xx System Global Control Registers device modelHavard Skinnemoen
Implement a device model for the System Global Control Registers in the NPCM730 and NPCM750 BMC SoCs. This is primarily used to enable SMP boot (the boot ROM spins reading the SCRPAD register) and DDR memory initialization; other registers are best effort for now. The reset values of the MDLR and PWRON registers are determined by the SoC variant (730 vs 750) and board straps respectively. Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alexander Bulekov <alxndr@bu.edu> Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com> Message-id: 20200911052101.2602693-2-hskinnemoen@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm: versal-virt: Correct the tx/rx GEM clocksEdgar E. Iglesias
Correct the GEMs tx/rx clocks to use the 125Mhz fixed-clock. This matches the setup with the fixed-link 100Mbit PHY. It also avoids the following warnings from the Linux kernel driver: eth0: unable to generate target frequency: 125000000 Hz Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20200909174647.662864-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-14hw/arm/mps2: New board model mps2-an500Peter Maydell
Implement a model of the MPS2 with the AN500 firmware. This is similar to the AN385, with the following differences: * Cortex-M7 CPU * PSRAM is at 0x6000_0000 * Ethernet is at 0xa000_0000 * No zbt_boot_ctrl remapping of the low 16K (but QEMU doesn't implement this anyway) * no "block RAM" at 0x01000000 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200903202048.15370-3-peter.maydell@linaro.org
2020-09-14hw/arm/mps2: New board model mps2-an386Peter Maydell
Implement a model of the MPS2 with the AN386 firmware. This is essentially identical to the AN385 firmware, but it has a Cortex-M4 rather than a Cortex-M3. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200903202048.15370-2-peter.maydell@linaro.org
2020-09-13Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging This PR includes multiple fixes and features for RISC-V: - Fixes a bug in printing trap causes - Allows 16-bit writes to the SiFive test device. This fixes the failure to reboot the RISC-V virt machine - Support for the Microchip PolarFire SoC and Icicle Kit - A reafactor of RISC-V code out of hw/riscv # gpg: Signature made Thu 10 Sep 2020 19:08:06 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits) hw/riscv: Sort the Kconfig options in alphabetical order hw/riscv: Drop CONFIG_SIFIVE hw/riscv: Always build riscv_hart.c hw/riscv: Move sifive_test model to hw/misc hw/riscv: Move sifive_uart model to hw/char hw/riscv: Move riscv_htif model to hw/char hw/riscv: Move sifive_plic model to hw/intc hw/riscv: Move sifive_clint model to hw/intc hw/riscv: Move sifive_gpio model to hw/gpio hw/riscv: Move sifive_u_otp model to hw/misc hw/riscv: Move sifive_u_prci model to hw/misc hw/riscv: Move sifive_e_prci model to hw/misc hw/riscv: sifive_u: Connect a DMA controller hw/riscv: clint: Avoid using hard-coded timebase frequency hw/riscv: microchip_pfsoc: Hook GPIO controllers hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 hw/net: cadence_gem: Add a new 'phy-addr' property hw/riscv: microchip_pfsoc: Connect a DMA controller hw/dma: Add SiFive platform DMA controller emulation ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/riscv/trace-events
2020-09-12Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-branch-for-5.2-pull-request' into staging trivial patches pull request 20200911 # gpg: Signature made Fri 11 Sep 2020 20:32:27 BST # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-5.2-pull-request: target/i386/kvm: Add missing fallthrough comment util/hexdump: Reorder qemu_hexdump() arguments util/hexdump: Convert to take a void pointer argument hw/arm/pxa2xx: Add missing fallthrough comment target/i386/kvm: Rename host_tsx_blacklisted() as host_tsx_broken() test-vmstate: remove unnecessary code in match_interval_mapping_node hw: hyperv: vmbus: Fix 32bit compilation kconfig: fix comment referring to old Makefiles meson.build: tweak sdl-image error message hw/net/e1000e: Remove duplicated write handler for FLSWDATA register hw/net/e1000e: Remove overwritten read handler for STATUS register Makefile: Skip the meson subdir in cscope/TAGS/ctags Makefile: Drop extra phony cscope hw/gpio/max7310: Replace disabled printf() by qemu_log_mask(UNIMP) hw/gpio/omap_gpio: Replace fprintf() by qemu_log_mask(GUEST_ERROR) hw/acpi/tco: Remove unused definitions hw/isa/isa-bus: Replace hw_error() by assert() hw/mips/fuloong2e: Convert pointless error message to an assert() Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # net/colo-compare.c
2020-09-11hw/arm/pxa2xx: Add missing fallthrough commentThomas Huth
Let's make this file compilable with -Werror=implicit-fallthrough : Looking at the code, it seems like the fallthrough is intended here, so we should add the corresponding "/* fallthrough */" comment here. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20200911121844.404434-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-09hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23Bin Meng
When cadence_gem model was created for Xilinx boards, the PHY address was hard-coded to 23 in the GEM model. Now that we have introduced a property we can use that to tell GEM model what our PHY address is. Change all boards' GEM 'phy-addr' property value to 23, and set the PHY address default value to 0 in the GEM model. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-13-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost
Generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-13-ehabkost@redhat.com> Message-Id: <20200831210740.126168-14-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost
Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE. Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]') which will split "typdef struct { ... } TypedefName" declarations. Followed by: $ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \ $(git grep -l '' -- '*.[ch]') which will: - move the typedefs and #defines above the type check macros - add missing #include "qom/object.h" lines if necessary Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-9-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-10-ehabkost@redhat.com> Message-Id: <20200831210740.126168-11-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-09-08configure: do not include dependency flags in QEMU_CFLAGS and LIBSPaolo Bonzini
All Meson executables should specify their dependencies explicitly, either directly or indirectly via declare_dependency. Makefiles instead did not propagate dependencies correctly from static libraries, for example. Therefore, flags for dependencies need not be included in QEMU_CFLAGS. LIBS is not used at all, so drop that one as well. In a few cases the dependencies were not yet specified, so add them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-09-03Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20200901' ↵Peter Maydell
into staging Various fixes of Aspeed machines : * New Supermicro X11 BMC machine (Erik) * Fixed valid access size on AST2400 SCU * Improved robustness of the ftgmac100 model. * New flash models in m25p80 (Igor) * Fixed reset sequence of SDHCI/eMMC controllers * Improved support of the AST2600 SDMC (Joel) * Couple of SMC cleanups # gpg: Signature made Tue 01 Sep 2020 13:39:20 BST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20200901: hw: add a number of SPI-flash's of m25p80 family arm: aspeed: add strap define `25HZ` of AST2500 aspeed/smc: Open AHB window of the second chip of the AST2600 FMC controller aspeed/sdmc: Simplify calculation of RAM bits aspeed/sdmc: Allow writes to unprotected registers aspeed/sdmc: Perform memory training ftgmac100: Improve software reset ftgmac100: Fix integer overflow in ftgmac100_do_tx() ftgmac100: Check for invalid len and address before doing a DMA transfer ftgmac100: Change interrupt status when a DMA error occurs ftgmac100: Fix interrupt status "Packet moved to RX FIFO" ftgmac100: Fix interrupt status "Packet transmitted on ethernet" ftgmac100: Fix registers that can be read aspeed/sdhci: Fix reset sequence aspeed/smc: Fix max_slaves of the legacy SMC device aspeed/smc: Fix MemoryRegionOps definition hw/arm/aspeed: Add board model for Supermicro X11 BMC aspeed/scu: Fix valid access size on AST2400 m25p80: Add support for n25q512ax3 m25p80: Return the JEDEC ID twice for mx25l25635e Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-01Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20200901' into staging target-arm queue: * Implement fp16 support for AArch32 VFP and Neon * hw/arm/sbsa-ref: add "reg" property to DT cpu nodes * hw/arm/sbsa-ref : Add embedded controller in secure memory # gpg: Signature made Tue 01 Sep 2020 16:17:23 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200901: (47 commits) hw/arm/sbsa-ref : Add embedded controller in secure memory hw/misc/sbsa_ec : Add an embedded controller for sbsa-ref hw/arm/sbsa-ref: add "reg" property to DT cpu nodes target/arm: Enable FP16 in '-cpu max' target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations target/arm: Implement fp16 for Neon VRINTX target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode target/arm: Implement fp16 for Neon VCVT with rounding modes target/arm: Implement fp16 for Neon VCVT fixed-point target/arm: Convert Neon VCVT fixed-point to gvec target/arm: Implement fp16 for Neon float-integer VCVT target/arm: Implement fp16 for Neon pairwise fp ops target/arm: Implement fp16 for Neon VRSQRTS target/arm: Implement fp16 for Neon VRECPS target/arm: Implement fp16 for Neon fp compare-vs-0 target/arm: Implement fp16 for Neon VFMA, VMFS target/arm: Implement fp16 for Neon VMLA, VMLS operations target/arm: Implement fp16 for Neon VMAXNM, VMINNM ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-01hw/arm/sbsa-ref : Add embedded controller in secure memoryGraeme Gregory
Add the previously created sbsa-ec device to the sbsa-ref machine in secure memory so the PSCI implementation in ARM-TF can access it, but not expose it to non secure firmware or OS except by via ARM-TF. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com> Tested-by: Leif Lindholm <leif@nuviainc.com> Message-id: 20200826141952.136164-3-graeme@nuviainc.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-09-01hw/arm/sbsa-ref: add "reg" property to DT cpu nodesLeif Lindholm
The sbsa-ref platform uses a minimal device tree to pass amount of memory as well as number of cpus to the firmware. However, when dumping that minimal dtb (with -M sbsa-virt,dumpdtb=<file>), the resulting blob generates a warning when decompiled by dtc due to lack of reg property. Add a simple reg property per cpu, representing a 64-bit MPIDR_EL1. This also ends up being cleaner than having the firmware calculating its own IDs for generating APCI. Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200827124335.30586-1-leif@nuviainc.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-26 21:58:29 +0000