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2022-07-12block: Change blk_{pread,pwrite}() param orderAlberto Faria
Swap 'buf' and 'bytes' around for consistency with blk_co_{pread,pwrite}(), and in preparation to implement these functions using generated_co_wrapper. Callers were updated using this Coccinelle script: @@ expression blk, offset, buf, bytes, flags; @@ - blk_pread(blk, offset, buf, bytes, flags) + blk_pread(blk, offset, bytes, buf, flags) @@ expression blk, offset, buf, bytes, flags; @@ - blk_pwrite(blk, offset, buf, bytes, flags) + blk_pwrite(blk, offset, bytes, buf, flags) It had no effect on hw/block/nand.c, presumably due to the #if, so that file was updated manually. Overly-long lines were then fixed by hand. Signed-off-by: Alberto Faria <afaria@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220705161527.1054072-4-afaria@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2022-07-12block: Add a 'flags' param to blk_pread()Alberto Faria
For consistency with other I/O functions, and in preparation to implement it using generated_co_wrapper. Callers were updated using this Coccinelle script: @@ expression blk, offset, buf, bytes; @@ - blk_pread(blk, offset, buf, bytes) + blk_pread(blk, offset, buf, bytes, 0) It had no effect on hw/block/nand.c, presumably due to the #if, so that file was updated manually. Overly-long lines were then fixed by hand. Signed-off-by: Alberto Faria <afaria@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20220705161527.1054072-3-afaria@redhat.com> Signed-off-by: Hanna Reitz <hreitz@redhat.com>
2022-07-07hw/arm/virt: dt: add rng-seed propertyJason A. Donenfeld
In 60592cfed2 ("hw/arm/virt: dt: add kaslr-seed property"), the kaslr-seed property was added, but the equally as important rng-seed property was forgotten about, which has identical semantics for a similar purpose. This commit implements it in exactly the same way as kaslr-seed. It then changes the name of the disabling option to reflect that this has more to do with randomness vs determinism, rather than something particular about kaslr. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> [PMM: added deprecated.rst section for the deprecation] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-30hw/misc/aspeed: Add PECI controllerPeter Delevoryas
This introduces a really basic PECI controller that responses to commands by always setting the response code to success and then raising an interrupt to indicate the command is done. This helps avoid getting hit with constant errors if the driver continuously attempts to send a command and keeps timing out. The AST2400 and AST2500 only included registers up to 0x5C, not 0xFC. They supported PECI 1.1, 2.0, and 3.0. The AST2600 and AST1030 support PECI 4.0, which includes more read/write buffer registers from 0x80 to 0xFC to support 64-byte mode. This patch doesn't attempt to handle that, or to create a different version of the controller for the different generations, since it's only implementing functionality that is common to all generations. The basic sequence of events is that the firmware will read and write to various registers and then trigger a command by setting the FIRE bit in the command register (similar to the I2C controller). Then the firmware waits for an interrupt from the PECI controller, expecting the interrupt status register to be filled in with info on what happened. If the command was transmitted and received successfully, then response codes from the host CPU will be found in the data buffer registers. Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220630045133.32251-12-me@pjd.dev> [ clg: s/sysbus_mmio_map/aspeed_mmio_map/ ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30hw/i2c: add asynchronous sendKlaus Jensen
Add an asynchronous version of i2c_send() that requires the slave to explicitly acknowledge on the bus with i2c_ack(). The current master must use the new i2c_start_send_async() to indicate that it wants to do an asynchronous transfer. This allows the i2c core to check if the target slave supports this or not. This approach relies on adding a new enum i2c_event member, which is why a bunch of other devices needs changes in their event handling switches. Signed-off-by: Klaus Jensen <k.jensen@samsung.com> Message-Id: <20220601210831.67259-5-its@irrelevant.dk> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220630045133.32251-6-me@pjd.dev> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30hw/arm/aspeed: firework: add I2C MUXes for VR channelsJae Hyun Yoo
Add 2-level cascaded I2C MUXes for SOC VR channels into the Firework machine. Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220627154703.148943-8-quic_jaehyoo@quicinc.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30hw/arm/aspeed: firework: Add Thermal DiodesMaheswara Kurapati
Add Thermal Diodes for Firework machine. Signed-off-by: Maheswara Kurapati <quic_mkurapat@quicinc.com> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220627154703.148943-7-quic_jaehyoo@quicinc.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30hw/arm/aspeed: Add MAX31785 Fan controllersMaheswara Kurapati
Add MAX31785 fan controllers in machines so that the Linux driver populates the sysfs interface. Firework has two MAX31785 Fan controllers at 0x52, and 0x54 on bus 9. Witherspoon has one at 0x52 on bus 3. Rainier has one at 0x52 on bus 7. Signed-off-by: Maheswara Kurapati <quic_mkurapat@quicinc.com> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220627154703.148943-6-quic_jaehyoo@quicinc.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30hw/arm/aspeed: add Qualcomm Firework BMC machineGraeme Gregory
Add base for Qualcomm Firework BMC machine. Signed-off-by: Graeme Gregory <quic_ggregory@quicinc.com> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220627154703.148943-3-quic_jaehyoo@quicinc.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30hw/arm/aspeed: add support for the Qualcomm DC-SCM v1 boardJae Hyun Yoo
Add qcom-dc-scm-v1 board support. Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220627154703.148943-2-quic_jaehyoo@quicinc.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30aspeed: Remove use of qemu_get_cpuPeter Delevoryas
Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220624003701.1363500-6-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30aspeed: Map unimplemented devices in SoC memoryPeter Delevoryas
Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220624003701.1363500-5-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30aspeed: Remove usage of sysbus_mmio_mapPeter Delevoryas
sysbus_mmio_map maps devices into "get_system_memory()". With the new SoC memory attribute, we want to make sure that each device is mapped into the SoC memory. In single SoC machines, the SoC memory is the same as "get_system_memory()", but in multi SoC machines it will be different. Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220624003701.1363500-4-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30aspeed: Add memory property to Aspeed SoCPeter Delevoryas
Multi-SoC machines can use this property to specify a memory container for each SoC. Single SoC machines will just specify get_system_memory(). Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220624003701.1363500-3-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30aspeed: Set CPU memory property explicitlyPeter Delevoryas
Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20220624003701.1363500-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30aspeed: Set the dram container at the SoC levelCédric Le Goater
Currently, the Aspeed machines allocate a ram container region in which the machine ram region is mapped. See commit ad1a9782186d ("aspeed: add a RAM memory region container"). An extra region is mapped after ram in the ram container to catch invalid access done by FW. That's how FW determines the size of ram. See commit ebe31c0a8ef7 ("aspeed: add a max_ram_size property to the memory controller"). Let's move all the logic under the SoC where it should be. It will also ease the work on multi SoC support. Reviewed-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20220623202123.3972977-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-27target/arm: Extend arm_pamax to more than aarch64Richard Henderson
Move the code from hw/arm/virt.c that is supposed to handle v7 into the one function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reported-by: He Zhe <zhe.he@windriver.com> Message-id: 20220619001541.131672-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-22aspeed: Add I2C buses to AST1030 modelTroy Lee
Instantiate the I2C buses in AST1030 model and create two slave device for ast1030-evb. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> [ clg : - adapted to current AST1030 upstream models - changed AST2600 to AST1030 in comment - fixed typo in commit log ] Message-Id: <20220324100439.478317-3-troy_lee@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed: Remove fake RTC device on ast2500-evbCédric Le Goater
The board has no such device. It might have been useful for some tests in the past, it's not anymore and the same can be achieved on the command line. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-10hw/core/loader: return image sizes as ssize_tJamie Iles
Various loader functions return an int which limits images to 2GB which is fine for things like a BIOS/kernel image, but if we want to be able to load memory images or large ramdisks then any file over 2GB would silently fail to load. Cc: Luc Michel <lmichel@kalray.eu> Signed-off-by: Jamie Iles <jamie@nuviainc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Luc Michel <lmichel@kalray.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20211111141141.3295094-2-jamie@nuviainc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-06-08xlnx-zynqmp: fix the irq mapping for the display port and its dmaFrederic Konrad
When the display port has been initially implemented the device driver wasn't using interrupts. Now that the display port driver waits for vblank interrupt it has been noticed that the irq mapping is wrong. So use the value from the linux device tree and the ultrascale+ reference manual. Signed-off-by: Frederic Konrad <fkonrad@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220601172353.3220232-5-fkonrad@xilinx.com [PMM: refold lines in commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-25hw/arm/aspeed: Add i2c devices for AST2600 EVBHoward Chiu
Add EEPROM and LM75 temperature sensor according to hardware schematic Signed-off-by: Howard Chiu <howard_chiu@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-25hw/gpio: Add ASPEED GPIO model for AST1030Jamin Lin
AST1030 integrates one set of Parallel GPIO Controller with maximum 151 control pins, which are 21 groups (A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6 R7 S0 S3 S4 S5 S6 S7 ) and the group T and U are input only. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220525053444.27228-3-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-25hw: aspeed: Init all UART's with serial devicesPeter Delevoryas
Background: AspeedMachineClass.uart_default specifies the serial console UART, which usually corresponds to the "stdout-path" in the device tree. The default value is UART5, since most boards use UART5 for this: amc->uart_default = ASPEED_DEV_UART5; Users can override AspeedMachineClass.uart_default in their board's machine class init to specify something besides UART5. For example, for fuji-bmc: amc->uart_default = ASPEED_DEV_UART1; We only connect this one UART, of the 5 UART's on the AST2400 and AST2500 and the 13 UART's on the AST2600 and AST1030, to a serial device that QEMU users can use. None of the other UART's are initialized, and the only way to override this attribute is by creating a specialized board definition, requiring QEMU source code changes and rebuilding. The result of this is that if you want to get serial console output on a board that uses UART3, you need to add a board definition. This was encountered by Zev in OpenBMC. [1] Changes: This commit initializes all of the UART's present on each Aspeed chip with serial devices and allows the QEMU user to connect as many or few as they like to serial devices. For example, you can still run QEMU and just connect stdout to the machine's default UART, without specifying any additional serial devices: qemu-system-arm -machine fuji-bmc \ -drive file=fuji.mtd,format=raw,if=mtd \ -nographic However, if you don't want to add a special machine definition, you can now manually configure UART1 to connect to stdout and get serial console output, even if the machine's default is UART5: qemu-system-arm -machine ast2600-evb \ -drive file=fuji.mtd,format=raw,if=mtd \ -serial null -serial mon:stdio -display none In the example above, the first "-serial null" argument is connected to UART5, and "-serial mon:stdio" is connected to UART1. Another example: you can get serial console output from Wedge100, which uses UART3, by reusing the palmetto AST2400 machine and rewiring the serial device arguments: qemu-system-arm -machine palmetto-bmc \ -drive file=wedge100.mtd,format=raw,if=mtd \ -serial null -serial null -serial null \ -serial mon:stdio -display none There is a slight change in behavior introduced with this change: now, each UART's memory-mapped IO region will have a serial device model connected to it. Previously, all reads and writes to those regions would be ineffective and return zero values, but now some values will be nonzero, even when the user doesn't connect a serial device backend (like a socket, file, etc). For example, the line status register might indicate that the transmit buffer is empty now, whereas previously it might have always indicated it was full. [1] https://lore.kernel.org/openbmc/YnzGnWjkYdMUUNyM@hatter.bewilderbeest.net/ [2] https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.mtd [3] https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge100.mtd Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516062328.298336-6-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-25hw: aspeed: Introduce common UART init functionPeter Delevoryas
Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516062328.298336-5-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-25hw: aspeed: Ensure AST1030 respects uart-defaultPeter Delevoryas
The AST1030 machine initialization was not respecting the Aspeed SoC property "uart-default", which specifies which UART should be connected to the first serial device, it was just always connecting UART5. This doesn't change any behavior, because the default value for "uart-default" is UART5, but it makes it possible to override this in new machine definitions using the AST1030. Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516062328.298336-4-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-25hw: aspeed: Add uarts_num SoC attributePeter Delevoryas
AST2400 and AST2500 have 5 UART's, while the AST2600 and AST1030 have 13. Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516062328.298336-3-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-25hw: aspeed: Add missing UART'sPeter Delevoryas
This adds the missing UART memory and IRQ mappings for the AST2400, AST2500, AST2600, and AST1030. This also includes the new UART interfaces added in the AST2600 and AST1030 from UART6 to UART13. The addresses and interrupt numbers for these two later chips are identical. Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516062328.298336-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-25aspeed: Introduce a get_irq AspeedSoCClass methodCédric Le Goater
and make routine aspeed_soc_get_irq() common to all SoCs. This will be useful to share code. Cc: Jamin Lin <jamin_lin@aspeedtech.com> Cc: Peter Delevoryas <pdel@fb.com> Reviewed-by: Peter Delevoryas <pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516055620.2380197-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-25hw/arm/aspeed: Add fby35 machine typePeter Delevoryas
Add the 'fby35-bmc' machine type based on the kernel DTS[1] and userspace i2c setup scripts[2]. Undefined values are inherited from the AST2600-EVB. Reference images can be found in Facebook OpenBMC Github Release assets as "fby35.mtd". [3] You can boot the reference images as follows (fby35 uses dual-flash): qemu-system-arm -machine fby35-bmc \ -drive file=fby35.mtd,format=raw,if=mtd \ -drive file=fby35.mtd,format=raw,if=mtd \ -nographic [1] https://github.com/facebook/openbmc-linux/blob/412d5053258007117e94b1e36015aefc1301474b/arch/arm/boot/dts/aspeed-bmc-facebook-fby35.dts [2] https://github.com/facebook/openbmc/blob/e2294ff5d31dd65c248fe396a385286d6d5c463d/meta-facebook/meta-fby35/recipes-fby35/plat-utils/files/setup-dev.sh [3] https://github.com/facebook/openbmc/releases Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220503225925.1798324-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-19target/arm: Use FIELD definitions for CPACR, CPTR_ELxRichard Henderson
We had a few CPTR_* bits defined, but missed quite a few. Complete all of the fields up to ARMv9.2. Use FIELD_EX64 instead of manual extract32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220517054850.177016-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-19ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACYPeter Maydell
The traditional ptimer behaviour includes a collection of weird edge case behaviours. In 2016 we improved the ptimer implementation to fix these and generally make the behaviour more flexible, with ptimers opting in to the new behaviour by passing an appropriate set of policy flags to ptimer_init(). For backwards-compatibility, we defined PTIMER_POLICY_DEFAULT (which sets no flags) to give the old weird behaviour. This turns out to be a poor choice of name, because people writing new devices which use ptimers are misled into thinking that the default is probably a sensible choice of flags, when in fact it is almost always not what you want. Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY and beef up the comment to more clearly say that new devices should not be using it. The code-change part of this commit was produced by sed -i -e 's/PTIMER_POLICY_DEFAULT/PTIMER_POLICY_LEGACY/g' $(git grep -l PTIMER_POLICY_DEFAULT) with the exception of a test name string change in tests/unit/ptimer-test.c which was added manually. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220516103058.162280-1-peter.maydell@linaro.org
2022-05-19hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb nodePeter Maydell
The virt board generates a gpio-keys node in the dtb, but it incorrectly gives this node #size-cells and #address-cells properties. If you dump the dtb with 'machine dumpdtb=file.dtb' and run it through dtc, dtc will warn about this: Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Remove the bogus properties. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220513131316.4081539-3-peter.maydell@linaro.org
2022-05-19hw/arm/virt: Fix incorrect non-secure flash dtb node namePeter Maydell
In the virt board with secure=on we put two nodes in the dtb for flash devices: one for the secure-only flash, and one for the non-secure flash. We get the reg properties for these correct, but in the DT node name, which by convention includes the base address of devices, we used the wrong address. Fix it. Spotted by dtc, which will complain Warning (unique_unit_address): /flash@0: duplicate unit-address (also used in node /secflash@0) if you dump the dtb from QEMU with -machine dumpdtb=file.dtb and then decompile it with dtc. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220513131316.4081539-2-peter.maydell@linaro.org
2022-05-13hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxlJonathan Cameron
This adds code to instantiate the slightly extended ACPI root port description in DSDT as per the CXL 2.0 specification. Basically a cut and paste job from the i386/pc code. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220429144110.25167-30-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-05-12machine: use QAPI struct for boot configurationPaolo Bonzini
As part of converting -boot to a property with a QAPI type, define the struct and use it throughout QEMU to access boot configuration. machine_boot_parse takes care of doing the QemuOpts->QAPI conversion by hand, for now. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20220414165300.555321-2-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-05-09hw/arm/virt: Fix CPU's default NUMA node IDGavin Shan
When CPU-to-NUMA association isn't explicitly provided by users, the default one is given by mc->get_default_cpu_node_id(). However, the CPU topology isn't fully considered in the default association and this causes CPU topology broken warnings on booting Linux guest. For example, the following warning messages are observed when the Linux guest is booted with the following command lines. /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \ -accel kvm -machine virt,gic-version=host \ -cpu host \ -smp 6,sockets=2,cores=3,threads=1 \ -m 1024M,slots=16,maxmem=64G \ -object memory-backend-ram,id=mem0,size=128M \ -object memory-backend-ram,id=mem1,size=128M \ -object memory-backend-ram,id=mem2,size=128M \ -object memory-backend-ram,id=mem3,size=128M \ -object memory-backend-ram,id=mem4,size=128M \ -object memory-backend-ram,id=mem4,size=384M \ -numa node,nodeid=0,memdev=mem0 \ -numa node,nodeid=1,memdev=mem1 \ -numa node,nodeid=2,memdev=mem2 \ -numa node,nodeid=3,memdev=mem3 \ -numa node,nodeid=4,memdev=mem4 \ -numa node,nodeid=5,memdev=mem5 : alternatives: patching kernel code BUG: arch topology borken the CLS domain not a subset of the MC domain <the above error log repeats> BUG: arch topology borken the DIE domain not a subset of the NODE domain With current implementation of mc->get_default_cpu_node_id(), CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately. That's incorrect because CPU#0/1/2 should be associated with same NUMA node because they're seated in same socket. This fixes the issue by considering the socket ID when the default CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids(). With this applied, no more CPU topology broken warnings are seen from the Linux guest. The 6 CPUs are associated with NODE#0/1, but there are no CPUs associated with NODE#2/3/4/5. Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Message-id: 20220503140304.855514-6-gshan@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09hw/arm/virt: Consider SMP configuration in CPU topologyGavin Shan
Currently, the SMP configuration isn't considered when the CPU topology is populated. In this case, it's impossible to provide the default CPU-to-NUMA mapping or association based on the socket ID of the given CPU. This takes account of SMP configuration when the CPU topology is populated. The die ID for the given CPU isn't assigned since it's not supported on arm/virt machine. Besides, the used SMP configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted to avoid testing failure Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Yanan Wang <wangyanan55@huawei.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20220503140304.855514-4-gshan@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09hw/arm: add versioning to sbsa-ref machine DTLeif Lindholm
The sbsa-ref machine is continuously evolving. Some of the changes we want to make in the near future, to align with real components (e.g. the GIC-700), will break compatibility for existing firmware. Introduce two new properties to the DT generated on machine generation: - machine-version-major To be incremented when a platform change makes the machine incompatible with existing firmware. - machine-version-minor To be incremented when functionality is added to the machine without causing incompatibility with existing firmware. to be reset to 0 when machine-version-major is incremented. This versioning scheme is *neither*: - A QEMU versioned machine type; a given version of QEMU will emulate a given version of the platform. - A reflection of level of SBSA (now SystemReady SR) support provided. The version will increment on guest-visible functional changes only, akin to a revision ID register found on a physical platform. These properties are both introduced with the value 0. (Hence, a machine where the DT is lacking these nodes is equivalent to version 0.0.) Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Radoslaw Biernacki <rad@semihalf.com> Cc: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09target/arm: Define neoverse-n1Richard Henderson
Enable the n1 for virt and sbsa board use. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09target/arm: Define cortex-a76Richard Henderson
Enable the a76 for virt and sbsa board use. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Replace sentinels with ARRAY_SIZE in cpregs.hRichard Henderson
Remove a possible source of error by removing REGINFO_SENTINEL and using ARRAY_SIZE (convinently hidden inside a macro) to find the end of the set of regs being registered or modified. The space saved by not having the extra array element reduces the executable's .data.rel.ro section by about 9k. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-05target/arm: Split out cpregs.hRichard Henderson
Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-02hw/arm/aspeed: fix AST2500/AST2600 EVB fmc modelJae Hyun Yoo
Current fmc model of AST2500 EVB and AST2600 EVB can't emulate quad mode properly so fix them using equivalent mx25l25635e and mx66u51235f respectively. These default settings still can be overridden using the 'fmc-model' command line option. Reported-by: Graeme Gregory <quic_ggregory@quicinc.com> Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220402184427.4010304-1-quic_jaehyoo@quicinc.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-02aspeed: Add an AST1030 eval boardJamin Lin
The image should be supplied with ELF binary. $ qemu-system-arm -M ast1030-evb -kernel zephyr.elf -nographic Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220401083850.15266-9-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-02aspeed/soc : Add AST1030 supportSteven Lee
The embedded core of AST1030 SoC is ARM Coretex M4. It is hard to be integrated in the common Aspeed Soc framework. We introduce a new ast1030 class with instance_init and realize handlers. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [ clg: rename aspeed_ast10xx.c to aspeed_ast10x0.c to match zephyr ] Message-Id: <20220401083850.15266-8-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-02aspeed: Add eMMC Boot Controller stubJoel Stanley
Guest code (u-boot) pokes at this on boot. No functionality is required for guest code to work correctly, but it helps to document the region being read from. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220318092211.723938-1-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-04-29hw/core: Move the ARM sysbus-fdt to coreAlistair Francis
The ARM virt machine currently uses sysbus-fdt to create device tree entries for dynamically created MMIO devices. The RISC-V virt machine can also benefit from this, so move the code to the core directory. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-3-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-28hw/arm/smmuv3: Advertise support for SMMUv3.2-BBML2Peter Maydell
The Arm SMMUv3 includes an optional feature equivalent to the CPU FEAT_BBM, which permits an OS to switch a range of memory between "covered by a huge page" and "covered by a sequence of normal pages" without having to engage in the traditional 'break-before-make' dance. (This is particularly important for the SMMU, because devices performing I/O through an SMMU are less likely to be able to cope with the window in the sequence where an access results in a translation fault.) The SMMU spec explicitly notes that one of the valid ways to be a BBM level 2 compliant implementation is: * if there are multiple entries in the TLB for an address, choose one of them and use it, ignoring the others Our SMMU TLB implementation (unlike our CPU TLB) does allow multiple TLB entries for an address, because the translation table level is part of the SMMUIOTLBKey, and so our IOTLB hashtable can include entries for the same address where the leaf was at different levels (i.e. both hugepage and normal page). Our TLB lookup implementation in smmu_iotlb_lookup() will always find the entry with the lowest level (i.e. it prefers the hugepage over the normal page) and ignore any others. TLB invalidation correctly removes all TLB entries matching the specified address or address range (unless the guest specifies the leaf level explicitly, in which case it gets what it asked for). So we can validly advertise support for BBML level 2. Note that we still can't yet advertise ourselves as an SMMU v3.2, because v3.2 requires support for the S2FWB feature, which we don't yet implement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20220426160422.2353158-4-peter.maydell@linaro.org
2022-04-28hw/arm/smmuv3: Add space in guest error messageJean-Philippe Brucker
Make the translation error message prettier by adding a missing space before the parenthesis. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20220427111543.124620-2-jean-philippe@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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