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2015-06-26hw/arm/virt: Make block devices default to virtioPeter Maydell
Now we have virtio-pci, we can make the virt board's default block device type be IF_VIRTIO. This allows users to use simplified command lines that don't have to explicitly create virtio-pci-blk devices; the -hda &c very short options now also work. This means we also need to set no_cdrom to avoid getting a default cdrom device -- this is needed because the virtio-blk device will fail if it is connected to a block backend with no media, which is what the default cdrom device typically is. Providing a cdrom with media via -cdrom will succeed, but silently create a device with non-removable medium. this is probably not really what the user wants, but is the best we can do now. Note that this change means that some command lines which used to work (by accident) will stop working. Where a drive was connected manually to a device but without 'if=none' being specified, we used to treat this as an IDE drive, which we would then not autoplug because the board doesn't support IDE. Now we will treat it as a virtio disk and autoplug it, which means the attempt to use the drive manually will fail: qemu-system-arm: -drive file=img.qcow2,id=foo: Drive 'foo' is already in use because it has been automatically connected to another device (did you need 'if=none' in the drive options?) The command line will have to be changed to include 'if=none', as the error message suggests. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1435068107-12594-4-git-send-email-peter.maydell@linaro.org
2015-06-19hw/arm/sysbus-fdt: enable vfio-calxeda-xgmac dynamic instantiationEric Auger
This patch allows the instantiation of the vfio-calxeda-xgmac device from the QEMU command line (-device vfio-calxeda-xgmac,host="<device>"). A specialized device tree node is created for the guest, containing compat, dma-coherent, reg and interrupts properties. Signed-off-by: Eric Auger <eric.auger@linaro.org> Acked-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1434455898-17895-1-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15target-arm: Use the kernel's idea of MPIDR if we're using KVMPavel Fedin
When we're using KVM, the kernel's internal idea of the MPIDR affinity fields must match the values we tell it for the guest vcpu cluster configuration in the device tree. Since at the moment the kernel doesn't support letting userspace tell it the correct affinity fields to use, we must read the kernel's view and reflect that back in the device tree. Signed-off-by: Shlomo Pongratz <shlomo.pongratz@huawei.com> Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Message-id: 02f601d0a1e6$90c7d630$b2578290$@samsung.com [PMM: Use a local #define rather than a global variable for the TCG ARM_CPUS_PER_CLUSTER setting. Tweak a comment. Update the commit message.] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-15hw/arm/virt: Add cortex-a53 cpu support in machine virtShannon Zhao
Add cortex-a53 cpu support in machine virt, so it can be used for TCG and KVM. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1433207452-4512-3-git-send-email-shannon.zhao@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-05pflash_cfi01: change big-endian property to BIT typePaolo Bonzini
Make this consistent with the secure property, added in the next patch. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-06-02hw/arm/virt: change indentation in a15memmapEric Auger
Re-indent in a15memmap after VIRT_PLATFORM_BUS introduction Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1433244554-12898-5-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02hw/arm/virt: add dynamic sysbus device supportEric Auger
Allows sysbus devices to be instantiated from command line by using -device option. Machvirt creates a platform bus at init. The dynamic sysbus devices are attached to this platform bus device. The platform bus device registers a machine init done notifier whose role will be to bind the dynamic sysbus devices. Indeed dynamic sysbus devices are created after machine init. machvirt also registers a notifier that will build the device tree nodes for the platform bus and its children dynamic sysbus devices. Signed-off-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1433244554-12898-4-git-send-email-eric.auger@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add the GICv2m to the virt boardChristoffer Dall
Add a GICv2m device to the virt board to enable MSIs on the generic PCI host controller. We allocate 64 SPIs in the IRQ space for now (this can be increased/decreased later) and map the GICv2m right after the GIC in the memory map. Reviewed-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-5-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Extend the gic node propertiesChristoffer Dall
In preparation for adding the GICv2m which requires address specifiers and is a subnode of the gic, we extend the gic DT definition to specify the #address-cells and #size-cells properties and add an empty ranges property properties of the DT node, since this is required to add the v2m node as a child of the gic node. Note that we must also expand the irq-map to reference the gic with the right address-cells as a consequence of this change. Reviewed-by: Eric Auger <eric.auger@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-4-git-send-email-christoffer.dall@linaro.org Suggested-by: Shanker Donthineni <shankerd@codeaurora.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-06-02target-arm: Add GIC phandle to VirtBoardInfoChristoffer Dall
Instead of passing the GIC phandle around between functions, add it to the VirtBoardInfo just like we do for the clock_phandle. We are about to add the v2m phandle as well, and it's easier not having to pass around a bunch of phandles, return multiple values from functions, etc. Reviewed-by: Eric Auger <eric.auger@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Message-id: 1432897270-7780-2-git-send-email-christoffer.dall@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt: Enable dynamic generation of ACPI v5.1 tablesShannon Zhao
Initialize VirtGuestInfoState and register a machine_init_done notify to call virt_acpi_build(). Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-25-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate GTDT tableShannon Zhao
ACPI v5.1 defines GTDT for ARM devices as a place to describe timer related information in the system. The Arch Timer interrupts must be provided for GTDT. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-11-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt: Record PCIe ranges in MemMapEntry arrayShannon Zhao
To generate ACPI table for PCIe controller, we need the base and size of the PCIe ranges. Record these ranges in MemMapEntry array, then we could share and use them for generating ACPI table. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-4-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt: Move common definitions to virt.hShannon Zhao
Move some common definitions to virt.h. These will be used by generating ACPI tables. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-3-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-12hw/arm/virt.c: Wire FIQ between CPU <> GICGreg Bellows
Connect FIQ output of the GIC CPU interfaces to the CPUs. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1430502643-25909-16-git-send-email-peter.maydell@linaro.org Message-id: 1429113742-8371-4-git-send-email-greg.bellows@linaro.org [PMM: minor format tweak] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-08arm: memory: Replace memory_region_init_ram with ↵Dirk Müller
memory_region_allocate_system_memory Commit 0b183fc871:"memory: move mem_path handling to memory_region_allocate_system_memory" split memory_region_init_ram and memory_region_init_ram_from_file. Also it moved mem-path handling a step up from memory_region_init_ram to memory_region_allocate_system_memory. Therefore for any board that uses memory_region_init_ram directly, -mem-path is not supported. Fix this by replacing memory_region_init_ram with memory_region_allocate_system_memory. Signed-off-by: Dirk Mueller <dmueller@suse.com> Message-id: CAL5wTH4UHYKpJF=dLJfFzxpufjY189chnCow47-ySuLf8GLbug@mail.gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-02hw/arm/virt: Fix corruption due to double freeShannon Zhao
As 4de9a88(hw/arm/virt: Fix memory leak reported by Coverity) and 6e05a12(arm: fix memory leak) both handle the memory leak reported by Coverity, this cause qemu corruption due to double free. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-id: 1427944026-8968-1-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-04-01hw/arm/virt: Fix memory leak reported by CoverityStefan Weil
As the conditional statement had to be split anyway, we can also add a better error report message. Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1426877982-3603-1-git-send-email-sw@weilnetz.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-19error: Replace error_report() & error_free() with error_report_err()zhanghailiang
This is a continuation of the work started in commit 565f65d27: "error: Use error_report_err() where appropriate" Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-03-19arm: fix memory leakGonglei
Cc: Michael Tokarev <mjt@tls.msk.ru> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-03-11hw/arm/virt: fix cmdline parsing bug with CPU options and smp > 1Ard Biesheuvel
The recently introduced feature that allows 32 bit guests to be executed under KVM on a 64-bit host incorrectly handles the case where more than 1 cpu is specified using '-smp N' For instance, this invocation of qemu qemu-system-aarch64 -M virt -cpu cortex-a57,aarch64=off -smp 2 produces the following error qemu-system-aarch64: Expected key=value format, found aarch64 which is caused by the destructive parsing performed by cpu_common_parse_features(), resulting in subsequent attempts to parse the CPU option string (for each additional CPU) to fail. So duplicate the string before parsing it, and free it directly afterwards. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1425402380-10488-1-git-send-email-ard.biesheuvel@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-03-10hw: Propagate errors through qdev_prop_set_drive()Markus Armbruster
Three kinds of callers: 1. On failure, report the error and abort Passing &error_abort does the job. No functional change. 2. On failure, report the error and exit() This is qdev_prop_set_drive_nofail(). Error reporting moves from qdev_prop_set_drive() to its caller. Because hiding away the error in the monitor right before exit() isn't helpful, replace qerror_report_err() by error_report_err(). Shouldn't make a difference, because qdev_prop_set_drive_nofail() should never be used in QMP context. 3. On failure, report the error and recover This is usb_msd_init() and scsi_bus_legacy_add_drive(). Error reporting and freeing the error object moves from qdev_prop_set_drive() to its callers. Because usb_msd_init() can't run in QMP context, replace qerror_report_err() by error_report_err() there. No functional change. scsi_bus_legacy_add_drive() calling qerror_report_err() is of course inappropriate, but this commit merely makes it more obvious. The next one will clean it up. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-Id: <1425925048-15482-3-git-send-email-armbru@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-02-13target-arm: Add feature parsing to virtGreg Bellows
Added machvirt parsing of feature keywords added to the -cpu command line option. Parsing occurs during machine initialization. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1423736974-14254-3-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-02-13arm: Add PCIe host bridge in virt machineAlexander Graf
Now that we have a working "generic" PCIe host bridge driver, we can plug it into ARM's virt machine to always have PCIe available to normal ARM VMs. I've successfully managed to expose a Bochs VGA device, XHCI and an e1000 into an AArch64 VM with this and they all lived happily ever after. Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Claudio Fontana <claudio.fontana@huawei.com> [PMM: Squashed in fix for off-by-one error in bus-range DT property from Laszlo Ersek <lersek@redhat.com>] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-02-05hw/arm/virt: explain device-to-transport mapping in create_virtio_devices()Laszlo Ersek
Signed-off-by: Laszlo Ersek <lersek@redhat.com> Message-id: 1422592273-4432-1-git-send-email-lersek@redhat.com [PMM: added note recommending UUIDs] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22hw/arm/virt: enable passing of EFI-stubbed kernel to guest UEFI firmwareLaszlo Ersek
The virt board already ensures mutual exclusion between -bios and -pflash unit#0; we only need to set "bootinfo.firmware_loaded", introduced in the previous patch, if either of those options was used to load the guest firmware. Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1419250305-31062-12-git-send-email-pbonzini@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22arm: add fw_cfg to "virt" boardLaszlo Ersek
fw_cfg already supports exposure over MMIO (used in ppc/mac_newworld.c, ppc/mac_oldworld.c, sparc/sun4m.c); we can easily add it to the "virt" board. Because MMIO access is slow on ARM KVM, we enable the guest, with fw_cfg_init_mem_wide(), to transfer up to 8 bytes with a single access. This has been measured to speed up transfers up to 7.5-fold, relative to single byte data access, on both ARM KVM and x86_64 TCG. The MMIO register block of fw_cfg is advertized in the device tree. As base address we pick 0x09020000, which conforms to the comment preceding "a15memmap": it falls in the miscellaneous device I/O range 128MB..256MB, and it is aligned at 64KB. The DTB properties follow the documentation in the Linux source file "Documentation/devicetree/bindings/arm/fw-cfg.txt". fw_cfg automatically exports a number of files to the guest; for example, "bootorder" (see fw_cfg_machine_reset()). Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1419250305-31062-9-git-send-email-pbonzini@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Set CPU has_el3 prop during virt initGreg Bellows
Adds setting of the CPU has_el3 property based on the virt machine secure state property during initialization. This enables/disables EL3 state during start-up. Changes include adding an additional secure state boolean during virt CPU initialization. Also disables the ARM secure boot by default. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1418684992-8996-13-git-send-email-greg.bellows@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Add virt machine secure propertyGreg Bellows
Add "secure" virt machine specific property to allow override of the default secure state configuration. By default, when using the QEMU -kernel command line argument, virt machines boot into NS/SVC. When using the QEMU -bios command line argument, virt machines boot into S/SVC. The secure state can be changed from the default specifying the secure state as a machine property. For example, the below command line would disable security extensions on a -kernel Linux boot: aarch64-softmmu/qemu-system-aarch64 -machine type=virt,secure=off -kernel ... Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-8-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Add virt class and machine typesGreg Bellows
Switch virt qemu machine support to use the newer object type, class, and instance model. Added virt TypeInfo with static registration along with virt specific class and machine structs. Also added virt class initialization method. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-7-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-11-20hw/arm/virt: set stdout-path instead of linux,stdout-pathLeif Lindholm
ePAPR 1.1 defines the stdout-path property, making the os-specific linux,stdout-path property redundant. Change the DT setup for ARM virt to use the generic property - supported by Linux since 3.15. The old QEMU behaviour was not present in any released version of QEMU, and was only added to QEMU after the kernel changed, so this should not break any existing setups. Signed-off-by: Leif Lindholm <leif.lindholm@linaro.org> [PMM: add note to commit about the old behaviour never hving been in a released version of QEMU] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24arm/virt: enable PSCI emulation support for system emulationRob Herring
Now that we have PSCI emulation, enable it for the virt platform. This simplifies the virt machine a bit now that PSCI no longer needs to be a KVM only feature. Signed-off-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412865028-17725-8-git-send-email-peter.maydell@linaro.org
2014-10-24hw/arm/virt: mark timer in fdt as v8-compatibleClaudio Fontana
check if the first cpu is an armv8 cpu, and if so, put arm,armv8-timer in the compatible string list. Note that due to this check, this patch moves the creation of the timer fdt node to after the cpu creation loop. Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com> Message-id: 1411736960-24206-1-git-send-email-hw.claudio@gmail.com [PMM: updated to list arm,armv8-timer first] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-20hw: Convert from BlockDriverState to BlockBackend, mostlyMarkus Armbruster
Device models should access their block backends only through the block-backend.h API. Convert them, and drop direct includes of inappropriate headers. Just four uses of BlockDriverState are left: * The Xen paravirtual block device backend (xen_disk.c) opens images itself when set up via xenbus, bypassing blockdev.c. I figure it should go through qmp_blockdev_add() instead. * Device model "usb-storage" prompts for keys. No other device model does, and this one probably shouldn't do it, either. * ide_issue_trim_cb() uses bdrv_aio_discard() instead of blk_aio_discard() because it fishes its backend out of a BlockAIOCB, which has only the BlockDriverState. * PC87312State has an unused BlockDriverState[] member. The next two commits take care of the latter two. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-10-20block: Eliminate DriveInfo member bdrv, use blk_by_legacy_dinfo()Markus Armbruster
The patch is big, but all it really does is replacing dinfo->bdrv by blk_bs(blk_by_legacy_dinfo(dinfo)) The replacement is repetitive, but the conversion of device models to BlockBackend is imminent, and will shorten it to just blk_legacy_dinfo(dinfo). Line wrapping muddies the waters a bit. I also omit tests whether dinfo->bdrv is null, because it never is. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Benoît Canet <benoit.canet@nodalink.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2014-09-12Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
- Memory: improve error reporting and avoid crashes on hotplug - Build: fixing block/iscsi.so and ranlib warnings on Mac OS X - Migration fixes for x86 - The odd KVM patch. # gpg: Signature made Thu 11 Sep 2014 11:21:10 BST using RSA key ID 9B4D86F2 # gpg: Good signature from "Paolo Bonzini <pbonzini@redhat.com>" # gpg: aka "Paolo Bonzini <bonzini@gnu.org>" * remotes/bonzini/tags/for-upstream: (21 commits) gdbstub: init mon_chr through qemu_chr_alloc pckbd: adding new fields to vmstate mc146818rtc: add missed field to vmstate piix: do not set irq while loading vmstate serial: fixing vmstate for save/restore parallel: adding vmstate for save/restore fdc: adding vmstate for save/restore cpu: init vmstate for ticks and clock offset apic_common: vapic_paddr synchronization fix vl: use QLIST_FOREACH_SAFE to visit change state handlers exec: add parameter errp to gethugepagesize exec: report error when memory < hpagesize hostmem-ram: don't exit qemu if size of memory-backend-ram is way too big memory: add parameter errp to memory_region_init_rom_device memory: add parameter errp to memory_region_init_ram exec: add parameter errp to qemu_ram_alloc and qemu_ram_alloc_from_ptr rules.mak: Fix DSO build by pulling in archive symbols util: Don't link host-utils.o if it's empty util: Move general qemu_getauxval to util/getauxval.c trace: Only link generated-tracers.o with "simple" backend ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-12hw/arm/virt: fix pl011 and pl031 irq flagsPeter Maydell
The pl011 and pl031 devices both use level triggered interrupts, but the device tree we construct was incorrectly telling the kernel to configure the GIC to treat them as edge triggered. This meant that output from the pl011 would hang after a while. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1410274423-9461-1-git-send-email-peter.maydell@linaro.org Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Cc: qemu-stable@nongnu.org
2014-09-12hw/arm/virt: Provide flash devices for boot ROMsPeter Maydell
Add two flash devices to the virt board, so that it can be used for running guests which want a bootrom image such as UEFI. We provide two flash devices to make it more convenient to provide both a read-only UEFI image and a read-write place to store guest-set UEFI config variables. The '-bios' command line option is set up to provide an image for the first of the two flash devices. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1409930126-28449-2-git-send-email-ard.biesheuvel@linaro.org
2014-09-12hw/arm/virt: add linux, stdout-path to /chosen DT nodeArd Biesheuvel
Add a property "linux,stdout-path" to the /chosen DT node and make it point to the emulated UART. This allows users such as the Linux kernel to produce console output without the need to pass console= or earlycon=pl011,0x... command line arguments. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Message-id: 1409317439-29349-1-git-send-email-ard.biesheuvel@linaro.org Reviewed-by: Rob Herring <rob.herring@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-09-09memory: add parameter errp to memory_region_init_ramHu Tao
Add parameter errp to memory_region_init_ram and update all call sites to pass in &error_abort. Signed-off-by: Hu Tao <hutao@cn.fujitsu.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-08-29aarch64: raise max_cpus to 8Joel Schopp
I'm running on a system with 8 cpus and it would be nice to have qemu support all of them. The attached patch does that and has been tested. That said, I'm not sure if 8 is enough or if we want to bump this even higher now before systems with many more cpus come along. 255 anyone? Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Joel Schopp <joel.schopp@amd.com> Message-id: 20140819213304.19537.2834.stgit@joelaarch64.amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2Christoffer Dall
The current code supplies the PSCI v0.1 function IDs in the DT even when KVM uses PSCI v0.2. This will break guest kernels that only support PSCI v0.1 as they will use the IDs provided in the DT. Guest kernels with PSCI v0.2 support are not affected by this patch, because they ignore the function IDs in the device tree and rely on the architecture definition. Define QEMU versions of the constants and check that they correspond to the Linux defines on Linux build hosts. After this patch, both guest kernels with PSCI v0.1 support and guest kernels with PSCI v0.2 should work. Tested on TC2 for 32-bit and APM Mustang for 64-bit (aarch64 guest only). Both cases tested with 3.14 and linus/master and verified I could bring up 2 cpus with both guest kernels. Also tested 32-bit with a 3.14 host kernel with only PSCI v0.1 and both guests booted here as well. Cc: qemu-stable@nongnu.org Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19target-arm: Rename QEMU PSCI v0.1 definitionsChristoffer Dall
The function IDs for PSCI v0.1 are exported by KVM and defined as KVM_PSCI_FN_<something>. To build using these defines in non-KVM code, QEMU defines these IDs locally and check their correctness against the KVM headers when those are available. However, the naming scheme used for QEMU (almost) clashes with the PSCI v0.2 definitions from Linux so to avoid unfortunate naming when we introduce local PSCI v0.2 defines, rename the current local defines with QEMU_ prependend and clearly identify the PSCI version as v0.1 in the defines. Cc: qemu-stable@nongnu.org Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-04hw/arm/virt: formatting: memory mapAndrew Jones
Add some spacing and zeros to make it easier to read and modify the map. This patch has no functional changes. The review looks ugly, but it's actually pretty easy to confirm all the addresses are as they should be - thanks to the new formatting ;-) Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-07-29hw/arm/virt: fix pl031 addr typoAndrew Jones
pl031's base address should be 0x9010000, not 0x90010000, otherwise it sits in ram when configuring a guest with greater than 1G. Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-29hw/arm/virt: Provide PL031 RTCPeter Maydell
UEFI mandates that the platform must include an RTC, so provide one in 'virt', using the PL031. This is also useful for directly booting Linux kernels which would otherwise have to run ntpdate. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-06-19Use PSCI v0.2 compatible string when KVM or TCG provides itPranavkumar Sawargaonkar
If we have PSCI v0.2 emulation available for KVM ARM/ARM64 or TCG then we need to provide PSCI v0.2 compatible string via generated DTB. Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org> Signed-off-by: Anup Patel <anup.patel@linaro.org> Reviewed-by: Rob Herring <rob.herring@linaro.org> Message-id: 1402901605-24551-9-git-send-email-pranavkumar@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-28machine: Conversion of QEMUMachineInitArgs to MachineStateMarcel Apfelbaum
Total removal of QEMUMachineInitArgs struct. QEMUMachineInitArgs's fields are copied into MachineState. Removed duplicated fields from MachineState. All the other changes are only mechanical refactoring, no semantic changes. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> (s390) Reviewed-by: Michael S. Tsirkin <mst@redhat.com> (PC) [AF: Renamed ms -> machine, use MACHINE_GET_CLASS()] Signed-off-by: Andreas Färber <afaerber@suse.de>
2014-05-01hw/arm/virt: Add support for Cortex-A57Peter Maydell
Support the Cortex-A57 in the virt machine model. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1398362083-17737-4-git-send-email-peter.maydell@linaro.org
2014-05-01hw/arm/virt: Put GIC register banks on 64K boundariesPeter Maydell
For an AArch64 CPU which supports 64K pages, having the GIC register banks at 4K offsets is potentially awkward. Move them out to being at 64K offsets. (This is harmless for AArch32 CPUs and for AArch64 CPUs with 4K pages, so it is simpler to use the same offsets everywhere than to try to use 64K offsets only for AArch64 host CPUs.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1398362083-17737-3-git-send-email-peter.maydell@linaro.org
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