Age | Commit message (Expand) | Author |
---|---|---|
2022-07-14 | aspeed: Refactor UART init for multi-SoC machines | Peter Delevoryas |
2022-07-14 | aspeed: Create SRAM name from first CPU index | Peter Delevoryas |
2022-06-30 | hw/misc/aspeed: Add PECI controller | Peter Delevoryas |
2022-06-30 | aspeed: Map unimplemented devices in SoC memory | Peter Delevoryas |
2022-06-30 | aspeed: Remove usage of sysbus_mmio_map | Peter Delevoryas |
2022-06-30 | aspeed: Add memory property to Aspeed SoC | Peter Delevoryas |
2022-06-22 | aspeed: Add I2C buses to AST1030 model | Troy Lee |
2022-05-25 | hw/gpio: Add ASPEED GPIO model for AST1030 | Jamin Lin |
2022-05-25 | hw: aspeed: Introduce common UART init function | Peter Delevoryas |
2022-05-25 | hw: aspeed: Ensure AST1030 respects uart-default | Peter Delevoryas |
2022-05-25 | hw: aspeed: Add uarts_num SoC attribute | Peter Delevoryas |
2022-05-25 | hw: aspeed: Add missing UART's | Peter Delevoryas |
2022-05-25 | aspeed: Introduce a get_irq AspeedSoCClass method | Cédric Le Goater |
2022-05-02 | aspeed/soc : Add AST1030 support | Steven Lee |