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2018-09-25hw/arm/aspeed: Add an Aspeed machine classCédric Le Goater
The code looks better, it removes duplicated lines and it will ease the introduction of common properties for the Aspeed machines. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180921161939.822-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-09-25hw/arm/aspeed: change the FMC flash model of the AST2500 evbCédric Le Goater
The AST2500 evb is shipped with a W25Q256 which has a non volatile bit to make the chip operate in 4 Byte address mode at power up. This should be an interesting feature to model as it will exercise a bit more the SMC controllers and MMIO execution at boot time. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180921161939.822-3-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16aspeed: add a max_ram_size property to the memory controllerCédric Le Goater
This will be used to construct a memory region beyond the RAM region to let firmwares scan the address space with load/store to guess how much RAM the SoC has. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-7-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-08aspeed: add the pc9552 chips to the witherspoon machineCédric Le Goater
The pca9552 LED blinkers on the Witherspoon machine are used for leds but also as GPIOs to control fans and GPUs. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180530064049.27976-8-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-08aspeed: Add EEPROM I2C devicesCédric Le Goater
The Aspeed boards have at least one EEPROM to hold the Vital Product Data (VPD). Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20180530064049.27976-6-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-08aspeed: add an I2C RTC device to all machinesCédric Le Goater
The AST2500 EVB does not have an RTC but we can pretend that one is plugged on the I2C bus header. The romulus and witherspoon boards expects an Epson RX8900 I2C RTC but a ds1338 is good enough for the basic features we need. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20180530064049.27976-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-08aspeed: add support for the witherspoon-bmc boardCédric Le Goater
The Witherspoon boards are OpenPOWER system hosting POWER9 Processors. Add support for their BMC including a couple of I2C devices as found on real HW. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20180530064049.27976-3-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-08aspeed: remove ignore_memory_transaction_failures on all boardsCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180530064049.27976-2-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-01hw: Do not include "sysemu/blockdev.h" if it is not necessaryPhilippe Mathieu-Daudé
The header "hw/boards.h" already includes "sysemu/blockdev.h". Code change produced with: $ git grep '#include "sysemu/blockdev.h"' hw | \ cut -d: -f-1 | \ xargs fgrep -l '#include "hw/boards.h"' | \ xargs sed -i.bak '/#include "sysemu\/blockdev.h"/d' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-14-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-04-26hw/arm/aspeed: don't make 'boot_rom' region 'nomigrate'Peter Maydell
Currently we use memory_region_init_ram_nomigrate() to create the "aspeed.boot_rom" memory region, and we don't manually register it with vmstate_register_ram(). This currently means that its contents are migrated but as a ram block whose name is the empty string; in future it may mean they are not migrated at all. Use memory_region_init_ram() instead. Note that would be a cross-version migration compatibility break for the "palmetto-bmc", "ast2500-evb" and "romulus-bmc" machines, but migration is currently broken for them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180420124835.7268-3-peter.maydell@linaro.org
2017-11-20hw/arm/aspeed: Unlock SCU when running kernelJoel Stanley
The ASPEED hardware contains a lock register for the SCU that disables any writes to the SCU when it is locked. The machine comes up with the lock enabled, but on all known hardware u-boot will unlock it and leave it unlocked when loading the kernel. This means the kernel expects the SCU to be unlocked. When booting from an emulated ROM the normal u-boot unlock path is executed. Things don't go well when booting using the -kernel command line, as u-boot does not run first. Change behaviour so that when a kernel is passed to the machine, set the reset value of the SCU to be unlocked. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 20171114122018.12204-1-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-07hw/arm: Set ignore_memory_transaction_failures for most ARM boardsPeter Maydell
Set the MachineClass flag ignore_memory_transaction_failures for almost all ARM boards. This means they retain the legacy behaviour that accesses to unimplemented addresses will RAZ/WI rather than aborting, when a subsequent commit adds support for external aborts. The exceptions are: * virt -- we know that guests won't try to prod devices that we don't describe in the device tree or ACPI tables * mps2 -- this board was written to use unimplemented-device for all the ranges with devices we don't yet handle New boards should not set the flag, but instead be written like the mps2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1504626814-23124-3-git-send-email-peter.maydell@linaro.org For the Xilinx boards: Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-07-14memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate()Peter Maydell
Rename memory_region_init_rom() to memory_region_init_rom_nomigrate() and memory_region_init_rom_device() to memory_region_init_rom_device_nomigrate(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1499438577-7674-5-git-send-email-peter.maydell@linaro.org
2017-06-20aspeed: use {set, get}_uint() for "ram-size" propertyMarc-André Lureau
This property is an alias for device TYPE_ASPEED_SDMC's property "ram-size", which is defined with DEFINE_PROP_UINT64(). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20170607163635.17635-25-marcandre.lureau@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2017-06-13aspeed: add a temp sensor device on I2C bus 3Cédric Le Goater
Temperatures can be changed from the monitor with : (qemu) qom-set /machine/unattached/device[2] temperature0 12000 Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1496739230-32109-3-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2017-06-02aspeed: add some I2C devices to the Aspeed machinesCédric Le Goater
Let's add an RTC to the palmetto BMC and a LM75 temperature sensor to the AST2500 EVB to start with. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1494827476-1487-5-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-10aspeed: remove useless comment on controller segment sizeCédric Le Goater
The flash devices used for the FMC controller (BMC firmware) are well defined for each Aspeed machine and are all smaller than the default mapping window size, at least for CE0 which is the chip the SoC boots from. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1486648058-520-3-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-10aspeed: check for negative values returned by blk_getlength()Cédric Le Goater
write_boot_rom() does not check for negative values. This is more a problem for coverity than the actual code as the size of the flash device is checked when the m25p80 object is created. If there is anything wrong with the backing file, we should not even reach that path. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1486648058-520-2-git-send-email-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-20aspeed: use first FMC flash as a boot ROMCédric Le Goater
Create a ROM region, using the default size of the mapping window for the CE0 FMC flash module, and fill it with the flash content. This is a little hacky but until we can boot from a MMIO region, it seems difficult to do anything else. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1483979087-32663-11-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed/smc: set the number of flash modules for the FMC controllerCédric Le Goater
Add a new configuration field at the board level and propagate the value using the "num-cs" property of the FMC controller model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1480434248-27138-14-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: change SoC revision of the palmetto-bmc machineCédric Le Goater
The palmetto BMC machine uses a AST2400 revision A1 SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-11-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: add support for the romulus-bmc boardCédric Le Goater
The Romulus machine is an OpenPOWER system with an AST2500 SoC for the BMC and a POWER9 chip for the host. It does not make much difference for qemu a part from the fact that the FMC controller has two SPI flash module. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 1480434248-27138-8-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: extend the board configuration with flash modelsCédric Le Goater
Future machine will use different flash models for the FMC and the SPI controllers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-7-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-17aspeed: extend the number of host SPI controllersCédric Le Goater
The AST2500 SoC has two. Let's prepare ground for the next changes which will add the required definitions for the second host SPI controller. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1474977462-28032-4-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-17aspeed: rename the smc object to fmcCédric Le Goater
The Aspeed SoC has three different types of SMC (Static Memory Controller) controllers: the SMC (legacy), the FMC (the new one) and the SPI for the host PNOR. The FMC and the SPI models are now converging on the AST2500 SoC and the SMC, which was still available on the AST2400 SoC, was removed. The Aspeed SoC does not provide support for the legacy SMC controller. So, let's rename the 'smc' object to 'fmc' to clarify its nature. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1474977462-28032-2-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-22aspeed: allocate RAM after the memory controller has checked the sizeCédric Le Goater
If the RAM size is invalid, the memory controller will use a default value. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1473438177-26079-15-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-22aspeed: add a ram_size property to the memory controllerCédric Le Goater
Configure the size of the RAM of the SOC using a property to propagate the value down to the memory controller from the board level. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1473438177-26079-14-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-22palmetto-bmc: remove extra no_sdcard assignementCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-11-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-22arm: add support for an ast2500 evaluation boardCédric Le Goater
The ast2500 eval board has a hardware strapping register value of 0xF100C2E6 which we use for a definition of AST2500_EVB_HW_STRAP1 below. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-10-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-22hw/misc: use macros to define hw-strap1 register on the AST2400 Aspeed SoCCédric Le Goater
This gives some explanation behind the magic number 0x120CE416. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-8-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-22palmetto-bmc: add board specific configurationCédric Le Goater
aspeed_board_init() now uses a board identifier to customize some values specific to the board. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-7-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-22palmetto-bmc: replace palmetto_bmc with aspeedCédric Le Goater
This is mostly a name replacement to prepare ground for other SoCs specificities. It also adds a TypeInfo struct for the palmetto-bmc board with a custom initialization for the same reason. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-6-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-22palmetto-bmc: rename the Aspeed board file to aspeed.cCédric Le Goater
We plan to add more Aspeed boards to this file. There are no changes in the code. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1473438177-26079-5-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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