aboutsummaryrefslogtreecommitdiff
path: root/docs/system
AgeCommit message (Collapse)Author
2022-05-09target/arm: Define neoverse-n1Richard Henderson
Enable the n1 for virt and sbsa board use. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09target/arm: Define cortex-a76Richard Henderson
Enable the a76 for virt and sbsa board use. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09target/arm: Enable FEAT_DGH for -cpu maxRichard Henderson
This extension concerns not merging memory access, which TCG does not implement. Thus we can trivially enable this feature. Add a comment to handle_hint for the DGH instruction, but no code. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09target/arm: Enable FEAT_CSV3 for -cpu maxRichard Henderson
This extension concerns cache speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09target/arm: Enable FEAT_CSV2_2 for -cpu maxRichard Henderson
There is no branch prediction in TCG, therefore there is no need to actually include the context number into the predictor. Therefore all we need to do is add the state for SCXTNUM_ELx. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09target/arm: Enable FEAT_CSV2 for -cpu maxRichard Henderson
This extension concerns branch speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09target/arm: Enable FEAT_IESB for -cpu maxRichard Henderson
This feature is AArch64 only, and applies to physical SErrors, which QEMU does not implement, thus the feature is a nop. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09target/arm: Enable FEAT_RAS for -cpu maxRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09target/arm: Enable FEAT_Debugv8p4 for -cpu maxRichard Henderson
This extension concerns changes to the External Debug interface, with Secure and Non-secure access to the debug registers, and all of it is outside the scope of QEMU. Indicating support for this is mandatory with FEAT_SEL2, which we do implement. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-09target/arm: Enable FEAT_Debugv8p2 for -cpu maxRichard Henderson
The only portion of FEAT_Debugv8p2 that is relevant to QEMU is CONTEXTIDR_EL2, which is also conditionally implemented with FEAT_VHE. The rest of the debug extension concerns the External debug interface, which is outside the scope of QEMU. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220506180242.216785-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-04-29hw/riscv: Enable TPM backendsAlistair Francis
Imply the TPM sysbus devices. This allows users to add TPM devices to the RISC-V virt board. This was tested by first creating an emulated TPM device: swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \ --ctrl type=unixio,path=swtpm-sock Then launching QEMU with: -chardev socket,id=chrtpm,path=swtpm-sock \ -tpmdev emulator,id=tpm0,chardev=chrtpm \ -device tpm-tis-device,tpmdev=tpm0 The TPM device can be seen in the memory tree and the generated device tree. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/942 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20220427234146.1130752-7-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-04-28target/arm: Advertise support for FEAT_BBM level 2Peter Maydell
The description in the Arm ARM of the requirements of FEAT_BBM is admirably clear on the guarantees it provides software, but slightly more obscure on what that means for implementations. The description of the equivalent SMMU feature in the SMMU specification (IHI0070D.b section 3.21.1) is perhaps a bit more detailed and includes some example valid implementation choices. (The SMMU version of this feature is slightly tighter than the CPU version: the CPU is permitted to raise TLB Conflict aborts in some situations that the SMMU may not. This doesn't matter for QEMU because we don't want to do TLB Conflict aborts anyway.) The informal summary of FEAT_BBM is that it is about permitting an OS to switch a range of memory between "covered by a huge page" and "covered by a sequence of normal pages" without having to engage in the 'break-before-make' dance that has traditionally been necessary. The 'break-before-make' sequence is: * replace the old translation table entry with an invalid entry * execute a DSB insn * execute a broadcast TLB invalidate insn * execute a DSB insn * write the new translation table entry * execute a DSB insn The point of this is to ensure that no TLB can simultaneously contain TLB entries for the old and the new entry, which would traditionally be UNPREDICTABLE (allowing the CPU to generate a TLB Conflict fault or to use a random mishmash of values from the old and the new entry). FEAT_BBM level 2 says "for the specific case where the only thing that changed is the size of the block, the TLB is guaranteed not to do weird things even if there are multiple entries for an address", which means that software can now do: * replace old translation table entry with new entry * DSB * broadcast TLB invalidate * DSB As the SMMU spec notes, valid ways to do this include: * if there are multiple entries in the TLB for an address, choose one of them and use it, ignoring the others * if there are multiple entries in the TLB for an address, throw them all out and do a page table walk to get a new one QEMU's page table walk implementation for Arm CPUs already meets the requirements for FEAT_BBM level 2. When we cache an entry in our TCG TLB, we do so only for the specific (non-huge) page that the address is in, and there is no way for the TLB data structure to ever have more than one TLB entry for that page. (We handle huge pages only in that we track what part of the address space is covered by huge pages so that a TLB invalidate operation for an address in a huge page results in an invalidation of the whole TLB.) We ignore the Contiguous bit in page table entries, so we don't have to do anything for the parts of FEAT_BBM that deal with changis to the Contiguous bit. FEAT_BBM level 2 also requires that the nT bit in block descriptors must be ignored; since commit 39a1fd25287f5dece5 we do this. It's therefore safe for QEMU to advertise FEAT_BBM level 2 by setting ID_AA64MMFR2_EL1.BBM to 2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220426160422.2353158-3-peter.maydell@linaro.org
2022-04-28target/arm: Advertise support for FEAT_TTLPeter Maydell
The Arm FEAT_TTL architectural feature allows the guest to provide an optional hint in an AArch64 TLB invalidate operation about which translation table level holds the leaf entry for the address being invalidated. QEMU's TLB implementation doesn't need that hint, and we correctly ignore the (previously RES0) bits in TLB invalidate operation values that are now used for the TTL field. So we can simply advertise support for it in our 'max' CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220426160422.2353158-2-peter.maydell@linaro.org
2022-04-22hw/arm/virt: Support TCG GICv4Peter Maydell
Add support for the TCG GICv4 to the virt board. For the board, the GICv4 is very similar to the GICv3, with the only difference being the size of the redistributor frame. The changes here are thus: * calculating virt_redist_capacity correctly for GICv4 * changing various places which were "if GICv3" to be "if not GICv2" * the commandline option handling Note that using GICv4 reduces the maximum possible number of CPUs on the virt board from 512 to 317, because we can now only fit half as many redistributors into the redistributor regions we have defined. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220408141550.1271295-42-peter.maydell@linaro.org
2022-04-21hw/arm/virt: impact of gic-version on max CPUsHeinrich Schuchardt
Describe that the gic-version influences the maximum number of CPUs. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Message-id: 20220413231456.35811-1-heinrich.schuchardt@canonical.com [PMM: minor punctuation tweaks] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-04-20docs/ccid: convert to restructuredTextLucas Ramage
Buglink: https://gitlab.com/qemu-project/qemu/-/issues/527 Signed-off-by: Lucas Ramage <lucas.ramage@infinite-omicron.com> Message-Id: <20220405142906.21382-1-oxr463@gmx.us> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> [thuth: Added some cosmetic fixes] Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-05Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell
* fix vss-win32 compilation with clang++ * update Coverity model * add measurement calculation to amd-memory-encryption docs # gpg: Signature made Tue 05 Apr 2022 09:42:59 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: docs/system/i386: Add measurement calculation details to amd-memory-encryption qga/vss-win32: fix compilation with clang++ coverity: update model for latest tools Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-04-05docs/system/i386: Add measurement calculation details to amd-memory-encryptionDov Murik
Add a section explaining how the Guest Owner should calculate the expected guest launch measurement for SEV and SEV-ES. Also update the name and links to the SEV API Spec document. Signed-off-by: Dov Murik <dovmurik@linux.ibm.com> Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20220217110059.2320497-1-dovmurik@linux.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-04-05docs/system/devices/can.rst: correct links to CTU CAN FD IP core documentation.Pavel Pisa
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-id: 20220402204523.32643-1-pisa@cmp.felk.cvut.cz Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-03Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-to-apply-20220303' into staging Fifth RISC-V PR for QEMU 7.0 * Fixup checks for ext_zb[abcs] * Add AIA support for virt machine * Increase maximum number of CPUs in virt machine * Fixup OpenTitan SPI address * Add support for zfinx, zdinx and zhinx{min} extensions # gpg: Signature made Thu 03 Mar 2022 05:26:55 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20220303: target/riscv: expose zfinx, zdinx, zhinx{min} properties target/riscv: add support for zhinx/zhinxmin target/riscv: add support for zdinx target/riscv: add support for zfinx target/riscv: hardwire mstatus.FS to zero when enable zfinx target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} hw: riscv: opentitan: fixup SPI addresses hw/riscv: virt: Increase maximum number of allowed CPUs docs/system: riscv: Document AIA options for virt machine hw/riscv: virt: Add optional AIA IMSIC support to virt machine hw/intc: Add RISC-V AIA IMSIC device emulation hw/riscv: virt: Add optional AIA APLIC support to virt machine target/riscv: fix inverted checks for ext_zb[abcs] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-03docs/system: riscv: Document AIA options for virt machineAnup Patel
We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel <anup.patel@wdc.com> Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20220220085526.808674-5-anup@brainfault.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-03-02target/arm: Implement FEAT_LPA2Richard Henderson
This feature widens physical addresses (and intermediate physical addresses for 2-stage translation) from 48 to 52 bits, when using 4k or 16k pages. This introduces the DS bit to TCR_ELx, which is RES0 unless the page size is enabled and supports LPA2, resulting in the effective value of DS for a given table walk. The DS bit changes the format of the page table descriptor slightly, moving the PS field out to TCR so that all pages have the same sharability and repurposing those bits of the page table descriptor for the highest bits of the output address. Do not yet enable FEAT_LPA2; we need extra plumbing to avoid tickling an old kernel bug. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220301215958.157011-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-02target/arm: Implement FEAT_LPARichard Henderson
This feature widens physical addresses (and intermediate physical addresses for 2-stage translation) from 48 to 52 bits, when using 64k pages. The only thing left at this point is to handle the extra bits in the TTBR and in the table descriptors. Note that PAR_EL1 and HPFAR_EL2 are nominally extended, but we don't mask out the high bits when writing to those registers, so no changes are required there. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220301215958.157011-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-02target/arm: Implement FEAT_LVARichard Henderson
This feature is relatively small, as it applies only to 64k pages and thus requires no additional changes to the table descriptor walking algorithm, only a change to the minimum TSZ (which is the inverse of the maximum virtual address space size). Note that this feature widens VBAR_ELx, but we already treat the register as being 64 bits wide. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220301215958.157011-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-28Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20220227' ↵Peter Maydell
into staging aspeed queue: * Removal of the swift-bmc machine * New Secure Boot Controller model * Improvements on the rainier machine * Various small cleanups # gpg: Signature made Sun 27 Feb 2022 08:45:45 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20220227: aspeed/sdmc: Add trace events aspeed/smc: Add an address mask on segment registers aspeed: Introduce a create_pca9552() helper aspeed: rainier: Add strap values taken from hardware aspeed: rainier: Add i2c LED devices ast2600: Add Secure Boot Controller model arm: Remove swift-bmc machine Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-26arm: Remove swift-bmc machineJoel Stanley
It was scheduled for removal in 7.0. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-02-23Merge remote-tracking branch ↵Peter Maydell
'remotes/berrange-gitlab/tags/misc-next-pull-request' into staging This misc series of changes: - Improves documentation of SSH fingerprint checking - Fixes SHA256 fingerprints with non-blockdev usage - Blocks the clone3, setns, unshare & execveat syscalls with seccomp - Blocks process spawning via clone syscall, but allows threads, with seccomp - Takes over seccomp maintainer role - Expands firmware descriptor spec to allow flash without NVRAM # gpg: Signature made Thu 17 Feb 2022 11:57:13 GMT # gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full] # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full] # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange-gitlab/tags/misc-next-pull-request: docs: expand firmware descriptor to allow flash without NVRAM MAINTAINERS: take over seccomp from Eduardo Otubo seccomp: block setns, unshare and execveat syscalls seccomp: block use of clone3 syscall seccomp: fix blocking of process spawning seccomp: add unit test for seccomp filtering seccomp: allow action to be customized per syscall block: print the server key type and fingerprint on failure block: support sha256 fingerprint with pre-blockdev options block: better document SSH host key fingerprint checking Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-21hw/arm: add initial mori-bmc boardPatrick Venture
This is the BMC attached to the OpenBMC Mori board. Signed-off-by: Patrick Venture <venture@google.com> Reviewed-by: Chris Rauer <crauer@google.com> Reviewed-by: Ilkyun Choi <ikchoi@google.com> Message-id: 20220208233104.284425-1-venture@google.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-16block: better document SSH host key fingerprint checkingDaniel P. Berrangé
The docs still illustrate host key fingerprint checking using the old md5 hashes which are considered insecure and obsolete. Change it to illustrate using a sha256 hash. Also show how to extract the hash value from the known_hosts file. Reviewed-by: Hanna Reitz <hreitz@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2022-02-16docs/system: riscv: Update description of CPUYu Li
Since the hypervisor extension been non experimental and enabled for default CPU, the previous command is no longer available and the option `x-h=true` or `h=true` is also no longer required. Signed-off-by: Yu Li <liyu.yukiteru@bytedance.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <9040401e-8f87-ef4a-d840-6703f08d068c@bytedance.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-02-09docs: rstfy confidential guest documentationCornelia Huck
Also rstfy the documentation for AMD SEV, and link it. The documentation for PEF had been merged into the pseries doc, fix the reference. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220204161251.241877-1-cohuck@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-20docs/can: convert to restructuredTextLucas Ramage
Buglink: https://gitlab.com/qemu-project/qemu/-/issues/527 Signed-off-by: Lucas Ramage <lucas.ramage@infinite-omicron.com> Message-id: 20220105205628.5491-1-oxr463@gmx.us Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: Move to docs/system/devices/ rather than top-level; fix a pre-existing typo in passing] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-01-20hw/arm/virt: KVM: Enable PAuth when supported by the hostMarc Zyngier
Add basic support for Pointer Authentication when running a KVM guest and that the host supports it, loosely based on the SVE support. Although the feature is enabled by default when the host advertises it, it is possible to disable it by setting the 'pauth=off' CPU property. The 'pauth' comment is removed from cpu-features.rst, as it is now common to both TCG and KVM. Tested on an Apple M1 running 5.16-rc6. Cc: Eric Auger <eric.auger@redhat.com> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220107150154.2490308-1-maz@kernel.org [PMM: fixed indentation] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-01-19Merge remote-tracking branch 'remotes/stsquad/tags/pull-for-7.0-180122-2' ↵Peter Maydell
into staging Various testing and other misc updates: - fix compiler warnings with ui and sdl - update QXL/spice dependancy - skip I/O tests on Alpine - update fedora image to latest version - integrate lcitool and regenerate docker images - favour CONFIG_LINUX_USER over CONFIG_LINUX - add libfuse3 dependencies to docker images - add dtb-kaslr-seed control knob to virt machine - fix build breakage from HMP update - update docs for C standard and suffix usage - add more logging for debugging user hole finding - expand reserve for brk() for static 64 bit programs - fix bug with linux-user hole calculation - avoid affecting flags when printing results in float tests - add float reference files for ppc64 - update FreeBSD to 12.3 - add bison dependancy to tricore images # gpg: Signature made Tue 18 Jan 2022 16:47:42 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-for-7.0-180122-2: (31 commits) docker: include bison in debian-tricore-cross FreeBSD: Upgrade to 12.3 release test/tcg/ppc64le: Add float reference files tests/tcg/multiarch: Read fp flags before printf linux-user: don't adjust base of found hole linux-user/elfload: add extra logging for hole finding linux-user: expand reserved brk space for 64bit guests docs/devel: more documentation on the use of suffixes docs/devel: update C standard to C11 monitor: move x-query-profile into accel/tcg to fix build hw/arm: add control knob to disable kaslr_seed via DTB tests/docker: add libfuse3 development headers tests/tcg: use CONFIG_LINUX_USER, not CONFIG_LINUX tests/docker: auto-generate alpine.docker with lcitool tests/docker: fully expand the alpine package list tests/docker: fix sorting of alpine image package lists tests/docker: updates to alpine package list .gitlab-ci.d/cirrus: auto-generate variables with lcitool tests/docker: remove ubuntu.docker container tests/docker: auto-generate opensuse-leap.docker with lcitool ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-01-18hw/arm: add control knob to disable kaslr_seed via DTBAlex Bennée
Generally a guest needs an external source of randomness to properly enable things like address space randomisation. However in a trusted boot environment where the firmware will cryptographically verify components having random data in the DTB will cause verification to fail. Add a control knob so we can prevent this being added to the system DTB. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Acked-by: Jerome Forissier <jerome@forissier.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-Id: <20220105135009.1584676-22-alex.bennee@linaro.org>
2022-01-18Link new ppc-spapr-uv-hcalls.rst to pseries.rst.Leonardo Garcia
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <a24d2c260442e44aa99d4c18b1717f2f4a73529a.1642446876.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-18Link new ppc-spapr-hotplug.rst file to pseries.rst.Leonardo Garcia
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <e54aad58e3cfbd96647430d33cdb59fd87d199b0.1641995058.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12docs: Clarifications and formatting changes in ppc docs.Leonardo Garcia
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <3b228af4785241c7fb4a2c70f0c495d2a9adea83.1641405872.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-01-12docs/system/ppc: Merge the PEF information into the pseries pageThomas Huth
The Protected Execution Facility is only available with the pseries machine, so let's merge the old ASCII text into the new RST file now. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220105103232.405204-1-thuth@redhat.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17Merge tag 'pull-ppc-20211217' of https://github.com/legoater/qemu into stagingRichard Henderson
ppc 7.0 queue: * General cleanup for Mac machines (Peter) * Fixes for FPU exceptions (Lucas) * Support for new ISA31 instructions (Matheus) * Fixes for ivshmem (Daniel) * Cleanups for PowerNV PHB (Christophe and Cedric) * Updates of PowerNV and pSeries documentation (Leonardo and Daniel) * Fixes for PowerNV (Daniel) * Large cleanup of FPU implementation (Richard) * Removal of SoftTLBs support for PPC74x CPUs (Fabiano) * Fixes for exception models in MPCx and 60x CPUs (Fabiano) * Removal of 401/403 CPUs (Cedric) * Deprecation of taihu machine (Thomas) * Large rework of PPC405 machine (Cedric) * Fixes for VSX instructions (Victor and Matheus) * Fix for e6500 CPU (Fabiano) * Initial support for PMU (Daniel) # gpg: Signature made Fri 17 Dec 2021 09:20:31 AM PST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-ppc-20211217' of https://github.com/legoater/qemu: (101 commits) ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices ppc/pnv: Move realize of PEC stacks under the PEC model ppc/pnv: Remove "system-memory" property from PHB4 PEC ppc/pnv: Compute the PHB index from the PHB4 PEC model ppc/pnv: Introduce a num_stack class attribute ppc/pnv: Introduce a "chip" property under the PHB4 model ppc/pnv: Introduce version and device_id class atributes for PHB4 devices ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices ppc/pnv: Use QOM hierarchy to scan PHB3 devices ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize() ppc/pnv: Drop the "num-phbs" property ppc/pnv: Use the chip class to check the index of PHB3 devices ppc/pnv: Introduce a "chip" property under PHB3 PPC64/TCG: Implement 'rfebb' instruction target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event target/ppc: enable PMU instruction count target/ppc: enable PMU counter overflow with cycle events target/ppc: PMU: update counters on MMCR1 write target/ppc: PMU: update counters on PMCs r/w target/ppc: PMU basic cycle count for pseries TCG ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-17Link new ppc-spapr-hcalls.rst file to pseries.rst.Leonardo Garcia
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <7d3c8bad1ca76eb13d6ce2b16dd9a821edcdb27b.1638982486.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17docs: Introducing pseries documentation.Leonardo Garcia
The purpose of this document is to substitute the content currently available in the QEMU wiki at [0]. This initial version does contain some additional content as well. Whenever this documentation gets upstream and is reflected in [1], the QEMU wiki will be edited to point to this documentation, so that we only need to keep it updated in one place. 0. https://wiki.qemu.org/Documentation/Platforms/POWER 1. https://qemu.readthedocs.io/en/latest/system/ppc/pseries.html Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <66b6fdde52062fdf4f4b4dc35a9f06a899c88293.1638981899.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17docs/system/ppc/powernv.rst: document KVM support statusDaniel Henrique Barboza
Put in a more accessible place the reasoning behind our decision to officially drop KVM support in the powernv machine. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20211130133153.444601-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17docs: Minor updates on the powernv documentation.Leonardo Garcia
Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com> [ clg: replaced Power9 by POWER9 ] Message-Id: <c387f883b3db34d9fcb44ccac2ef11c35a25e18c.1637669345.git.lagarcia@br.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-16Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
* improve compatibility for macOS scripts/entitlement.sh (Evan) * add support for KVM_GUESTDBG_BLOCKIRQ (Maxim) * update linux-headers to Linux 5.16 (myself) * configure cleanups (myself) * lsi53c895a assertion failure fix (Philippe) * fix incorrect description for die-id (Yanan) * support for NUMA in SGX enclave memory (Yang Zhong) # gpg: Signature made Wed 15 Dec 2021 02:49:44 AM PST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [unknown] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: configure: remove dead variables doc: Add the SGX numa description numa: Support SGX numa in the monitor and Libvirt interfaces numa: Enable numa for SGX EPC sections kvm: add support for KVM_GUESTDBG_BLOCKIRQ gdbstub, kvm: let KVM report supported singlestep flags gdbstub: reject unsupported flags in handle_set_qemu_sstep linux-headers: update to 5.16-rc1 virtio-gpu: do not byteswap padding scripts/entitlement.sh: Use backward-compatible cp flags qapi/machine.json: Fix incorrect description for die-id tests/qtest: Add fuzz-lsi53c895a-test hw/scsi/lsi53c895a: Do not abort when DMA requested and no data queued Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-12-15docs: aspeed: ADC is now modelledJoel Stanley
Move it to the supported list. Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20211117065752.330632-5-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-12-15docs: aspeed: Give an example of booting a kernelJoel Stanley
A common use case for the ASPEED machine is to boot a Linux kernel. Provide a full example command line. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20211117065752.330632-4-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-12-15docs: aspeed: Update OpenBMC image URLJoel Stanley
This is the latest URL for the OpenBMC CI. The old URL still works, but redirects. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20211117065752.330632-3-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-12-15docs: aspeed: Add new boardsJoel Stanley
Add X11, FP5280G2, G220A, Rainier and Fuji. Mention that Swift will be removed in v7.0. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 20211117065752.330632-2-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-12-10doc: Add the SGX numa descriptionYang Zhong
Add the SGX numa reference command and how to check if SGX numa is support or not with multiple EPC sections. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Message-Id: <20211101162009.62161-5-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-16 03:19:33 +0000