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2024-04-26exec: Declare target_words_bigendian() in 'exec/tswap.h'Philippe Mathieu-Daudé
We usually check target endianess before swapping values, so target_words_bigendian() declaration makes sense in "exec/tswap.h" with the target swapping helpers. Remove "hw/core/cpu.h" when it was only included to get the target_words_bigendian() declaration. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20231212123401.37493-16-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-24target/nios2: Remove the deprecated Nios II targetPhilippe Mathieu-Daudé
The Nios II target is deprecated since v8.2 in commit 9997771bc1 ("target/nios2: Deprecate the Nios II architecture"). Remove: - Buildsys / CI infra - User emulation - System emulation (10m50-ghrd & nios2-generic-nommu machines) - Tests Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Marek Vasut <marex@denx.de> Message-Id: <20240327144806.11319-3-philmd@linaro.org>
2024-04-08nanomips: fix warnings with GCC 14Paolo Bonzini
GCC 14 shows -Wshadow=local warnings if an enum conflicts with a local variable (including a parameter). To avoid this, move the problematic enum and all of its dependencies after the hundreds of functions that have a parameter named "instruction". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-03-29disas: Show opcodes for target_disas and monitor_disasRichard Henderson
Fixes: 83b4613ba83 ("disas: introduce show_opcodes") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-03-06target/riscv: honour show_opcodes when disassemblingAlex Bennée
This makes the output suitable when used for plugins. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-30-alex.bennee@linaro.org>
2024-03-06disas/hppa: honour show_opcodesAlex Bennée
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-28-alex.bennee@linaro.org>
2024-03-06disas: introduce show_opcodesAlex Bennée
For plugins we don't expect the raw opcodes in the disassembly. We already deal with this by hand crafting our capstone call but for other diassemblers we need a flag. Introduce show_opcodes which defaults to off. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-27-alex.bennee@linaro.org>
2024-02-11disas/hppa: Add disassembly for qemu specific instructionsHelge Deller
Add disassembly of opcodes for "HALT QEMU", "RESET QEMU" and "RESTORE SHR" (restore shadow registers). Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-30disas/riscv: Clean up includesPeter Maydell
This commit was created with scripts/clean-includes: ./scripts/clean-includes --git disas/riscv disas/riscv*[ch] All .c should include qemu/osdep.h first. The script performs three related cleanups: * Ensure .c files include qemu/osdep.h first. * Including it in a .h is redundant, since the .c already includes it. Drop such inclusions. * Likewise, including headers qemu/osdep.h includes is redundant. Drop these, too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-01-10disas/riscv: Add amocas.[w,d,q] instructionsRob Bradford
Signed-off-by: Rob Bradford <rbradford@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20231207153842.32401-3-rbradford@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-24disas/cris: Pass buffer size to format_dec() to avoid overflow warningPhilippe Mathieu-Daudé
Propagate the buffer size to format_dec() and use snprintf(). This should silence this UBSan -Wformat-overflow warning: In file included from /usr/include/stdio.h:906, from include/qemu/osdep.h:114, from ../disas/cris.c:21: In function 'sprintf', inlined from 'format_dec' at ../disas/cris.c:1737:3, inlined from 'print_with_operands' at ../disas/cris.c:2477:12, inlined from 'print_insn_cris_generic.constprop' at ../disas/cris.c:2690:8: /usr/include/bits/stdio2.h:30:10: warning: null destination pointer [-Wformat-overflow=] 30 | return __builtin___sprintf_chk (__s, __USE_FORTIFY_LEVEL - 1, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 31 | __glibc_objsize (__s), __fmt, | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 32 | __va_arg_pack ()); | ~~~~~~~~~~~~~~~~~ Reported-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231120132222.82138-1-philmd@linaro.org> [Rewritten to fix logic and avoid repeated expression. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-11-17disas/hppa: Show hexcode of instruction along with disassemblyHelge Deller
On hppa many instructions can be expressed by different bytecodes. To be able to debug qemu translation bugs it's therefore necessary to see the currently executed byte codes without the need to lookup the sequence without the full executable. With this patch the instruction byte code is shown beside the disassembly. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-07disas/riscv: Replace TABs with spaceMax Chou
Replaces TABs with spaces, making sure to have a consistent coding style of 4 space indentations. Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231026151828.754279-15-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-07disas/riscv: Add support for vector crypto extensionsMax Chou
This patch adds following v1.0.0 ratified vector crypto extensions support to the RISC-V disassembler. - Zvbb - Zvbc - Zvkb - Zvkg - Zvkned - Zvknha - Zvknhb - Zvksed - Zvksh Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20231026151828.754279-14-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-07disas/riscv: Add rv_codec_vror_vi for vror.viMax Chou
Add rv_codec_vror_vi for the vector crypto instruction - vror.vi. The rotate amount of vror.vi is defined by combining seperated bits. Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231026151828.754279-13-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-07disas/riscv: Add rv_fmt_vd_vs2_uimm formatMax Chou
Add rv_fmt_vd_vs2_uimm format for vector crypto instructions. Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231026151828.754279-12-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-10-12disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14Alvin Chang
Fix the inverted order of pmpaddr13 and pmpaddr14 in csr_name(). Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230907084500.328-1-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-09-29disas/m68k: clean up local variable shadowingLaurent Vivier
Fix following warnings .../disas/m68k.c: In function ‘print_insn_arg’: .../disas/m68k.c:1635:13: warning: declaration of ‘val’ shadows a previous local [-Wshadow=compatible-local] 1635 | int val = fetch_arg (buffer, place, 5, info); | ^~~ .../disas/m68k.c:1093:7: note: shadowed declaration is here 1093 | int val = 0; | ^~~ Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20230925084455.395150-1-laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2023-07-19riscv/disas: Fix disas output of upper immediatesChristoph Müllner
The GNU assembler produces the following output for instructions with upper immediates: 00002597 auipc a1,0x2 000024b7 lui s1,0x2 6409 lui s0,0x2 # c.lui The immediate operands of upper immediates are not shifted. However, the QEMU disassembler prints them shifted: 00002597 auipc a1,8192 000024b7 lui s1,8192 6409 lui s0,8192 # c.lui The current implementation extracts the immediate bits and shifts the by 12, so the internal representation of the immediate is the actual immediate. However, the immediates are later printed using rv_fmt_rd_imm or rv_fmt_rd_offset, which don't undo the shift. Let's fix this by using specific output formats for instructions with upper immediates, that take care of the shift. Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230711075051.1531007-1-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner
This patch introduces the RISC-V Zfa extension, which introduces additional floating-point instructions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round to integer) * fcvtmod.w.d (Modular Convert-to-Integer) * fmv* to access high bits of float register bigger than XLEN * Quiet comparison instructions (fleq/fltq) Zfa defines its instructions in combination with the following extensions: * single-precision floating-point (F) * double-precision floating-point (D) * quad-precision floating-point (Q) * half-precision floating-point (Zfh) Since QEMU does not support the RISC-V quad-precision floating-point ISA extension (Q), this patch does not include the instructions that depend on this extension. All other instructions are included in this patch. The Zfa specification can be found here: https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex The Zfa specifciation is frozen and is in public review since May 3, 2023: https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg The patch also includes a TCG test for the fcvtmod.w.d instruction. The test cases test for correct results and flag behaviour. Note, that the Zfa specification requires fcvtmod's flag behaviour to be identical to a fcvt with the same operands (which is also tested). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230710071243.282464-1-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-10target/riscv: Add disas support for BF16 extensionsWeiwei Li
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230703071759.86775-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-10disas/riscv: Add support for XThead* instructionsChristoph Müllner
Support for emulating XThead* instruction has been added recently. This patch adds support for these instructions to the RISC-V disassembler. Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-10disas/riscv: Add support for XVentanaCondOpsChristoph Müllner
This patch adds XVentanaCondOps support to the RISC-V disassembler. Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-Id: <20230612111034.3955227-8-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-10disas/riscv: Provide infrastructure for vendor extensionsChristoph Müllner
A previous patch provides a pointer to the RISCVCPUConfig data. Let's use this to add the necessary code for vendor extensions. This patch does not change the current behaviour, but clearly defines how vendor extension support can be added to the disassembler. Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230612111034.3955227-7-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-10disas/riscv: Encapsulate opcode_data into decodeChristoph Müllner
This patch adds a reference to a struct rv_opcode_data object into struct rv_decode. This further allows to remove all references to the global variable opcode_data (which is renamed to rvi_opcode_data). This patch does not introduce any functional change, but prepares the code for more struct rv_opcode_data objects in the future. This patch is based on previous work from Liu Zhiwei: https://lists.nongnu.org/archive/html/qemu-devel/2022-08/msg03662.html Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230612111034.3955227-6-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-10disas/riscv: Make rv_op_illegal a shared enum valueChristoph Müllner
The enum value 'rv_op_illegal' does not represent an instruction, but is a catch-all value in case we have no match in the decoder. Let's make the value a shared one, so that other compile units can reuse it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230612111034.3955227-5-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-07-10disas/riscv: Move types/constants to new header fileChristoph Müllner
In order to enable vendor disassembler support, we need to move types and constants into a header file so that other compilation units can use them as well. This patch does not introduce any functional changes. Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230612111034.3955227-4-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé
We use the user_ss[] array to hold the user emulation sources, and the softmmu_ss[] array to hold the system emulation ones. Hold the latter in the 'system_ss[]' array for parity with user emulation. Mechanical change doing: $ sed -i -e s/softmmu_ss/system_ss/g $(git grep -l softmmu_ss) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-10-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-13disas/riscv.c: Remove redundant parenthesesWeiwei Li
Remove redundant parenthese and fix multi-line comments. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-9-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13disas/riscv.c: Fix lines with over 80 charactersWeiwei Li
Fix lines with over 80 characters. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructionsWeiwei Li
Currently decomp_rv32 and decomp_rv64 value in opcode_data for vector instructions are the same op index as their own. And they have no functional decomp_data. So they have no functional difference from just leaving them as zero. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13disas/riscv.c: Support disas for Z*inx extensionsWeiwei Li
Support disas for Z*inx instructions only when Zfinx extension is supported. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13disas/riscv.c: Support disas for Zcm* extensionsWeiwei Li
Support disas for Zcmt* instructions only when related extensions are supported. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-06-13target/riscv: Pass RISCVCPUConfig as target_info to disassemble_infoWeiwei Li
Pass RISCVCPUConfig as disassemble_info.target_info to support disas of conflict instructions related to specific extensions. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230523093539.203909-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-05-25disas/riscv: Decode czero.{eqz,nez}Richard Henderson
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11disas: Move disas.c into the target-independent source setThomas Huth
Use target_words_bigendian() instead of an ifdef. Remove CONFIG_RISCV_DIS from the check for riscv as a host; this is a poisoned identifier, and anyway will always be set by meson.build when building on a riscv host. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20230508133745.109463-3-thuth@redhat.com> [rth: Type change done in a separate patch] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11disas: Move softmmu specific code to separate fileThomas Huth
We'd like to move disas.c into the common code source set, where CONFIG_USER_ONLY is not available anymore. So we have to move the related code into a separate file instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20230508133745.109463-2-thuth@redhat.com> [rth: Type change done in a separate patch] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11disas: Remove target-specific headersRichard Henderson
Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230503072331.1747057-83-richard.henderson@linaro.org>
2023-05-11disas: Remove target_ulong from the interfaceRichard Henderson
Use uint64_t for the pc, and size_t for the size. Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230503072331.1747057-81-richard.henderson@linaro.org>
2023-05-11disas: Move disas.c to disas/Richard Henderson
Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230503072331.1747057-80-richard.henderson@linaro.org>
2023-05-05disas/riscv.c: add disasm support for Zc*Weiwei Li
Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* instructions currently. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-10-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-03-14Fix incorrect register name in disassembler for fmv,fabs,fneg instructionsMikhail Tyutin
Fix incorrect register name in RISC-V disassembler for fmv,fabs,fneg instructions Signed-off-by: Mikhail Tyutin <m.tyutin@yadro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <3454991f-7f64-24c3-9a36-f5fa2cc389e1@yadro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-03-14disas/riscv: Fix slli_uw decodingIvan Klokov
The decoding of the slli_uw currently contains decoding error: shamt part of opcode has six bits, not five. Fixes 3de1fb71("target/riscv: update disas.c for xnor/orn/andn and slli.uw") Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230227090228.17117-1-ivan.klokov@syntacore.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-03-05disas/riscv Fix ctzw disassembleIvan Klokov
Due to typo in opcode list, ctzw is disassembled as clzw instruction. Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions") Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230217151459.54649-1-ivan.klokov@syntacore.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-02-07target/riscv: update disas.c for xnor/orn/andn and slli.uwPhilipp Tomsich
The decoding of the following instructions from Zb[abcs] currently contains decoding/printing errors: * xnor,orn,andn: the rs2 operand is not being printed * slli.uw: decodes and prints the immediate shift-amount as a register (e.g. 'shift-by-2' becomes 'sp') instead of interpreting this as an immediate This commit updates the instruction descriptions to use the appropriate decoding/printing formats. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230120151551.1022761-1-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-01-13mips: Always include nanomips disassemblerPaolo Bonzini
Since the nanomips disassembler is not C++ code anymore, it need not depend on link_language == cpp. Always include it and remove the CONFIG_NANOMIPS_DIS symbol. Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20230110084942.299460-1-pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-11-08disas/nanomips: Tidy read for 48-bit opcodesRichard Henderson
There is no point in looking for a 48-bit opcode if we've not read the second word for a 32-bit opcode. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221106023735.5277-5-richard.henderson@linaro.org>
2022-11-08disas/nanomips: Split out read_u16Richard Henderson
Split out a helper function for reading a uint16_t with the correct endianness. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221106023735.5277-4-richard.henderson@linaro.org>
2022-11-08disas/nanomips: Merge insn{1,2,3} into words[3]Richard Henderson
Since Disassemble wants the data in this format, collect it that way. This allows using a loop to print the bytes. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221106212852.152384-3-richard.henderson@linaro.org>
2022-11-08disas/nanomips: Move setjmp into nanomips_disRichard Henderson
Reduce the number of local variables within the scope of the setjmp by moving it to the existing helper. The actual length returned from Disassemble is not used, because we have already determined the length while reading bytes. Fixes: nanomips.c: In function ‘print_insn_nanomips’: nanomips.c:21925:14: error: variable ‘insn1’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] nanomips.c:21925:25: error: variable ‘insn2’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] nanomips.c:21925:36: error: variable ‘insn3’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] nanomips.c:21926:22: error: variable ‘buf’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221106212852.152384-2-richard.henderson@linaro.org>
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