aboutsummaryrefslogtreecommitdiff
path: root/disas
AgeCommit message (Expand)Author
2024-04-08nanomips: fix warnings with GCC 14Paolo Bonzini
2024-03-29disas: Show opcodes for target_disas and monitor_disasRichard Henderson
2024-03-06target/riscv: honour show_opcodes when disassemblingAlex Bennée
2024-03-06disas/hppa: honour show_opcodesAlex Bennée
2024-03-06disas: introduce show_opcodesAlex Bennée
2024-02-11disas/hppa: Add disassembly for qemu specific instructionsHelge Deller
2024-01-30disas/riscv: Clean up includesPeter Maydell
2024-01-10disas/riscv: Add amocas.[w,d,q] instructionsRob Bradford
2023-11-24disas/cris: Pass buffer size to format_dec() to avoid overflow warningPhilippe Mathieu-Daudé
2023-11-17disas/hppa: Show hexcode of instruction along with disassemblyHelge Deller
2023-11-07disas/riscv: Replace TABs with spaceMax Chou
2023-11-07disas/riscv: Add support for vector crypto extensionsMax Chou
2023-11-07disas/riscv: Add rv_codec_vror_vi for vror.viMax Chou
2023-11-07disas/riscv: Add rv_fmt_vd_vs2_uimm formatMax Chou
2023-10-12disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14Alvin Chang
2023-09-29disas/m68k: clean up local variable shadowingLaurent Vivier
2023-07-19riscv/disas: Fix disas output of upper immediatesChristoph Müllner
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner
2023-07-10target/riscv: Add disas support for BF16 extensionsWeiwei Li
2023-07-10disas/riscv: Add support for XThead* instructionsChristoph Müllner
2023-07-10disas/riscv: Add support for XVentanaCondOpsChristoph Müllner
2023-07-10disas/riscv: Provide infrastructure for vendor extensionsChristoph Müllner
2023-07-10disas/riscv: Encapsulate opcode_data into decodeChristoph Müllner
2023-07-10disas/riscv: Make rv_op_illegal a shared enum valueChristoph Müllner
2023-07-10disas/riscv: Move types/constants to new header fileChristoph Müllner
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé
2023-06-13disas/riscv.c: Remove redundant parenthesesWeiwei Li
2023-06-13disas/riscv.c: Fix lines with over 80 charactersWeiwei Li
2023-06-13disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructionsWeiwei Li
2023-06-13disas/riscv.c: Support disas for Z*inx extensionsWeiwei Li
2023-06-13disas/riscv.c: Support disas for Zcm* extensionsWeiwei Li
2023-06-13target/riscv: Pass RISCVCPUConfig as target_info to disassemble_infoWeiwei Li
2023-05-25disas/riscv: Decode czero.{eqz,nez}Richard Henderson
2023-05-11disas: Move disas.c into the target-independent source setThomas Huth
2023-05-11disas: Move softmmu specific code to separate fileThomas Huth
2023-05-11disas: Remove target-specific headersRichard Henderson
2023-05-11disas: Remove target_ulong from the interfaceRichard Henderson
2023-05-11disas: Move disas.c to disas/Richard Henderson
2023-05-05disas/riscv.c: add disasm support for Zc*Weiwei Li
2023-03-14Fix incorrect register name in disassembler for fmv,fabs,fneg instructionsMikhail Tyutin
2023-03-14disas/riscv: Fix slli_uw decodingIvan Klokov
2023-03-05disas/riscv Fix ctzw disassembleIvan Klokov
2023-02-07target/riscv: update disas.c for xnor/orn/andn and slli.uwPhilipp Tomsich
2023-01-13mips: Always include nanomips disassemblerPaolo Bonzini
2022-11-08disas/nanomips: Tidy read for 48-bit opcodesRichard Henderson
2022-11-08disas/nanomips: Split out read_u16Richard Henderson
2022-11-08disas/nanomips: Merge insn{1,2,3} into words[3]Richard Henderson
2022-11-08disas/nanomips: Move setjmp into nanomips_disRichard Henderson
2022-11-08disas/nanomips: Remove headers already included by "qemu/osdep.h"Philippe Mathieu-Daudé
2022-11-08disas/nanomips: Use G_GNUC_PRINTF to avoid invalid string formatsPhilippe Mathieu-Daudé