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2022-10-31disas/nanomips: Remove #include <sstream>Milica Lazarevic
<sstream> is a C++ library and it's not used by disassembler. Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220912122635.74032-13-milica.lazarevic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31disas/nanomips: Delete nanomips.hMilica Lazarevic
Header file nanomips.h has been deleted for the nanomips disassembler to stay consistent with the rest of the disassemblers which don't include extra header files. Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220912122635.74032-12-milica.lazarevic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31disas/nanomips: Move typedefs etc to nanomips.cppMilica Lazarevic
The following is moved from the nanomips.h to nanomips.cpp file: - #include line - typedefs - enums - definition of the Pool struct. Header file nanomips.h will be deleted to be consistent with the rest of the disas/ code. Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220912122635.74032-11-milica.lazarevic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31disas/nanomips: Remove NMD classMilica Lazarevic
NMD class has been deleted. The following methods are now declared as static functions: - public NMD::Disassemble method - private NMD::Disassemble method - private NMD::extract_op_code_value helper method Also, the implementation of the print_insn_nanomips function and nanomips_dis function is moved to the end of the nanomips.cpp file, right after the implementation of the Disassemble function. Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220912122635.74032-10-milica.lazarevic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31disas/nanomips: Remove Pool tables from the classMilica Lazarevic
Pool tables are no longer declared as static fields of the NMD class but as global static const variables. Pool struct is defined outside of the class. The NMD::Disassemble method is using the MAJOR Pool table variable, so its implementation is moved to the end of the nanomips.cpp file, right after the initialization of the MAJOR Pool table. Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220912122635.74032-9-milica.lazarevic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31disas/nanomips: Remove disasm methods from classMilica Lazarevic
NMD class methods with the disassembly_function type like NMD::ABS_D, NMD::ABS_S, etc. are removed from the class. They're now declared global static functions. Therefore, typedef of the function pointer, disassembly_function is defined outside of the class. Now that disassembly_function type functions are not part of the NMD class we can't access them using the this pointer. Thus, the use of the this pointer has been deleted. Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220912122635.74032-8-milica.lazarevic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31disas/nanomips: Remove __cond methods from classMilica Lazarevic
NMD class methods with the conditional_function type like NMD::ADDIU_32__cond, NMD::ADDIU_RS5__cond, etc. are removed from the NMD class. They're now declared global static functions. Therefore, typedef of the function pointer, conditional_function is defined outside of the class. Now that conditional_function type functions are not part of the NMD class we can't access them using the this pointer. Thus, the use of the this pointer has been deleted. Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220912122635.74032-7-milica.lazarevic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31disas/nanomips: Remove helper methods from classMilica Lazarevic
Helper methods from NMD class like NMD::renumber_registers, NMD::decode_gpr_gpr4... etc. are removed from the class. They're now declared global static functions. Following helper methods have been deleted because they're not used by the nanomips disassembler: - NMD::encode_msbd_from_pos_and_size, - NMD::encode_s_from_s_hi, - NMD::neg_copy Global functions used by those methods: - nanomips_dis - sign_extend - extract_bits have also been defined as static global functions. Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220912122635.74032-6-milica.lazarevic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31disas/nanomips: Delete NMD class second fieldMilica Lazarevic
We're deleting the m_pc field of the NMD class. It's now part of the Dis_info struct that this patch introduces. Currently, the Dis_info struct has just one field, m_pc, which we need for address calculation in the ADDRESS function. We're filling Dis_info at the entrance of the nanoMIPS disassembler. I.e. print_insn_nanomips. Next, we're adding that information as an argument wherever we need to. Since NMD class now has no more fields, the NMD constructor is also deleted. Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220912122635.74032-5-milica.lazarevic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31disas/nanomips: Delete NMD class fieldMilica Lazarevic
The m_requested_instruction_categories field always has the same value, ALL_ATTRIBUTES. The only use of that field is within the if statement. When replaced with a specific value, the if statement is always false, so it has been removed. Now, when the only use of the m_requested_instruction_categories field is removed, we can delete the field declaration and initialization in the NMD class. Also, we're changing the way of the construction of the NMD object in the nanomips_dis function. Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220912122635.74032-4-milica.lazarevic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31disas/nanomips: Extract enums out of the NMD classMilica Lazarevic
Definitions of enums TABLE_ENTRY_TYPE and TABLE_ATTRIBUTE_TYPE are moved out of the NMD class. The main goal is to remove NMD class completely. Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220912122635.74032-3-milica.lazarevic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-31disas/nanomips: Remove namespace imgMilica Lazarevic
Since there's no namespace feature in C, namespace img has been replaced with adding the prefix "img" to the namespace members. Prefix "img" has been added to the function names of functions that used to be wrapped in namespace img. Those are img::format() functions. I.e. replaced img::format with the img_format. Typedef address that used to belong to namespace img now is called img_address. Signed-off-by: Milica Lazarevic <milica.lazarevic@syrmia.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220912122635.74032-2-milica.lazarevic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-14disas/riscv.c: rvv: Add disas support for vector instructionsYang Liu
Tested with https://github.com/ksco/rvv-decoder-tests Expected checkpatch errors for consistency and brevity reasons: ERROR: line over 90 characters ERROR: trailing statements should be on next line ERROR: braces {} are necessary for all arms of this statement Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220928051842.16207-1-liuyang22@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-10-06disas: use result of ->read_memory_funcAlex Bennée
This gets especially confusing if you start plugging in host addresses from a trace and you wonder why the output keeps changing. Report when read_memory_func fails instead of blindly disassembling the buffer contents. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220929114231.583801-35-alex.bennee@linaro.org>
2022-09-27target/riscv: Remove sideleg and sedelegRahul Pathak
sideleg and sedeleg csrs are not part of riscv isa spec anymore, these csrs were part of N extension which is removed from the riscv isa specification. These commits removed all traces of these csrs from riscv spec (https://github.com/riscv/riscv-isa-manual) - commit f8d27f805b65 ("Remove or downgrade more references to N extension (#674)") commit b6cade07034d ("Remove N extension chapter for now") Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220824145255.400040-1-rpathak@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: fix shifts shamt value for rv128cFrédéric Pétrot
For rv128c shifts, a shamt of 0 is a shamt of 64, while for rv32c/rv64c it stays 0 and is a hint instruction that does not change processor state. For rv128c right shifts, the 6-bit shamt is in addition sign extended to 7 bits. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220710110451.245567-1-frederic.petrot@univ-grenoble-alpes.fr> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-07-05disas: Remove libvixl disassemblerThomas Huth
The disassembly via capstone should be superiour to our old vixl sources nowadays, so let's finally cut this old disassembler out of the QEMU source tree. Message-Id: <20220603164249.112459-1-thuth@redhat.com> Tested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-09disas: Remove old libopcode ppc disassemblerThomas Huth
Capstone should be superior to the old libopcode disassembler, so we can drop the old file nowadays. Message-Id: <20220505173619.488350-1-thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-09disas: Remove old libopcode i386 disassemblerThomas Huth
Capstone should be superior to the old libopcode disassembler, so we can drop the old file nowadays. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220412165836.355850-4-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-09disas: Remove old libopcode arm disassemblerThomas Huth
Capstone should be superior to the old libopcode disassembler, so we can drop the old file nowadays. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220412165836.355850-3-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-04disas: Remove old libopcode s390 disassemblerThomas Huth
Capstone should be superior to the old libopcode disassembler, so we can drop the old file nowadays. Message-Id: <20220412165836.355850-2-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-04-29disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructionsWeiwei Li
Co-authored-by: Ruibo Lu <luruibo2000@163.com> Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-14-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot
This patch adds the support of the '-cpu rv128' option to qemu-system-riscv64 so that we can indicate that we want to run rv128 executables. Still, there is no support for 128-bit insns at that stage so qemu fails miserably (as expected) if launched with this option. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-8-frederic.petrot@univ-grenoble-alpes.fr [ Changed by AF - Rename CPU to "x-rv128" ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22disas/nios2: Simplify endianess conversionPhilippe Mathieu-Daudé
Since commit 12b6e9b27d4 ("disas: Clean up CPUDebug initialization") the disassemble_info->bfd_endian enum is set for all targets in target_disas(). We can directly call print_insn_nios2() and simplify. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210807110939.95853-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-22disas/nios2: Fix style in print_insn_nios2()Philippe Mathieu-Daudé
We are going to modify this function, fix its style first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210807110939.95853-2-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-07disas/riscv: Add Zb[abcs] instructionsPhilipp Tomsich
With the addition of Zb[abcs], we also need to add disassembler support for these new instructions. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-17-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-08-12Hexagon (disas/hexagon.c) fix memory leak for early exit casesTaylor Simpson
Don't allocate the string until error conditions have been checked Fixes: a00cfed0e ("Hexagon (disas) disassembler") Eliminate Coverity CID 1460121 (Resource leak) Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daud? <f4bug@amsat.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-05-25disas/libvixl: Protect C system header for C++ compilerPhilippe Mathieu-Daudé
When selecting an ARM target on Debian unstable, we get: Compiling C++ object libcommon.fa.p/disas_libvixl_vixl_utils.cc.o FAILED: libcommon.fa.p/disas_libvixl_vixl_utils.cc.o c++ -Ilibcommon.fa.p -I. -I.. [...] -o libcommon.fa.p/disas_libvixl_vixl_utils.cc.o -c ../disas/libvixl/vixl/utils.cc In file included from /home/philmd/qemu/disas/libvixl/vixl/utils.h:30, from ../disas/libvixl/vixl/utils.cc:27: /usr/include/string.h:36:43: error: missing binary operator before token "(" 36 | #if defined __cplusplus && (__GNUC_PREREQ (4, 4) \ | ^ /usr/include/string.h:53:62: error: missing binary operator before token "(" 53 | #if defined __USE_MISC || defined __USE_XOPEN || __GLIBC_USE (ISOC2X) | ^ /usr/include/string.h:165:21: error: missing binary operator before token "(" 165 | || __GLIBC_USE (LIB_EXT2) || __GLIBC_USE (ISOC2X)) | ^ /usr/include/string.h:174:43: error: missing binary operator before token "(" 174 | #if defined __USE_XOPEN2K8 || __GLIBC_USE (LIB_EXT2) || __GLIBC_USE (ISOC2X) | ^ /usr/include/string.h:492:19: error: missing binary operator before token "(" 492 | #if __GNUC_PREREQ (3,4) | ^ Relevant information from the host: $ lsb_release -d Description: Debian GNU/Linux 11 (bullseye) $ gcc --version gcc (Debian 10.2.1-6) 10.2.1 20210110 $ dpkg -S /usr/include/string.h libc6-dev: /usr/include/string.h $ apt-cache show libc6-dev Package: libc6-dev Version: 2.31-11 Partially cherry-pick vixl commit 78973f258039f6e96 [*]: Refactor VIXL to use `extern` block when including C header that do not have a C++ counterpart. which is similar to commit 875df03b221 ('osdep: protect qemu/osdep.h with extern "C"'). [*] https://git.linaro.org/arm/vixl.git/commit/?id=78973f258039f6e96 Buglink: https://bugs.launchpad.net/qemu/+bug/1914870 Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20210516171023.510778-1-f4bug@amsat.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-12Drop the deprecated lm32 targetMarkus Armbruster
Target lm32 was deprecated in commit d8498005122, v5.2.0. See there for rationale. Some of its code lives on in device models derived from milkymist ones: hw/char/digic-uart.c and hw/display/bcm2835_fb.c. Cc: Michael Walle <michael@walle.cc> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210503084034.3804963-2-armbru@redhat.com> Acked-by: Michael Walle <michael@walle.cc> [Trivial conflicts resolved, reST markup fixed]
2021-05-12Remove the deprecated moxie targetThomas Huth
There are no known users of this CPU anymore, and there are no binaries available online which could be used for regression tests, so the code has likely completely bit-rotten already. It's been marked as deprecated since two releases now and nobody spoke up that there is still a need to keep it, thus let's remove it now. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210430160355.698194-1-thuth@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [Commit message typos fixed, trivial conflicts resolved] Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-05-10include/disas/dis-asm.h: Handle being included outside 'extern "C"'Peter Maydell
Make dis-asm.h handle being included outside an 'extern "C"' block; this allows us to remove the 'extern "C"' blocks that our two C++ files that include it are using. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2021-04-17osdep: protect qemu/osdep.h with extern "C"Paolo Bonzini
System headers may include templates if compiled with a C++ compiler, which cause the compiler to complain if qemu/osdep.h is included within a C++ source file's 'extern "C"' block. Add an 'extern "C"' block directly to qemu/osdep.h, so that system headers can be kept out of it. There is a stray declaration early in qemu/osdep.h, which needs to be special cased. Add a definition in qemu/compiler.h to make it look nice. config-host.h, CONFIG_TARGET, exec/poison.h and qemu/compiler.h are included outside the 'extern "C"' block; that is not an issue because they consist entirely of preprocessor directives. This allows us to move the include of osdep.h in our two C++ source files outside the extern "C" block they were previously using for it, which in turn means that they compile successfully against newer versions of glib which insist that glib.h is *not* inside an extern "C" block. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210416135543.20382-3-peter.maydell@linaro.org [PMM: Moved disas/arm-a64.cc osdep.h include out of its extern "C" block; explained in commit message why we're doing this] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-17tcg/tci: Implement the disassembler properlyRichard Henderson
Actually print arguments as opposed to simply the opcodes and, uselessly, the argument counts. Reuse all of the helpers developed as part of the interpreter. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-03-09Various spelling fixesMichael Tokarev
An assorted set of spelling fixes in various places. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210309111510.79495-1-mjt@msgid.tls.msk.ru> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-18Hexagon (disas) disassemblerTaylor Simpson
Add hexagon to disas/meson.build Add disas/hexagon.c Add hexagon to include/disas/dis-asm.h Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1612763186-18161-6-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-01-21build-system: clean up TCG/TCI configuryPaolo Bonzini
Make CONFIG_TCG_INTERPRETER a Meson option, and enable TCI (though with a warning) if the host CPU is unsupported, making it more similar to other --enable-* options. Remove TCG-specific include paths from !CONFIG_TCG builds. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-01-07disas: Push const down through host disassemblyRichard Henderson
Reviewed-by: Joelle van Dyne <j@getutm.app> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-12-18disas/libvixl: Fix fall-through annotation for GCC >= 7Thomas Huth
For compiling with -Wimplicit-fallthrough we need to fix the fallthrough annotations in the libvixl code. This is based on the following upstream vixl commit by Martyn Capewell: https://git.linaro.org/arm/vixl.git/commit/?id=de326f850f736c3a337 "GCC 7 enables switch/case fallthrough checking, but this fails in VIXL, because the annotation we use is Clang specific. Also, fix a missing annotation in the disassembler." Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20201211152426.350966-2-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-11-15nomaintainer: Fix Lesser GPL version numberChetan Pant
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. This patch contains all the files, whose maintainer I could not get from ‘get_maintainer.pl’ script. Signed-off-by: Chetan Pant <chetan4windows@gmail.com> Message-Id: <20201023124424.20177-1-chetan4windows@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> [thuth: Adapted exec.c and qdev-monitor.c to new location] Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-11-02disas/capstone: Fix monitor disassembly of >32 bytesPeter Maydell
If we're using the capstone disassembler, disassembly of a run of instructions more than 32 bytes long disassembles the wrong data for instructions beyond the 32 byte mark: (qemu) xp /16x 0x100 0000000000000100: 0x00000005 0x54410001 0x00000001 0x00001000 0000000000000110: 0x00000000 0x00000004 0x54410002 0x3c000000 0000000000000120: 0x00000000 0x00000004 0x54410009 0x74736574 0000000000000130: 0x00000000 0x00000000 0x00000000 0x00000000 (qemu) xp /16i 0x100 0x00000100: 00000005 andeq r0, r0, r5 0x00000104: 54410001 strbpl r0, [r1], #-1 0x00000108: 00000001 andeq r0, r0, r1 0x0000010c: 00001000 andeq r1, r0, r0 0x00000110: 00000000 andeq r0, r0, r0 0x00000114: 00000004 andeq r0, r0, r4 0x00000118: 54410002 strbpl r0, [r1], #-2 0x0000011c: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c 0x00000120: 54410001 strbpl r0, [r1], #-1 0x00000124: 00000001 andeq r0, r0, r1 0x00000128: 00001000 andeq r1, r0, r0 0x0000012c: 00000000 andeq r0, r0, r0 0x00000130: 00000004 andeq r0, r0, r4 0x00000134: 54410002 strbpl r0, [r1], #-2 0x00000138: 3c000000 .byte 0x00, 0x00, 0x00, 0x3c 0x0000013c: 00000000 andeq r0, r0, r0 Here the disassembly of 0x120..0x13f is using the data that is in 0x104..0x123. This is caused by passing the wrong value to the read_memory_func(). The intention is that at this point in the loop the 'cap_buf' buffer already contains 'csize' bytes of data for the instruction at guest addr 'pc', and we want to read in an extra 'tsize' bytes. Those extra bytes are therefore at 'pc + csize', not 'pc'. On the first time through the loop 'csize' happens to be zero, so the initial read of 32 bytes into cap_buf is correct and as long as the disassembly never needs to read more data we return the correct information. Use the correct guest address in the call to read_memory_func(). Cc: qemu-stable@nongnu.org Fixes: https://bugs.launchpad.net/qemu/+bug/1900779 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201022132445.25039-1-peter.maydell@linaro.org
2020-10-03disas/capstone: Add skipdata hook for s390xRichard Henderson
It is always possible to tell the length of an insn, even if the actual insn is unknown. Skip the correct number of bytes, so that we stay in sync with the instruction stream. Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-10-03disas: Split out capstone code to disas/capstone.cRichard Henderson
There is nothing target-specific about this code, so it can be added to common_ss. This also requires that the base capstone dependency be added to common_ss, so that we get the correct include paths added to CFLAGS. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-09-17disas/: fix some comment spelling errorszhaolichang
I found that there are many spelling errors in the comments of qemu, so I used the spellcheck tool to check the spelling errors and finally found some spelling errors in the disas folder. Signed-off-by: zhaolichang <zhaolichang@huawei.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20200917075029.313-9-zhaolichang@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-09-08configure: move disassembler configuration to mesonPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-08-21meson: convert disas directory to MesonMarc-André Lureau
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2020-07-13disas/sh4: Add missing fallthrough annotationsThomas Huth
Add fallthrough annotations to be able to compile the code without warnings with -Wimplicit-fallthrough. Looking at the code, it seems like the fallthrough is indeed intended here, so the comments should be appropriate. Message-Id: <20200630055953.9309-1-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2020-01-29target/mips: Add implementation of GINVT instructionYongbok Kim
Implement emulation of GINVT instruction. As QEMU doesn't support caches and virtualization, this implementation covers only one instruction (GINVT - Global Invalidate TLB) among all TLB-related MIPS instructions. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1579883929-1517-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-12-17libvixl: remove per-target compiler flagsPaolo Bonzini
We are already including -D__STDC_LIMIT_MACROS in the global CXXFLAGS, so it makes sense to do the same for -D__STDC_CONSTANT_MACROS and -D__STDC_FORMAT_MACROS instead of limiting that to libvixl. The -Wno-sign-compare option can also be removed since GCC 4.6 is not supported anymore. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-04cris: do not leak struct cris_disasm_dataPaolo Bonzini
Use a stack-allocated struct to avoid a memory leak. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-08-21ppc: Add support for 'mffsl' instructionPaul A. Clarke
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. This patch adds support for 'mffsl'. 'mffsl' is identical to 'mffs', except it only returns mode, status, and enable bits from the FPSCR. On CPUs without support for 'mffsl' (below ISA 3.0), the 'mffsl' instruction will execute identically to 'mffs'. Note: I renamed FPSCR_RN to FPSCR_RN0 so I could create an FPSCR_RN mask which is both bits of the FPSCR rounding mode, as defined in the ISA. I also fixed a typo in the definition of FPSCR_FR. Signed-off-by: Paul A. Clarke <pc@us.ibm.com> v4: - nit: added some braces to resolve a checkpatch complaint. v3: - Changed tcg_gen_and_i64 to tcg_gen_andi_i64, eliminating the need for a temporary, per review from Richard Henderson. v2: - I found that I copied too much of the 'mffs' implementation. The 'Rc' condition code bits are not needed for 'mffsl'. Removed. - I now free the (renamed) 'tmask' temporary. - I now bail early for older ISA to the original 'mffs' implementation. Message-Id: <1565982203-11048-1-git-send-email-pc@us.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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