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2020-01-29target/mips: Add implementation of GINVT instructionYongbok Kim
Implement emulation of GINVT instruction. As QEMU doesn't support caches and virtualization, this implementation covers only one instruction (GINVT - Global Invalidate TLB) among all TLB-related MIPS instructions. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1579883929-1517-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-12-17libvixl: remove per-target compiler flagsPaolo Bonzini
We are already including -D__STDC_LIMIT_MACROS in the global CXXFLAGS, so it makes sense to do the same for -D__STDC_CONSTANT_MACROS and -D__STDC_FORMAT_MACROS instead of limiting that to libvixl. The -Wno-sign-compare option can also be removed since GCC 4.6 is not supported anymore. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-10-04cris: do not leak struct cris_disasm_dataPaolo Bonzini
Use a stack-allocated struct to avoid a memory leak. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-08-21ppc: Add support for 'mffsl' instructionPaul A. Clarke
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. This patch adds support for 'mffsl'. 'mffsl' is identical to 'mffs', except it only returns mode, status, and enable bits from the FPSCR. On CPUs without support for 'mffsl' (below ISA 3.0), the 'mffsl' instruction will execute identically to 'mffs'. Note: I renamed FPSCR_RN to FPSCR_RN0 so I could create an FPSCR_RN mask which is both bits of the FPSCR rounding mode, as defined in the ISA. I also fixed a typo in the definition of FPSCR_FR. Signed-off-by: Paul A. Clarke <pc@us.ibm.com> v4: - nit: added some braces to resolve a checkpatch complaint. v3: - Changed tcg_gen_and_i64 to tcg_gen_andi_i64, eliminating the need for a temporary, per review from Richard Henderson. v2: - I found that I copied too much of the 'mffs' implementation. The 'Rc' condition code bits are not needed for 'mffsl'. Removed. - I now free the (renamed) 'tmask' temporary. - I now bail early for older ISA to the original 'mffs' implementation. Message-Id: <1565982203-11048-1-git-send-email-pc@us.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-06-27disas/riscv: Fix `rdinstreth` constraintWladimir J. van der Laan
The constraint for `rdinstreth` was comparing the csr number to 0xc80, which is `cycleh` instead. Fix this. Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-27disas/riscv: Disassemble reserved compressed encodings as illegalMichael Clark
Due to the design of the disassembler, the immediate is not known during decoding of the opcode; so to handle compressed encodings with reserved immediate values (non-zero), we need to add an additional check during decompression to match reserved encodings with zero immediates and translate them into the illegal instruction. The following compressed opcodes have reserved encodings with zero immediates: c.addi4spn, c.addi, c.lui, c.addi16sp, c.srli, c.srai, c.andi and c.slli Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> [Palmer: Broke long lines] Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster
No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
2019-05-13Clean up header guards that don't match their file nameMarkus Armbruster
Header guard symbols should match their file name to make guard collisions less likely. Cleaned up with scripts/clean-header-guards.pl, followed by some renaming of new guard symbols picked by the script to better ones. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190315145123.28030-6-armbru@redhat.com> [Rebase to master: update include/hw/net/ne2000-isa.h]
2019-04-18disas: Rename include/disas/bfd.h back to include/disas/dis-asm.hMarkus Armbruster
Commit dc99065b5f9 (v0.1.0) added dis-asm.h from binutils. Commit 43d4145a986 (v0.1.5) inlined bfd.h into dis-asm.h to remove the dependency on binutils. Commit 76cad71136b (v1.4.0) moved dis-asm.h to include/disas/bfd.h. The new name is confusing when you try to match against (pre GPLv3+) binutils. Rename it back. Keep it in the same directory, of course. Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190417191805.28198-17-armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-03-19RISC-V: Remove unnecessary disassembler constraintsMichael Clark
Remove machine generated constraints that are not referenced by the pseudo-instruction constraints. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-03-05disas: nanoMIPS: Add graphical description of pool organizationAleksandar Markovic
Add graphical description of nanoMIPS instruction pool organization. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05disas: nanoMIPS: Correct comments to handlers of some DSP instructionsAleksandar Markovic
Correct comments to handlers of some DSP instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-02-27disas: nanoMIPS: Fix a function misnomerAleksandar Markovic
Rename function extract_ac_13_12() to extract_ac_15_14(). Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551185735-17154-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-01-24disas: nanoMIPS: Amend DSP instructions related commentsAleksandar Markovic
Amend some DSP instructions related comments. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-11remove space-tab sequencesPaolo Bonzini
There are not many, and they are all simple mistakes that ended up being committed. Remove them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20181213223737.11793-2-pbonzini@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-01-03disas: nanoMIPS: Add a note on documentationAleksandar Markovic
Add "nanoMIPS32 Instruction Set Technical Reference Manual" as a reference. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Reorder declarations and definitions of gpr decodersAleksandar Markovic
Reorder declarations and definitions of gpr decoders by number of input bits of corresponding encoding type. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Comment the decoder of 'gpr1' gpr encoding typeAleksandar Markovic
Comment the decoder of 'gpr1' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Rename the decoder of 'gpr1' gpr encoding typeAleksandar Markovic
Rename the decoder of 'gpr1' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Comment the decoder of 'gpr2.reg2' gpr encoding typeAleksandar Markovic
Comment the decoder of 'gpr2.reg2' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Rename the decoder of 'gpr2.reg2' gpr encoding typeAleksandar Markovic
Rename the decoder of 'gpr2.reg2' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Comment the decoder of 'gpr2.reg1' gpr encoding typeAleksandar Markovic
Comment the decoder of 'gpr2.reg1' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Rename the decoder of 'gpr2.reg1' gpr encoding typeAleksandar Markovic
Rename the decoder of 'gpr2.reg1' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Comment the decoder of 'gpr4.zero' gpr encoding typeAleksandar Markovic
Comment the decoder of 'gpr4.zero' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Rename the decoder of 'gpr4.zero' gpr encoding typeAleksandar Markovic
Rename the decoder of 'gpr4.zero' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Comment the decoder of 'gpr4' gpr encoding typeAleksandar Markovic
Comment the decoder of 'gpr4' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Rename the decoder of 'gpr4' gpr encoding typeAleksandar Markovic
Rename the decoder of 'gpr4' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Comment the decoder of 'gpr3.src.store' gpr encoding typeAleksandar Markovic
Comment the decoder of 'gpr3.src.store' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Rename the decoder of 'gpr3.src.store' gpr encoding typeAleksandar Markovic
Rename the decoder of 'gpr3.src.store' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Comment the decoder of 'gpr3' gpr encoding typeAleksandar Markovic
Comment the decoder of 'gpr3' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Rename the decoder of 'gpr3' gpr encoding typeAleksandar Markovic
Rename the decoder of 'gpr3' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix order of more invocationsAleksandar Markovic
Fix order of extraction function invocations so that extraction goes from MSB side to LSB side of the given instruction coding content. This is desireable because of consistency and easier visual spotting of errors. After this patch, all such invocations should be in the desired order. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Name more functions in a more descriptive wayAleksandar Markovic
Rename more functions that have names that are hard to understand. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix an FP-related misnomer 3Aleksandar Markovic
Rename NMD::extract_ft_20_19_18_17_16(uint64 instruction) to NMD::extract_ft_25_24_23_22_21(uint64 instruction). Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix an FP-related misnomer 2Aleksandar Markovic
Rename NMD::extract_fs_15_14_13_12_11(uint64 instruction) to NMD::extract_fs_20_19_18_17_16(uint64 instruction). Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix an FP-related misnomer 1Aleksandar Markovic
Rename NMD::extract_fd_10_9_8_7_6(uint64 instruction) to NMD::extract_fd_15_14_13_12_11(uint64 instruction). Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Name some functions in a more descriptive wayAleksandar Markovic
Rename some functions that have names that are hard to understand. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix order of some invocationsAleksandar Markovic
Fix order of extraction function invocations so that extraction goes from MSB side to LSB side of the given instruction coding content. This is desireable because of consistency and easier visual spotting of errors. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix a function misnomerAleksandar Markovic
Fix wrong function name. The convention in these files is that names of extraction functions should reflect bit patterns they are extracting. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Remove functions that are not usedAleksandar Markovic
Some functions were not used at all. Compiler doesn't complain since they are class memebers. Remove them - no future usage is planned. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix preamble text in nanomips.* filesAleksandar Markovic
Fix several mistakes in preambles of nanomips disassembler source files. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix types and format stringsStefan Weil
Use POSIX types and format strings. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Weil <sw@weilnetz.de>
2018-12-26disas/microblaze: Remove unused REG_SP macroRichard Henderson
This causes a build error with debian sid, riscv64 host: disas/microblaze.c:179: error: "REG_SP" redefined [-Werror] #define REG_SP 1 /* stack pointer */ In file included from /usr/include/signal.h:306, from include/qemu/osdep.h:101, from disas/microblaze.c:36: /usr/include/riscv64-linux-gnu/sys/ucontext.h:36: note: this is the location of the previous definition # define REG_SP 2 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-21target/ppc: tcg: Implement addex instructionSuraj Jitindar Singh
Implement the addex instruction introduced in ISA V3.00 in qemu tcg. The add extended using alternate carry bit (addex) instruction performs the same operation as the add extended (adde) instruction, but using the overflow (ov) field in the fixed point exception register (xer) as the carry in and out instead of the carry (ca) field. The instruction has a Z23-form, not an XO form, as follows: ------------------------------------------------------------------ | 31 | RT | RA | RB | CY | 170 | 0 | ------------------------------------------------------------------ 0 6 11 16 21 23 31 32 However since the only valid form of the instruction defined so far is CY = 0, we can treat this like an XO form instruction. There is no dot form (addex.) of the instruction and the summary overflow (so) bit in the xer is not modified by this instruction. For simplicity we reuse the gen_op_arith_add function and add a function argument to specify where the carry in input should come from and the carry out output be stored (note must be the same location). Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-10-25target/mips: Add disassembler support for nanoMIPSAleksandar Markovic
Add disassembler support for nanoMIPS. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Matthew Fortune <matthew.fortune@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-08-23fix "Missing break in switch" coverity reportsPaolo Bonzini
Many of these are marked as "intentional/fix required" because they just need adding a fall through comment. This is exactly what this patch does, except for target/mips/translate.c where it is easier to duplicate the code, and hw/audio/sb16.c where I consulted the DOSBox sources and decide to just remove the LOG_UNIMP before the fallthrough. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-07-02target/m68k: correctly disassemble move16Laurent Vivier
"move16 %a0@+,%a1@" and "fmovel (cpid=3) %a0@-,%fpcr" share the same opcode. To fix that, backport the fix from binutils: 2005-11-10 Andreas Schwab <schwab@suse.de> * m68k-dis.c (print_insn_m68k): Only match FPU insns with coprocessor ID 1. Reported-by: Thomas Huth <huth@tuxfamily.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Tested-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20180625203559.21370-2-laurent@vivier.eu>
2018-05-06RISC-V: Fix missing break statement in disassemblerMichael Clark
This fixes an issue when disassembling rv128 c.sqsp, where the code erroneously fell through to c.swsp. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Alistair Francis <Alistair.Francis@wdc.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-05-06RISC-V: Include instruction hex in disassemblyMichael Clark
This was added to help debug issues using -d in_asm. It is useful to see the instruction bytes, as one can detect if one is trying to execute ASCII or device-tree magic. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-03-28RISC-V: Fix incorrect disassembly for addiwMichael Clark
This fixes a bug in the disassembler constraints used to lift instructions into pseudo-instructions, whereby addiw instructions are always lifted to sext.w instead of just lifting addiw with a zero immediate. An associated fix has been made to the metadata used to machine generate the disseasembler: https://github.com/michaeljclark/riscv-meta/ commit/4a6b2f3898430768acfe201405224d2ea31e1477 Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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