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2015-07-21disas/arm-a64: Add missing compiler attribute GCC_FMT_ATTRStefan Weil
Type fprintf_function which fits here was defined with this attribute. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1437208027-14584-1-git-send-email-sw@weilnetz.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-15disas/mips: fix disassembling R6 instructionsYongbok Kim
In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF and CACHE instructions have 9 bits offsets. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2015-07-09tci: Fix compile failure by including qemu-common.hPeter Maydell
Compilation of TCI was accidentally broken by the recent disassembler changes: CC x86_64-softmmu/arch_init.o In file included from target-i386/cpu-qom.h:23:0, from target-i386/cpu.h:986, from include/qemu-common.h:122, from include/disas/bfd.h:12, from disas/tci.c:20: include/qom/cpu.h:178:43: error: unknown type name ‘disassemble_info’ void (*disas_set_info)(CPUState *cpu, disassemble_info *info); ^ include/qom/cpu.h:179:1: error: no semicolon at end of struct or union [-Werror] } CPUClass; ^ cc1: all warnings being treated as errors The underlying cause of this is an include loop: bfd.h -> qemu-common.h -> target-arm/cpu.h -> target-arm/cpu-qom.h -> qom/cpu.h -> bfd.h which means that if bfd.h is included first then qom/cpu.h doesn't get the definition of the disassemble_info type that it wanted. The easiest fix for this is to include qemu-common.h from tci.c before including disas/bfd.h. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-09disas: cris: Fix 0 buffer length casePeter Crosthwaite
Cris has the complication of variable length instructions and has a check in place to clamp memory reads in case the disas request doesn't have enough bytes for the instruction being disas'd. This breaks down in the case where disassembling for the monitor where the buffer length is defaulted to 0. The buffer length should never be zero for a regular target_disas, so we can safely assume the 0 case is for the monitor in which case consider the buffer length to be the max for cris instructions. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2015-07-09disas: arm-a64: Make printfer and stream variablePeter Crosthwaite
In a normal disassembly flow, the printf() and stream being used varies from disas job to job. In particular it varies if mixing monitor_disas and target_disas. Make both the printf() function and target stream settable in the QEMUDisassmbler class. Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com> Tested-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2015-06-12target-mips: add MTHC0 and MFHC0 instructionsLeon Alrae
Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access upper word of extended to 64-bits CP0 registers. In MIPS64, when CP0 destination register specified is the EntryLo0 or EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate functions for EntryLo0 and EntryLo1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-06-11target-mips: add ERETNC instruction and Config5.LLB bitLeon Alrae
ERETNC is identical to ERET except that an ERETNC will not clear the LLbit that is set by execution of an LL instruction, and thus when placed between an LL and SC sequence, will never cause the SC to fail. Presence of ERETNC is denoted by the Config5.LLB. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2015-03-19cris: remove unused cris_cond15 declarationsMichael Tokarev
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Stefan Weil <sw@weilnetz.de>
2015-03-10disas/microblaze: Fix warnings caused by missing 'static' attributeStefan Weil
Warnings from the Sparse static analysis tool: disas/microblaze.c:289:3: warning: symbol 'opcodes' was not declared. Should it be static? disas/microblaze.c:570:6: warning: symbol 'register_prefix' was not declared. Should it be static? disas/microblaze.c:571:6: warning: symbol 'special_register_prefix' was not declared. Should it be static? disas/microblaze.c:572:6: warning: symbol 'fsl_register_prefix' was not declared. Should it be static? disas/microblaze.c:573:6: warning: symbol 'pvr_register_prefix' was not declared. Should it be static? Remove the unused variable special_register_prefix. The variable pvr_register_prefix was unused, too, but can be used. Add also 'const' where possible. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-03-10disas/arm: Fix warnings caused by missing 'static' attributeStefan Weil
Warnings from the Sparse static analysis tool: disas/arm.c:1552:15: warning: symbol 'last_type' was not declared. Should it be static? disas/arm.c:1553:5: warning: symbol 'last_mapping_sym' was not declared. Should it be static? disas/arm.c:1554:9: warning: symbol 'last_mapping_addr' was not declared. Should it be static? Instead of adding 'static', the unused variables and the unused code which refers to those variables (which was deactivated a long time ago in commit 4b0f1a8b) are removed. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-02-10disas/sh4: Fix warning caused by missing 'static' attributeStefan Weil
Warning from the Sparse static analysis tool: disas/sh4.c:335:22: warning: symbol 'sh_table' was not declared. Should it be static? Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-02-05disas/arm-a64.cc: Tell libvixl correct code addressesPeter Maydell
disassembling relative branches in code which doesn't reside at what the guest CPU would think its execution address is. Use the new MapCodeAddress() API to tell libvixl where the code is from the guest CPU's point of view so it can get the target addresses right. Previous disassembly: 0x0000000040000000: 580000c0 ldr x0, pc+24 (addr 0x7f6cb7020434) 0x0000000040000004: aa1f03e1 mov x1, xzr 0x0000000040000008: aa1f03e2 mov x2, xzr 0x000000004000000c: aa1f03e3 mov x3, xzr 0x0000000040000010: 58000084 ldr x4, pc+16 (addr 0x7f6cb702042c) 0x0000000040000014: d61f0080 br x4 Fixed disassembly: 0x0000000040000000: 580000c0 ldr x0, pc+24 (addr 0x40000018) 0x0000000040000004: aa1f03e1 mov x1, xzr 0x0000000040000008: aa1f03e2 mov x2, xzr 0x000000004000000c: aa1f03e3 mov x3, xzr 0x0000000040000010: 58000084 ldr x4, pc+16 (addr 0x40000020) 0x0000000040000014: d61f0080 br x4 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1422274779-13359-3-git-send-email-peter.maydell@linaro.org
2015-02-05disas/libvixl: Update to upstream VIXL 1.7Peter Maydell
Update our copy of libvixl to upstream's 1.7 release. This includes upstream's fix for the issue we had a local patch for in commit 94cc44a9e. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1422274779-13359-2-git-send-email-peter.maydell@linaro.org
2015-02-03disas/s390.c: Remove unused variablesPeter Maydell
The variables s390_opformats and s390_num_opformats are unused and provoke clang warnings: disas/s390.c:849:33: warning: variable 's390_opformats' is not needed and will not be emitted [-Wunneeded-internal-declaration] static const struct s390_opcode s390_opformats[] = ^ disas/s390.c:875:18: warning: unused variable 's390_num_opformats' [-Wunused-const-variable] static const int s390_num_opformats = ^ Delete them, since QEMU doesn't use them. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-id: 1419373100-17690-3-git-send-email-peter.maydell@linaro.org Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-01-21disas/sparc: Remove unused data sparc_opcode_archs[]Peter Maydell
Remove sparc_opcode_archs and the macros which use it, because we don't use them in QEMU and they provoke clang warnings: disas/sparc.c:307:39: warning: unused variable 'sparc_opcode_archs' [-Wunused-const-variable] static const struct sparc_opcode_arch sparc_opcode_archs[] = ^ Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-12-16disas/mips: disable unused mips16_to_32_reg_map[]Leon Alrae
This array is used by print_mips16_insn_arg() which is guarded by #if 0. Therefore doing the same with the array as it generates clang warnings. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-12-16disas/mips: remove unused mips_msa_control_names_numeric[32]Leon Alrae
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2014-11-03disas/mips.c: disassemble MSA instructionsYongbok Kim
disassemble MIPS SIMD Architecture instructions Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-11-03target-mips: add TLBINV supportLeon Alrae
For Standard TLB configuration (Config.MT=1): TLBINV invalidates a set of TLB entries based on ASID. The virtual address is ignored in the entry match. TLB entries which have their G bit set to 1 are not modified. TLBINVF causes all entries to be invalidated. Single TLB entry can be marked as invalid on TLB entry write by having EntryHi.EHINV set to 1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-10-24disas/libvixl/a64/instructions-a64.h: Remove unused constantsChen Gang
The instructions-a64.h header defines a number of floating point constants whose initializers are function calls. gcc 5 will warn if these constants are not used by the C or C++ file which includes the header, because they imply a runtime cost. Since for the files QEMU uses from libvixl we don't use these constants at all, just remove them. Upstream intend to fix these by shifting to an 'extern const' in the header plus definition in a suitable source file, so we can drop this patch when we sync with the upcoming libvixl 1.7. The related compiling error: CXX disas/arm-a64.o In file included from /upstream/qemu/disas/libvixl/a64/disasm-a64.h:32:0, from disas/arm-a64.cc:20: disas/libvixl/a64/instructions-a64.h:98:13: error: 'vixl::kFP32PositiveInfinity' defined but not used [-Werror=unused-variable] const float kFP32PositiveInfinity = rawbits_to_float(0x7f800000); ^ disas/libvixl/a64/instructions-a64.h:99:13: error: 'vixl::kFP32NegativeInfinity' defined but not used [-Werror=unused-variable] const float kFP32NegativeInfinity = rawbits_to_float(0xff800000); ^ disas/libvixl/a64/instructions-a64.h:100:14: error: 'vixl::kFP64PositiveInfinity' defined but not used [-Werror=unused-variable] const double kFP64PositiveInfinity = ^ disas/libvixl/a64/instructions-a64.h:102:14: error: 'vixl::kFP64NegativeInfinity' defined but not used [-Werror=unused-variable] const double kFP64NegativeInfinity = ^ disas/libvixl/a64/instructions-a64.h:107:21: error: 'vixl::kFP64SignallingNaN' defined but not used [-Werror=unused-variable] static const double kFP64SignallingNaN = ^ disas/libvixl/a64/instructions-a64.h:109:20: error: 'vixl::kFP32SignallingNaN' defined but not used [-Werror=unused-variable] static const float kFP32SignallingNaN = rawbits_to_float(0x7f800001); ^ disas/libvixl/a64/instructions-a64.h:112:21: error: 'vixl::kFP64QuietNaN' defined but not used [-Werror=unused-variable] static const double kFP64QuietNaN = ^ disas/libvixl/a64/instructions-a64.h:114:20: error: 'vixl::kFP32QuietNaN' defined but not used [-Werror=unused-variable] static const float kFP32QuietNaN = rawbits_to_float(0x7fc00001); ^ disas/libvixl/a64/instructions-a64.h:117:21: error: 'vixl::kFP64DefaultNaN' defined but not used [-Werror=unused-variable] static const double kFP64DefaultNaN = ^ disas/libvixl/a64/instructions-a64.h:119:20: error: 'vixl::kFP32DefaultNaN' defined but not used [-Werror=unused-variable] static const float kFP32DefaultNaN = rawbits_to_float(0x7fc00000); ^ cc1plus: all warnings being treated as errors make: *** [disas/arm-a64.o] Error 1 Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> [PMM: Rewrote the commit message a little] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-10-24disas/libvixl: Update to libvixl 1.6Peter Maydell
Update our copy of libvixl to upstream 1.6. There are no changes of any particular interest to QEMU, so this is simply keeping up with current upstream. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1412091418-25744-1-git-send-email-peter.maydell@linaro.org
2014-10-14target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructionsYongbok Kim
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-14target-mips: add new Floating Point Comparison instructionsYongbok Kim
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-14target-mips: add new Floating Point instructionsLeon Alrae
In terms of encoding MIPS32R6 MIN.fmt, MAX.fmt, MINA.fmt, MAXA.fmt replaced MIPS-3D RECIP1, RECIP2, RSQRT1, RSQRT2 instructions. In R6 all Floating Point instructions are supposed to be IEEE-2008 compliant i.e. FIR.HAS2008 always 1. However, QEMU softfloat for MIPS has not been updated yet. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-10-14target-mips: add AUI, LSA and PCREL instruction familiesLeon Alrae
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
2014-10-13target-mips: add compact and CP1 branchesYongbok Kim
Introduce MIPS32R6 Compact Branch instructions which do not have delay slot - they have forbidden slot instead. However, current implementation does not support forbidden slot yet. Add also BC1EQZ and BC1NEZ instructions. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2014-10-13target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructionsYongbok Kim
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-13target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6Leon Alrae
Also consider OPC_SPIM instruction as deleted in R6 because it is overlaping with MIPS32R6 SDBBP. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-13target-mips: redefine Integer Multiply and Divide instructionsLeon Alrae
Use "R6_" prefix in front of all new Multiply / Divide instructions for easier differentiation between R6 and preR6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-13target-mips: move PREF, CACHE, LLD and SCD instructionsLeon Alrae
The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6. Additionally, the hint codes in PREF instruction greater than or equal to 24 generate Reserved Instruction Exception. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
2014-10-13target-mips: move LL and SC instructionsLeon Alrae
The encoding of LL and SC instruction has changed in MIPS32 Release 6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: James Hogan <james.hogan@imgtec.com>
2014-10-13target-mips: add SELEQZ and SELNEZ instructionsLeon Alrae
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: James Hogan <james.hogan@imgtec.com>
2014-09-29tcg-sparc: Use UMULXHI instructionRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-09-29tcg-sparc: Rename ADDX/SUBX insnsRichard Henderson
The pre-v9 ADDX/SUBX insns were renamed ADDC/SUBC for v9. Standardizing on the v9 name makes things less confusing. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-09-29tcg-sparc: Use ADDXC in addsub2_i64Richard Henderson
On T4 and newer Sparc chips we have an add-with-carry insn that takes its input from %xcc instead of %icc. Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-08-29disas/libvixl: Update to upstream VIXL 1.5Peter Maydell
Update our copy of libvixl to upstream's 1.5 release. This includes the upstream versions of the fixes we were carrying locally (commit ffebe899). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1407162987-4659-1-git-send-email-peter.maydell@linaro.org
2014-07-08disas/libvixl: prepend the include path of libvixl header filesStefano Stabellini
Currently the Makefile of disas/libvixl appends -I$(SRC_PATH)/disas/libvixl to QEMU_CFLAGS. As a consequence C++ files that #include "utils.h", such as disas/libvixl/a64/instructions-a64.cc, are going to look for utils.h on all the other include paths first. When building QEMU as part of the Xen make system, another unrelated utils.h file is going to be chosen for inclusion, causing a build failure: In file included from disas/libvixl/a64/instructions-a64.cc:27:0: /qemu/disas/libvixl/a64/instructions-a64.h:88:64: error: 'rawbits_to_float' was not declared in this scope const float kFP32PositiveInfinity = rawbits_to_float(0x7f800000); Fix the problem by prepending (rather than appending) the libvixl include path to QEMU_CFLAGS. Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-29disas/libvixl: Fix wrong format stringsStefan Weil
When the compiler is told to check the arguments of AppendToOutput, it reports several errors of this kind: error: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘int64_t {aka long int}’ [-Werror=format] Fix those bugs by using the correct format strings with PRId64, PRIx64. Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1403113751-19799-1-git-send-email-sw@weilnetz.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-06-29disas/libvixl: Update README for version baseRichard Henderson
Signed-off-by: Richard Henderson <rth@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-05-13disas/libvixl: Update to libvixl 1.4Peter Maydell
Update our copy of libvixl to upstream's 1.4 release. Note that we no longer need any local fixes for compilation on 32 bit hosts -- they have all been integrated upstream. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1399040419-9227-1-git-send-email-peter.maydell@linaro.org Acked-by: Richard Henderson <rth@twiddle.net>
2014-05-08build: convert some obj-specific CFLAGS to use new foo.o-cflags syntaxMichael Tokarev
Current Makefile system allows using foo.o-cflags variables to store object-specific CFLAGS. Convert some usages of old syntax (using QEMU_CFLAGS += construct) to the new syntax. Do not touch multifile modules for now, as build system isn't ready for this. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2014-03-10libvixl: Fix format strings for several int64_t valuesStefan Weil
"%d" or "%x" won't work on hosts where int values are smaller than 64 bit. Signed-off-by: Stefan Weil <sw@weilnetz.de> Message-id: 1394219753-26106-1-git-send-email-sw@weilnetz.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-17disas/i386: Disassemble ANDN/SHLX/SHRX/SHAXRichard Henderson
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2014-02-15libvixl: fix 64bit constants usageMichael Tokarev
Since commit 999b53ec8794f203964db3ecf939a3da5c4bc843: Author: Claudio Fontana <claudio.fontana@linaro.org> Date: Wed Feb 5 17:27:28 2014 +0000 disas: Implement disassembly output for A64 Use libvixl to implement disassembly output in debug logs for A64, for use with both AArch64 hosts and targets. disas/libvixl/ contains functions which uses 64bit constants without using appropriate suffixes, which fails on 32bits. Fix this by using ULL suffix. Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08disas: Implement disassembly output for A64Claudio Fontana
Use libvixl to implement disassembly output in debug logs for A64, for use with both AArch64 hosts and targets. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> [PMM: * added support for target disassembly * switched to custom QEMUDisassembler so the output format matches what QEMU expects * make sure we correctly fall back to "just print hex" if we didn't build the AArch64 disassembler because of lack of a C++ compiler * rename from 'aarch64' to 'arm-a64' because this is a disassembler for the A64 instruction set * merge aarch64.c and aarch64-cxx.cc into one C++ file * simplify the aarch64.c<->aarch64-cxx.cc interface] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-02-08disas/libvixl: Fix upstream libvixl compilation issuesPeter Maydell
Fix various minor issues with upstream libvixl so that it will compile successfully on the platforms QEMU cares about: * remove unused GBytes constant (it clashes with the glib headers) * fix suffixes on constants to use 'LL' for 64 bit constants so we can compile on 32 bit hosts Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-02-08disas: Add subset of libvixl sources for A64 disassemblerPeter Maydell
Add the subset of the libvixl sources that are needed for the A64 disassembler support. These sources come from https://github.com/armvixl/vixl commit 578645f14e122d2b which is VIXL release 1.1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-01-25disas/i386.c: disassemble movbe instructionAurelien Jarno
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-09-02disas/ppc.c: Fix little endian disassemblyAnton Blanchard
Use info->endian to select the endian of the instruction to be disassembled. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-27tcg-arm: Implement division instructionsRichard Henderson
An armv7 extension implements division, present on Cortex A15. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
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