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path: root/disas/riscv.c
AgeCommit message (Expand)Author
2024-07-18disas/riscv: Add decode for Zawrs extensionBalaji Ravikumar
2024-07-18disas/riscv: Support zabha disassembleLIU Zhiwei
2024-07-18disas/riscv: Support zcmop disassembleLIU Zhiwei
2024-07-18disas/riscv: Support zimop disassembleLIU Zhiwei
2024-06-05disas/riscv: Use GString in format_instRichard Henderson
2024-06-03disas/riscv: Decode all of the pmpcfg and pmpaddr CSRsAlistair Francis
2024-03-06target/riscv: honour show_opcodes when disassemblingAlex Bennée
2024-01-10disas/riscv: Add amocas.[w,d,q] instructionsRob Bradford
2023-11-07disas/riscv: Replace TABs with spaceMax Chou
2023-11-07disas/riscv: Add support for vector crypto extensionsMax Chou
2023-11-07disas/riscv: Add rv_codec_vror_vi for vror.viMax Chou
2023-10-12disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14Alvin Chang
2023-07-19riscv/disas: Fix disas output of upper immediatesChristoph Müllner
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner
2023-07-10target/riscv: Add disas support for BF16 extensionsWeiwei Li
2023-07-10disas/riscv: Add support for XThead* instructionsChristoph Müllner
2023-07-10disas/riscv: Add support for XVentanaCondOpsChristoph Müllner
2023-07-10disas/riscv: Provide infrastructure for vendor extensionsChristoph Müllner
2023-07-10disas/riscv: Encapsulate opcode_data into decodeChristoph Müllner
2023-07-10disas/riscv: Make rv_op_illegal a shared enum valueChristoph Müllner
2023-07-10disas/riscv: Move types/constants to new header fileChristoph Müllner
2023-06-13disas/riscv.c: Remove redundant parenthesesWeiwei Li
2023-06-13disas/riscv.c: Fix lines with over 80 charactersWeiwei Li
2023-06-13disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructionsWeiwei Li
2023-06-13disas/riscv.c: Support disas for Z*inx extensionsWeiwei Li
2023-06-13disas/riscv.c: Support disas for Zcm* extensionsWeiwei Li
2023-06-13target/riscv: Pass RISCVCPUConfig as target_info to disassemble_infoWeiwei Li
2023-05-25disas/riscv: Decode czero.{eqz,nez}Richard Henderson
2023-05-05disas/riscv.c: add disasm support for Zc*Weiwei Li
2023-03-14Fix incorrect register name in disassembler for fmv,fabs,fneg instructionsMikhail Tyutin
2023-03-14disas/riscv: Fix slli_uw decodingIvan Klokov
2023-03-05disas/riscv Fix ctzw disassembleIvan Klokov
2023-02-07target/riscv: update disas.c for xnor/orn/andn and slli.uwPhilipp Tomsich
2022-10-14disas/riscv.c: rvv: Add disas support for vector instructionsYang Liu
2022-09-27target/riscv: Remove sideleg and sedelegRahul Pathak
2022-09-07target/riscv: fix shifts shamt value for rv128cFrédéric Pétrot
2022-04-29disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructionsWeiwei Li
2022-01-08target/riscv: setup everything for rv64 to support rv128 executionFrédéric Pétrot
2021-10-07disas/riscv: Add Zb[abcs] instructionsPhilipp Tomsich
2019-06-27disas/riscv: Fix `rdinstreth` constraintWladimir J. van der Laan
2019-06-27disas/riscv: Disassemble reserved compressed encodings as illegalMichael Clark
2019-04-18disas: Rename include/disas/bfd.h back to include/disas/dis-asm.hMarkus Armbruster
2019-03-19RISC-V: Remove unnecessary disassembler constraintsMichael Clark
2018-05-06RISC-V: Fix missing break statement in disassemblerMichael Clark
2018-05-06RISC-V: Include instruction hex in disassemblyMichael Clark
2018-03-28RISC-V: Fix incorrect disassembly for addiwMichael Clark
2018-03-07RISC-V DisassemblerMichael Clark
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