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2018-12-21target/ppc: tcg: Implement addex instructionSuraj Jitindar Singh
Implement the addex instruction introduced in ISA V3.00 in qemu tcg. The add extended using alternate carry bit (addex) instruction performs the same operation as the add extended (adde) instruction, but using the overflow (ov) field in the fixed point exception register (xer) as the carry in and out instead of the carry (ca) field. The instruction has a Z23-form, not an XO form, as follows: ------------------------------------------------------------------ | 31 | RT | RA | RB | CY | 170 | 0 | ------------------------------------------------------------------ 0 6 11 16 21 23 31 32 However since the only valid form of the instruction defined so far is CY = 0, we can treat this like an XO form instruction. There is no dot form (addex.) of the instruction and the summary overflow (so) bit in the xer is not modified by this instruction. For simplicity we reuse the gen_op_arith_add function and add a function argument to specify where the carry in input should come from and the carry out output be stored (note must be the same location). Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-31disas/ppc: Fix indefinite articles in commentsStefan Weil
Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-10disas/ppc: Handle popcnt and cnttzRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-11-15target-ppc: add vrldnm and vrlwnm instructionsBharata B Rao
vrldnm: Vector Rotate Left Doubleword then AND with Mask vrlwnm: Vector Rotate Left Word then AND with Mask Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-11-15target-ppc: add vrldnmi and vrlwmi instructionsGautham R. Shenoy
vrldmi: Vector Rotate Left Dword then Mask Insert vrlwmi: Vector Rotate Left Word then Mask Insert Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com> Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> ( use extract[32,64] and rol[32,64], introduce mask helpers in internal.h ) Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-18disas: Remove unused macro '_'Lluís Vilanova
Eliminates a future compilation error when UI code includes the tracing headers (indirectly pulling "disas/bfd.h" through "qom/cpu.h") and GLib's i18n '_' macro. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-01-29ppc: Clean up includesPeter Maydell
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-6-git-send-email-peter.maydell@linaro.org
2013-09-02disas/ppc.c: Fix little endian disassemblyAnton Blanchard
Use info->endian to select the endian of the instruction to be disassembled. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>