| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-10-21 | openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC) | Stafford Horne | |
| Add OpenRISC Multicore PIC which handles inter processor interrupts (IPI) between cores. In OpenRISC all device interrupts are routed to each core enabling this device to be simple. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com> | |||
| 2017-02-14 | target/openrisc: Rename the cpu from or32 to or1k | Richard Henderson | |
| This is in keeping with the toolchain and or1ksim. Signed-off-by: Richard Henderson <rth@twiddle.net> | |||
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index : slackcoder/qemu | |
| QEMU is a generic and open source machine & userspace emulator and virtualizer | Mirror |
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