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2019-02-21hw/arm/musca.c: Implement models of the Musca-A and -B1 boardsPeter Maydell
The Musca-A and Musca-B1 development boards are based on the SSE-200 subsystem for embedded. Implement an initial skeleton model of these boards, which are similar but not identical. This commit creates the board model with the SSE and the IRQ splitters to wire IRQs up to its two CPUs. As yet there are no devices and no memory: these will be added later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-05hw/vfio/Makefile.objs: Create new CONFIG_* variables for VFIO core and PCIPaolo Bonzini
Make hw/vfio configurable and add new CONFIG_VFIO_* to the default-configs/s390x*-softmmu.mak. This allow a finer-grain selection of the various VFIO backends. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190202072456.6468-28-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-05hw/i2c/Makefile.objs: Create new CONFIG_* variables for EEPROM and ACPI ↵Paolo Bonzini
controller Create separate variables for these components, they are used in many boards but not all. This allows finer-grain selection of the included code with default-configs/*.mak. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190202072456.6468-27-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-05hw/arm/Makefile.objs: CONFIG_ARM_VIRT created for virt boardYang Zhong
Make ARM virt code configurable and the new CONFIG_ARM_VIRT definitions added to the default-configs/arm-softmmu.mak. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190202072456.6468-8-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-05hw/pci-host/Makefile.objs: make CONFIGS clear for PCI EXPRESSYang Zhong
Change the CONFIGs for PCI EXPRESS and make module name more clear for code files. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Cc: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190202072456.6468-5-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-05arm: disable CONFIG_SERIAL_ISAPaolo Bonzini
ARM should not have an ISA bus, this device should not be enabled. Kconfig allows to clean up the dependencies and remove CONFIG_ISA_BUS=y from ARM, and then catches a contradiction between the hardcoded CONFIG_SERIAL_ISA=y and CONFIG_ISA_BUS=n. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190202072456.6468-2-yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-02-01hw/misc/armsse-cpuid: Implement SSE-200 CPU_IDENTITY register blockPeter Maydell
The SSE-200 has a CPU_IDENTITY register block, which is a set of read-only registers. As well as the usual PID/CID registers, there is a single CPUID register which indicates whether the CPU is CPU 0 or CPU 1. Implement a model of this register block. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-20-peter.maydell@linaro.org
2019-02-01hw/arm/iotkit: Rename files to hw/arm/armsse.[ch]Peter Maydell
Rename the files that used to be iotkit.[ch] to armsse.[ch] to reflect the fact they new cover multiple Arm subsystems for embedded. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190121185118.18550-8-peter.maydell@linaro.org
2018-09-25arm: Add Nordic Semiconductor nRF51 SoCJoel Stanley
The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at this stage. Signed-off-by: Joel Stanley <joel@jms.id.au> Message-id: 20180831220920.27113-3-joel@jms.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: wrapped a few long lines] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-24hw/misc/tz-msc: Model TrustZone Master Security ControllerPeter Maydell
Implement a model of the TrustZone Master Securtiy Controller, as documented in the Arm CoreLink SIE-200 System IP for Embedded TRM (DDI0571G): https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g The MSC is intended to sit in front of a device which can be a bus master (eg a DMA controller) and programmably gate its transactions. This allows a bus-mastering device to be controlled by non-secure code but still restricted from making accesses to addresses which are secure-only. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180820141116.9118-12-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2018-08-24hw/misc/iotkit-sysinfo: Implement IoTKit system information blockPeter Maydell
Implement the IoTKit system control element's system information block; this is just a pair of read-only version/config registers, plus the usual PID/CID ID registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-10-peter.maydell@linaro.org
2018-08-24hw/misc/iotkit-sysctl: Implement IoTKit system control elementPeter Maydell
The Arm IoTKit includes a system control element which provides a block of read-only ID registers and a block of read-write control registers. Implement a minimal version of this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-9-peter.maydell@linaro.org
2018-08-24hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer modulePeter Maydell
The Arm Cortex-M System Design Kit includes a "dual-input timer module" which combines two programmable down-counters. Implement a model of this device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180820141116.9118-4-peter.maydell@linaro.org
2018-08-20hw/watchdog/cmsdk_apb_watchdog: Implement CMSDK APB watchdog modulePeter Maydell
The Arm Cortex-M System Design Kit includes a simple watchdog module based on a 32-bit down-counter. Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-16i.MX6UL: Add i.MX6UL SOCJean-Christophe Dubois
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Message-id: 3853ec555d68e7e25d726170833b775796151a07.1532984236.git.jcd@tribudubois.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection ControllerPeter Maydell
Implement the Arm TrustZone Memory Protection Controller, which sits in front of RAM and allows secure software to configure it to either pass through or reject transactions. We implement the MPC as a QEMU IOMMU, which will direct transactions either through to the devices and memory behind it or to a special "never works" AddressSpace if they are blocked. This initial commit implements the skeleton of the device: * it always permits accesses * it doesn't implement most of the registers * it doesn't implement the interrupt or other behaviour for blocked transactions Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20180620132032.28865-2-peter.maydell@linaro.org
2018-06-08misc: add pca9552 LED blinker modelCédric Le Goater
Specs are available here : https://www.nxp.com/docs/en/application-note/AN264.pdf This is a simple model supporting the basic registers for led and GPIO mode. The device also supports two blinking rates but not the model yet. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180530064049.27976-7-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-01hw: make virtio devices configurable via default-configs/Paolo Bonzini
This is only half of the work, because the proxy devices (virtio-*-pci, virtio-*-ccw, etc.) are still included unconditionally. It is still a move in the right direction. Based-on: <20180522194943.24871-1-pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-03-09hw/arm: Use more CONFIG switches for the object filesThomas Huth
A lot of ARM object files are linked into the executable unconditionally, even though we have corresponding CONFIG switches like CONFIG_PXA2XX or CONFIG_OMAP. We should make sure to use these switches in the Makefile so that the users can disable certain unwanted boards and devices more easily. While we're at it, also add some new switches for the boards that do not have a CONFIG option yet. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1520266949-29817-1-git-send-email-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-09i.MX: Add i.MX7 SOC implementation.Andrey Smirnov
The following interfaces are partially or fully emulated: * up to 2 Cortex A9 cores (SMP works with PSCI) * A7 MPCORE (identical to A15 MPCORE) * 4 GPTs modules * 7 GPIO controllers * 2 IOMUXC controllers * 1 CCM module * 1 SVNS module * 1 SRC module * 1 GPCv2 controller * 4 eCSPI controllers * 4 I2C controllers * 7 i.MX UART controllers * 2 FlexCAN controllers * 2 Ethernet controllers (FEC) * 3 SD controllers (USDHC) * 4 WDT modules * 1 SDMA module * 1 GPR module * 2 USBMISC modules * 2 ADC modules * 1 PCIe controller Tested to boot and work with upstream Linux (4.13+) guest. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [PMM: folded a couple of long lines] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-09pci: Add support for Designware IP blockAndrey Smirnov
Add code needed to get a functional PCI subsytem when using in conjunction with upstream Linux guest (4.13+). Tested to work against "e1000e" (network adapter, using MSI interrupts) as well as "usb-ehci" (USB controller, using legacy PCI interrupts). Based on "i.MX6 Applications Processor Reference Manual" (Document Number: IMX6DQRM Rev. 4) as well as corresponding dirver in Linux kernel (circa 4.13 - 4.16 found in drivers/pci/dwc/*) Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-02hw/arm/iotkit: Model Arm IOT KitPeter Maydell
Model the Arm IoT Kit documented in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html The Arm IoT Kit is a subsystem which includes a CPU and some devices, and is intended be extended by adding extra devices to form a complete system. It is used in the MPS2 board's AN505 image for the Cortex-M33. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-19-peter.maydell@linaro.org
2018-03-02hw/misc/iotkit-secctl: Arm IoT Kit security controller initial skeletonPeter Maydell
The Arm IoT Kit includes a "security controller" which is largely a collection of registers for controlling the PPCs and other bits of glue in the system. This commit provides the initial skeleton of the device, implementing just the ID registers, and a couple of read-only read-as-zero registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-16-peter.maydell@linaro.org
2018-03-02hw/misc/tz-ppc: Model TrustZone peripheral protection controllerPeter Maydell
Add a model of the TrustZone peripheral protection controller (PPC), which is used to gate transactions to non-TZ-aware peripherals so that secure software can configure them to not be accessible to non-secure software. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-15-peter.maydell@linaro.org
2018-03-02hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505Peter Maydell
The MPS2 AN505 FPGA image includes a "FPGA control block" which is a small set of registers handling LEDs, buttons and some counters. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-14-peter.maydell@linaro.org
2018-03-01arm/vexpress: Add proper display connector emulationLinus Walleij
This adds the SiI9022 (and implicitly EDID I2C) device to the ARM Versatile Express machine, and selects the two I2C devices necessary in the arm-softmmu.mak configuration so everything will build smoothly. I am implementing proper handling of the graphics in the Linux kernel and adding proper emulation of SiI9022 and EDID makes the driver probe as nicely as before, retrieving the resolutions supported by the "QEMU monitor" and overall just working nice. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Message-id: 20180227104903.21353-6-linus.walleij@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-02-05i2c: Add a CONFIG_I2C master switch to the configuration filesThomas Huth
The i2c core and the at24c EEPROM should only be compiled and linked on the machines that support i2c. Otherwise it's quite strange to see the at24c-eeprom to be "available" on qemu-system-s390x for example. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <1516634853-15883-1-git-send-email-thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-12-13xilinx_spips: Add support for the ZynqMP Generic QSPIFrancisco Iglesias
Add support for the Zynq Ultrascale MPSoc Generic QSPI. Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20171126231634.9531-13-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-11-16build-sys: restrict vmcoreinfo to fw_cfg+dma capable targetsMarc-André Lureau
vmcoreinfo is built for all targets. However, it requires fw_cfg with DMA operations support (write operation). Restrict vmcoreinfo exposure to architectures that are supporting FW_CFG_DMA, that is arm-virt and x86 only atm. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com> Tested-by: Daniel Henrique Barboza <danielhb@linux.vnet.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-09-21msf2: Add Smartfusion2 SoCSubbaraya Sundeep
Smartfusion2 SoC has hardened Microcontroller subsystem and flash based FPGA fabric. This patch adds support for Microcontroller subsystem in the SoC. Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170920201737.25723-5-f4bug@amsat.org [PMD: drop cpu_model to directly use cpu type, check m3clk non null] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-17hw/misc/mps2_scc: Implement MPS2 Serial Communication ControllerPeter Maydell
Implement a model of the Serial Communication Controller (SCC) found in MPS2 FPGA images. The primary purpose of this device is to communicate with the Motherboard Configuration Controller (MCC) which is located on the MPS board itself, outside the FPGA image. This is used for programming the MPS clock generators. The SCC also has some basic ID registers and an output for the board LEDs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1500029487-14822-7-git-send-email-peter.maydell@linaro.org
2017-07-17hw/char/cmsdk-apb-timer: Implement CMSDK APB timer devicePeter Maydell
Implement a model of the simple timer device found in the CMSDK. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1500029487-14822-5-git-send-email-peter.maydell@linaro.org
2017-07-17hw/char/cmsdk-apb-uart.c: Implement CMSDK APB UARTPeter Maydell
Implement a model of the simple "APB UART" provided in the Cortex-M System Design Kit (CMSDK). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1500029487-14822-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-07-17hw/arm/mps2: Implement skeleton mps2-an385 and mps2-an511 board modelsPeter Maydell
Model the ARM MPS2/MPS2+ FPGA based development board. The MPS2 and MPS2+ dev boards are FPGA based (the 2+ has a bigger FPGA but is otherwise the same as the 2). Since the CPU itself and most of the devices are in the FPGA, the details of the board as seen by the guest depend significantly on the FPGA image. We model the following FPGA images: "mps2_an385" -- Cortex-M3 as documented in ARM Application Note AN385 "mps2_an511" -- Cortex-M3 'DesignStart' as documented in AN511 They are fairly similar but differ in the details for some peripherals. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1500029487-14822-2-git-send-email-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-06-13hw/misc: add a TMP42{1, 2, 3} device modelCédric Le Goater
Largely inspired by the TMP105 temperature sensor, here is a model for the TMP42{1,2,3} temperature sensors. Specs can be found here : http://www.ti.com/lit/gpn/tmp421 Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1496739230-32109-2-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2017-04-24net: add FTGMAC100 supportCédric Le Goater
The FTGMAC100 device is an Ethernet controller with DMA function that can be found on Aspeed SoCs (which include NCSI). It is fully compliant with IEEE 802.3 specification for 10/100 Mbps Ethernet and IEEE 802.3z specification for 1000 Mbps Ethernet and includes Reduced Media Independent Interface (RMII) and Reduced Gigabit Media Independent Interface (RGMII) interfaces. It adopts an AHB bus interface and integrates a link list DMA engine with direct M-Bus accesses for transmitting and receiving packets. It has independent TX/RX fifos, supports half and full duplex (1000 Mbps mode only supports full duplex), flow control for full duplex and backpressure for half duplex. The FTGMAC100 also implements IP, TCP, UDP checksum offloads and supports IEEE 802.1Q VLAN tag insertion and removal. It offers high-priority transmit queue for QoS and CoS applications This model is backed with a RealTek 8211E PHY which is the chip found on the AST2500 EVB. It is complete enough to satisfy two different Linux drivers and a U-Boot driver. Not supported features are : - IEEE 802.1Q VLAN - High Priority Transmit Queue - Wake-On-LAN functions The code is based on the Coldfire Fast Ethernet Controller model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2017-02-28armv7m: Don't put core v7M devices under CONFIG_STELLARISPeter Maydell
The NVIC is a core v7M device that exists for all v7M CPUs; put it under a CONFIG_ARM_V7M rather than hiding it under CONFIG_STELLARIS. (We'll use CONFIG_ARM_V7M for the SysTick device too when we split it out of the NVIC.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-9-git-send-email-peter.maydell@linaro.org
2017-02-10hw/vfio: Add CONFIG switches for calxeda-xgmac and amd-xgbeThomas Huth
Both devices seem to be specific to the ARM platform. It's confusing for the users if they show up on other target architectures, too (e.g. when the user runs QEMU with "-device ?" to get a list of supported devices). Thus let's introduce proper configuration switches so that the devices are only compiled and included when they are really required. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2017-02-06Split serial-isa into its own config optionDavid Gibson
At present, the core device model code for 8250-like serial ports (serial.c) and the code for serial ports attached to ISA-style legacy IO (serial-isa.c) are both controlled by the CONFIG_SERIAL variable. There are lots and lots of embedded platforms that have 8250-like serial ports but have never had anything resembling ISA legacy IO. Therefore, split serial-isa into its own CONFIG_SERIAL_ISA option so it can be disabled for platforms where it's not appropriate. For now, I enabled CONFIG_SERIAL_ISA in every default-config where CONFIG_SERIAL is enabled, excepting microblaze, or32, and xtensa. As best as I can tell, those platforms never used legacy ISA, and also don't include PCI support (which would allow connection of a PCI->ISA bridge and/or a southbridge including legacy ISA serial ports). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
2017-02-01hw/pcie: Introduce a base class for PCI Express Root PortsMarcel Apfelbaum
The 'base' PCI Express Root Port includes the common code to be re-used for all Root Ports implementations. Most of the code was taken from the current implementation of Intel's IOH 3420 Root Port. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-10-04STM32F2xx: Add the SPI deviceAlistair Francis
Add the STM32F2xx SPI device. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 8197811d5c94f814fa67c6a33ca2f7fd0aa97432.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-10-04STM32F2xx: Add the ADC deviceAlistair Francis
Add the STM32F2xx ADC device. This device randomly generates values on each read. This also includes creating a hw/adc directory. Signed-off-by: Alistair Francis <alistair@alistair23.me> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 3240e660adaf537f55a63ce06096e844aece8cda.1474742262.git.alistair@alistair23.me Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-13default-configs: removed obsolete CONFIG_ISA_MMIODaniel P. Berrange
The use of the CONFIG_ISA_MMIO setting was removed in commit 61fcb628627ea464dc1954f615ae13edfefd284f Author: Paolo Bonzini <pbonzini@redhat.com> Date: Mon Jul 22 15:54:24 2013 +0200 isa_mmio: delete but this commit only removed it from some of the default config files. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-Id: <1473096320-1638-3-git-send-email-berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-07-04dma: Add Xilinx Zynq devcfg device modelAlistair Francis
Add a minimal model for the devcfg device which is part of Zynq. This model supports DMA capabilities and interrupt generation. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 83df49d8fa2d203a421ca71620809e4b04754e65.1467053537.git.alistair.francis@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-05-12i.MX: Add i.MX6 SOC implementation.Jean-Christophe DUBOIS
For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 3 I2C controllers * 7 GPIO controllers * 6 SDHC controllers * 5 SPI controllers * 1 CCM device * 1 SRC device * various ROM/RAM areas. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-30hw/gpio: Add the emulation of gpio_keyShannon Zhao
This will be used by ARM virt machine as a power button. Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1458221140-15232-2-git-send-email-zhaoshenglong@huawei.com [PMM: Use hyphen rather than underscore in type names; add a comment briefly describing what the device does] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-16hw/timer: Add ASPEED timer device modelAndrew Jeffery
Implement basic ASPEED timer functionality for the AST2400 SoC[1]: Up to 8 timers can independently be configured, enabled, reset and disabled. Some hardware features are not implemented, namely clock value matching and pulse generation, but the implementation is enough to boot the Linux kernel configured with aspeed_defconfig. [1] http://www.aspeedtech.com/products.php?fPath=20&rId=376 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1458096317-25223-2-git-send-email-andrew@aj.id.au Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-03bcm2835_mbox: add BCM2835 mailboxesAndrew Baumann
This adds the system mailboxes which are used to communicate with a number of GPU peripherals on Pi/Pi2. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07i.MX: Add SOC support for i.MX25Jean-Christophe Dubois
For now we support the following devices: * CPU: ARM926 * Interrupt Controller: AVIC * CCM * UART x 5 * EPIT x 2 * GPT x 4 * FEC * I2C x 3 Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-id: 62218bfa90f9101f79098e768c3d58bd92dcb7f3.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-09-07i.MX: Add FEC Ethernet EmulatorJean-Christophe Dubois
This is based on mcf_fec.c FEC implementation for Coldfire * A generic PHY was added (borrowwed from LAN9118) * The buffer management is also modified as buffers are slightly different between Coldfire and i.MX Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: fb314f8a120aa49f8f6ad886f312c649b484fb5a.1441057361.git.jcd@tribudubois.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-23 14:06:29 +0000