Age | Commit message (Collapse) | Author |
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reworked cr8 handling - added CPUState.hflags2
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generation and is practially always cleared.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4597 c046a42c-6fe2-441c-8c8c-71466251a162
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Rearrange interrupt handling to match other targets.
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* Dont flush the entire qemu tlb when the $pid changes. Instead we go through
the guests TLB and choose entries that need to be flushed.
* Add env->dslot and handle delayslots at pageboundaries.
* Remove some unused code.
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This patch allows the qemu backend debugger to single step an
instruction without running the hardware interrupts.
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* Support both the I and D MMUs and improve the accuracy of the MMU model.
* Handle the automatic user/kernel stack pointer switching when leaving or entering user mode.
* Move the CCS evaluation into helper funcs.
* Make sure user-mode cannot change flags only writeable in kernel mode.
* More conversion of the translator into TCG.
* Handle exceptions while in a delayslot.
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(Jan Kiszka)
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(Stuart Brady)
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(Stefan Weil)
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* Clean up the interrupt handling a bit.
* Connect some NOR flash to the test board.
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allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
and using the same definition in code translation code.
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the regex.
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