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AgeCommit message (Expand)Author
2019-02-11cputlb: update TLB entry/index after tlb_fillEmilio G. Cota
2019-02-07Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190206' into stagingPeter Maydell
2019-02-06accel/tcg: Consider cluster index in tb_lookup__cpu_state()Peter Maydell
2019-02-05cpu-exec: reset BQL after longjmp in cpu_exec_step_atomicEmilio G. Cota
2019-02-05cpu-exec: add assert_no_pages_locked() after longjmpEmilio G. Cota
2019-01-30tcg: Fix LGPL version numberThomas Huth
2019-01-29accel/tcg: Add cluster number to TCG TB hashPeter Maydell
2019-01-29accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs writePeter Maydell
2019-01-28cputlb: Remove static tlb sizingRichard Henderson
2019-01-28tcg: introduce dynamic TLB sizingEmilio G. Cota
2019-01-28cputlb: do not evict empty entries to the vtlbEmilio G. Cota
2019-01-28tcg: Add opcodes for vector minmax arithmeticRichard Henderson
2019-01-28tcg: Add gvec expanders for nand, nor, eqvRichard Henderson
2019-01-11qemu/queue.h: leave head structs anonymous unless necessaryPaolo Bonzini
2019-01-11build-sys: don't include windows.h, osdep.h does itMarc-André Lureau
2019-01-11accel: Improve selection of the default acceleratorThomas Huth
2019-01-07hw: apply accel compat properties without touching globalsMarc-André Lureau
2018-12-26tcg: Add RISC-V cpu signal handlerAlistair Francis
2018-12-11accel: register global_props like machine globalsMarc-André Lureau
2018-10-31cputlb: Remove tlb_c.pending_flushesRichard Henderson
2018-10-31cputlb: Filter flushes on already clean tlbsRichard Henderson
2018-10-31cputlb: Count "partial" and "elided" tlb flushesRichard Henderson
2018-10-31cputlb: Merge tlb_flush_page into tlb_flush_page_by_mmuidxRichard Henderson
2018-10-31cputlb: Merge tlb_flush_nocheck into tlb_flush_by_mmuidx_async_workRichard Henderson
2018-10-31cputlb: Move env->vtlb_index to env->tlb_d.vindexRichard Henderson
2018-10-31cputlb: Split large page tracking per mmu_idxRichard Henderson
2018-10-31cputlb: Move cpu->pending_tlb_flush to env->tlb_c.pending_flushRichard Henderson
2018-10-31cputlb: Remove tcg_enabled hack from tlb_flush_nocheckRichard Henderson
2018-10-31cputlb: Move tlb_lock to CPUTLBCommonRichard Henderson
2018-10-19Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2018-10-19target-i386 : add coalesced_pio APIPeng Hao
2018-10-18cputlb: read CPUTLBEntry.addr_write atomicallyEmilio G. Cota
2018-10-18tcg: Split CONFIG_ATOMIC128Richard Henderson
2018-10-18tcg: Add tlb_index and tlb_entry helpersRichard Henderson
2018-10-18cputlb: serialize tlb updates with env->tlb_lockEmilio G. Cota
2018-10-18cputlb: fix assert_cpu_is_self macroEmilio G. Cota
2018-10-18exec: introduce tlb_initEmilio G. Cota
2018-10-18tcg: access cpu->icount_decr.u16.high with atomicsEmilio G. Cota
2018-10-18tcg: Implement CPU_LOG_TB_NOCHAIN during expansionRichard Henderson
2018-10-02accel/tcg: Remove dead codeThomas Huth
2018-10-02translator: fix breakpoint processingPavel Dovgalyuk
2018-09-26qht: drop ht argument from qht iteratorsEmilio G. Cota
2018-08-23KVM: cleanup unnecessary #ifdef KVM_CAP_...Paolo Bonzini
2018-08-17kvm: Use inhibit to prevent ballooning without synchronous mmuAlex Williamson
2018-08-14accel/tcg: Check whether TLB entry is RAM consistently with how we set it upPeter Maydell
2018-08-14accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code()Peter Maydell
2018-08-14accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAMPeter Maydell
2018-08-14accel/tcg: Handle get_page_addr_code() returning -1 in tb_check_watchpoint()Peter Maydell
2018-08-14accel/tcg: Handle get_page_addr_code() returning -1 in hashtable lookupsPeter Maydell
2018-08-14accel/tcg: Pass read access type through to io_readx()Peter Maydell
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