Age | Commit message (Expand) | Author |
2019-03-11 | accel: Allow to build QEMU without TCG or KVM support | Anthony PERARD |
2019-03-05 | hw/boards: Add a MachineState parameter to kvm_type callback | Eric Auger |
2019-02-14 | kvm: Add kvm_set_ioeventfd* traces | Dr. David Alan Gilbert |
2019-02-11 | cputlb: update TLB entry/index after tlb_fill | Emilio G. Cota |
2019-02-07 | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190206' into staging | Peter Maydell |
2019-02-06 | accel/tcg: Consider cluster index in tb_lookup__cpu_state() | Peter Maydell |
2019-02-05 | cpu-exec: reset BQL after longjmp in cpu_exec_step_atomic | Emilio G. Cota |
2019-02-05 | cpu-exec: add assert_no_pages_locked() after longjmp | Emilio G. Cota |
2019-01-30 | tcg: Fix LGPL version number | Thomas Huth |
2019-01-29 | accel/tcg: Add cluster number to TCG TB hash | Peter Maydell |
2019-01-29 | accel/tcg/user-exec: Don't parse aarch64 insns to test for read vs write | Peter Maydell |
2019-01-28 | cputlb: Remove static tlb sizing | Richard Henderson |
2019-01-28 | tcg: introduce dynamic TLB sizing | Emilio G. Cota |
2019-01-28 | cputlb: do not evict empty entries to the vtlb | Emilio G. Cota |
2019-01-28 | tcg: Add opcodes for vector minmax arithmetic | Richard Henderson |
2019-01-28 | tcg: Add gvec expanders for nand, nor, eqv | Richard Henderson |
2019-01-11 | qemu/queue.h: leave head structs anonymous unless necessary | Paolo Bonzini |
2019-01-11 | build-sys: don't include windows.h, osdep.h does it | Marc-André Lureau |
2019-01-11 | accel: Improve selection of the default accelerator | Thomas Huth |
2019-01-07 | hw: apply accel compat properties without touching globals | Marc-André Lureau |
2018-12-26 | tcg: Add RISC-V cpu signal handler | Alistair Francis |
2018-12-11 | accel: register global_props like machine globals | Marc-André Lureau |
2018-10-31 | cputlb: Remove tlb_c.pending_flushes | Richard Henderson |
2018-10-31 | cputlb: Filter flushes on already clean tlbs | Richard Henderson |
2018-10-31 | cputlb: Count "partial" and "elided" tlb flushes | Richard Henderson |
2018-10-31 | cputlb: Merge tlb_flush_page into tlb_flush_page_by_mmuidx | Richard Henderson |
2018-10-31 | cputlb: Merge tlb_flush_nocheck into tlb_flush_by_mmuidx_async_work | Richard Henderson |
2018-10-31 | cputlb: Move env->vtlb_index to env->tlb_d.vindex | Richard Henderson |
2018-10-31 | cputlb: Split large page tracking per mmu_idx | Richard Henderson |
2018-10-31 | cputlb: Move cpu->pending_tlb_flush to env->tlb_c.pending_flush | Richard Henderson |
2018-10-31 | cputlb: Remove tcg_enabled hack from tlb_flush_nocheck | Richard Henderson |
2018-10-31 | cputlb: Move tlb_lock to CPUTLBCommon | Richard Henderson |
2018-10-19 | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging | Peter Maydell |
2018-10-19 | target-i386 : add coalesced_pio API | Peng Hao |
2018-10-18 | cputlb: read CPUTLBEntry.addr_write atomically | Emilio G. Cota |
2018-10-18 | tcg: Split CONFIG_ATOMIC128 | Richard Henderson |
2018-10-18 | tcg: Add tlb_index and tlb_entry helpers | Richard Henderson |
2018-10-18 | cputlb: serialize tlb updates with env->tlb_lock | Emilio G. Cota |
2018-10-18 | cputlb: fix assert_cpu_is_self macro | Emilio G. Cota |
2018-10-18 | exec: introduce tlb_init | Emilio G. Cota |
2018-10-18 | tcg: access cpu->icount_decr.u16.high with atomics | Emilio G. Cota |
2018-10-18 | tcg: Implement CPU_LOG_TB_NOCHAIN during expansion | Richard Henderson |
2018-10-02 | accel/tcg: Remove dead code | Thomas Huth |
2018-10-02 | translator: fix breakpoint processing | Pavel Dovgalyuk |
2018-09-26 | qht: drop ht argument from qht iterators | Emilio G. Cota |
2018-08-23 | KVM: cleanup unnecessary #ifdef KVM_CAP_... | Paolo Bonzini |
2018-08-17 | kvm: Use inhibit to prevent ballooning without synchronous mmu | Alex Williamson |
2018-08-14 | accel/tcg: Check whether TLB entry is RAM consistently with how we set it up | Peter Maydell |
2018-08-14 | accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code() | Peter Maydell |
2018-08-14 | accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAM | Peter Maydell |