aboutsummaryrefslogtreecommitdiff
path: root/accel/tcg/cputlb.c
AgeCommit message (Expand)Author
2023-05-23accel/tcg: Correctly use atomic128.h in ldst_atomicity.c.incRichard Henderson
2023-05-23accel/tcg: Eliminate #if on HAVE_ATOMIC128 and HAVE_CMPXCHG128Richard Henderson
2023-05-23accel/tcg: Remove prot argument to atomic_mmu_lookupRichard Henderson
2023-05-23accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmuRichard Henderson
2023-05-16tcg: Widen helper_{ld,st}_i128 addresses to uint64_tRichard Henderson
2023-05-16accel/tcg: Widen tcg-ldst.h addresses to uint64_tRichard Henderson
2023-05-16tcg: Add 128-bit guest memory primitivesRichard Henderson
2023-05-16tcg: Unify helper_{be,le}_{ld,st}*Richard Henderson
2023-05-16accel/tcg: Honor atomicity of storesRichard Henderson
2023-05-16accel/tcg: Honor atomicity of loadsRichard Henderson
2023-05-11accel/tcg: Reorg system mode store helpersRichard Henderson
2023-05-11accel/tcg: Reorg system mode load helpersRichard Henderson
2023-05-11accel/tcg: Introduce tlb_read_idxRichard Henderson
2023-05-11accel/tcg: Fix atomic_mmu_lookup for readsRichard Henderson
2023-05-05tcg: Widen helper_*_st[bw]_mmu val argumentsRichard Henderson
2023-05-02accel/tcg: Add cpu_ld*_code_mmuRichard Henderson
2023-05-02accel/tcg: Uncache the host address for instruction fetch when tlb size < 1Weiwei Li
2023-03-05accel/tcg: Trigger watchpoints from atomic_mmu_lookupRichard Henderson
2023-03-05accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookupRichard Henderson
2023-03-05accel/tcg: Retain prot flags from tlb_fillRichard Henderson
2023-02-28accel/tcg: Add 'size' param to probe_access_fullRichard Henderson
2023-02-28accel/tcg: Add 'size' param to probe_access_flags()Daniel Henrique Barboza
2023-02-04tcg: Add guest load/store primitives for TCGv_i128Richard Henderson
2023-02-04accel/tcg: Test CPUJumpCache in tb_jmp_cache_clear_pageEric Auger
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé
2023-01-04accel/tcg: Use QEMU_IOTHREAD_LOCK_GUARD in io_readx/io_writexRichard Henderson
2022-12-20accel/tcg: Factor tb_invalidate_phys_range_fast() outPhilippe Mathieu-Daudé
2022-12-20accel/tcg: Rename tb_invalidate_phys_page_fast{,__locked}()Philippe Mathieu-Daudé
2022-12-20accel/tcg: Remove trace events from trace-root.hPhilippe Mathieu-Daudé
2022-10-04include/hw/core: Create struct CPUJumpCacheRichard Henderson
2022-10-04accel/tcg: Inline tb_flush_jmp_cacheRichard Henderson
2022-10-04accel/tcg: Do not align tb->page_addr[0]Richard Henderson
2022-10-03accel/tcg: Introduce tlb_set_page_fullRichard Henderson
2022-10-03accel/tcg: Introduce probe_access_fullRichard Henderson
2022-10-03accel/tcg: Suppress auto-invalidate in probe_access_internalRichard Henderson
2022-10-03accel/tcg: Drop addr member from SavedIOTLBRichard Henderson
2022-10-03accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFullRichard Henderson
2022-10-03cputlb: used cached CPUClass in our hot-pathsAlex Bennée
2022-09-06accel/tcg: Use probe_access_internal for softmmu get_page_addr_code_hostpRichard Henderson
2022-09-06accel/tcg: Move qemu_ram_addr_from_host_nofail to physmem.cRichard Henderson
2022-09-06accel/tcg: Properly implement get_page_addr_code for user-onlyRichard Henderson
2022-07-12accel/tcg: Fix unaligned stores to s390x low-address-protected lowcoreIlya Leoshkevich
2022-04-26accel/tcg: Assert mmu_idx in range before use in cputlbRichard Henderson
2022-04-20accel/tcg: Remove ATOMIC_MMU_IDXRichard Henderson
2022-03-16accel/tcg: Fix cpu_ldq_be_mmu typoRichard Henderson
2022-02-14Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220211' into...Peter Maydell
2022-02-09tracing: remove TCG memory access tracingAlex Bennée
2022-02-09accel/tcg: Optimize jump cache flush during tlb range flushIdan Horowitz
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot
2021-10-13tcg: Move helper_*_mmu decls to tcg/tcg-ldst.hRichard Henderson
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-12 04:34:10 +0000