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2018-05-08block/mirror: Make cancel always cancel pre-READYMax Reitz
Commit b76e4458b1eb3c32e9824fe6aa51f67d2b251748 made the mirror block job respect block-job-cancel's @force flag: With that flag set, it would now always really cancel, even post-READY. Unfortunately, it had a side effect: Without that flag set, it would now never cancel, not even before READY. Considering that is an incompatible change and not noted anywhere in the commit or the description of block-job-cancel's @force parameter, this seems unintentional and we should revert to the previous behavior, which is to immediately cancel the job when block-job-cancel is called before source and target are in sync (i.e. before the READY event). Cc: qemu-stable@nongnu.org Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1572856 Reported-by: Yanan Fu <yfu@redhat.com> Signed-off-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 20180501220509.14152-2-mreitz@redhat.com Reviewed-by: Jeff Cody <jcody@redhat.com> Signed-off-by: Jeff Cody <jcody@redhat.com>
2018-05-08block/mirror: honor ratelimit againStefan Hajnoczi
Commit b76e4458b1eb3c32e9824fe6aa51f67d2b251748 ("block/mirror: change the semantic of 'force' of block-job-cancel") accidentally removed the ratelimit in the mirror job. Reintroduce the ratelimit but keep the block-job-cancel force=true behavior that was added in commit b76e4458b1eb3c32e9824fe6aa51f67d2b251748. Note that block_job_sleep_ns() returns immediately when the job is cancelled. Therefore it's safe to unconditionally call block_job_sleep_ns() - a cancelled job does not sleep. This commit fixes the non-deterministic qemu-iotests 185 output. The test relies on the ratelimit to make the job sleep until the 'quit' command is processed. Previously the job could complete before the 'quit' command was received since there was no ratelimit. Cc: Liang Li <liliang.opensource@gmail.com> Cc: Jeff Cody <jcody@redhat.com> Cc: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20180424123527.19168-1-stefanha@redhat.com Signed-off-by: Jeff Cody <jcody@redhat.com>
2018-05-08Merge remote-tracking branch 'remotes/kraxel/tags/vga-20180507-pull-request' ↵Peter Maydell
into staging qxl: fix local renderer crash # gpg: Signature made Mon 07 May 2018 10:52:09 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20180507-pull-request: qxl: fix local renderer crash Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-08Merge remote-tracking branch ↵Peter Maydell
'remotes/riscv/tags/riscv-qemu-2.13-pull-20180506' into staging RISC-V: QEMU 2.13 Privileged ISA emulation updates Several code cleanups, minor specification conformance changes, fixes to make ROM read-only and add device-tree size checks. * Honour privileged ISA v1.10 counter enable CSRs. * Implements WARL behavior for CSRs that don't support writes * Past behavior of raising traps was non-conformant with the RISC-V Privileged ISA Specification v1.10. * Allow S-mode access to sstatus.MXR when priv ISA >= v1.10 * Sets mtval/stval to zero on exceptions without addresses * Past behavior of leaving the last value was non-conformant with the RISC-V Privileged ISA Specition v1.10. mtval/stval must be set on all exceptions; to zero if not supported. * Make ROMs read-only and implement device-tree size checks * Uses memory_region_init_rom and rom_add_blob_fixed_as * Adds hexidecimal instruction bytes to disassembly output. * Fixes missing break statement for rv128 disassembly. * Several code cleanups * Replacing hard-coded constants with enums * Dead-code elimination This is an incremental pull that contains 20 reviewed changes out of 38 changes currently queued in the qemu-2.13-for-upstream branch. # gpg: Signature made Sun 06 May 2018 00:27:37 BST # gpg: using DSA key 6BF1D7B357EF3E4F # gpg: Good signature from "Michael Clark <michaeljclark@mac.com>" # gpg: aka "Michael Clark <mjc@sifive.com>" # gpg: aka "Michael Clark <michael@metaparadigm.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7C99 930E B17C D8BA 073D 5EFA 6BF1 D7B3 57EF 3E4F * remotes/riscv/tags/riscv-qemu-2.13-pull-20180506: RISC-V: Mark ROM read-only after copying in code RISC-V: No traps on writes to misa,minstret,mcycle RISC-V: Make mtvec/stvec ignore vectored traps RISC-V: Add mcycle/minstret support for -icount auto RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10 RISC-V: Allow S-mode mxr access when priv ISA >= v1.10 RISC-V: Clear mtval/stval on exceptions without info RISC-V: Hardwire satp to 0 for no-mmu case RISC-V: Update E and I extension order RISC-V: Remove erroneous comment from translate.c RISC-V: Remove EM_RISCV ELF_MACHINE indirection RISC-V: Make virt header comment title consistent RISC-V: Make some header guards more specific RISC-V: Fix missing break statement in disassembler RISC-V: Include instruction hex in disassembly RISC-V: Remove unused class definitions RISC-V: Remove identity_translate from load_elf RISC-V: Use ROM base address and size from memmap RISC-V: Make virt board description match spike RISC-V: Replace hardcoded constants with enum values Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-08Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180507-pull-request' ↵Peter Maydell
into staging usb: fixes for mtp and host. # gpg: Signature made Mon 07 May 2018 10:44:26 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/usb-20180507-pull-request: usb-host: skip open on pending postload bh usb-mtp: Unconditionally check for the readonly bit usb-mtp: Add some NULL checks for issues pointed out by coverity Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-08ppc: e500: use g_strdup_printf() instead of snprintf()Greg Kurz
qemu-system-ppc fails to build with GCC 8.0.1: /home/hsp/src/qemu-master/hw/ppc/e500.c: In function ‘ppce500_load_device_tree’: /home/hsp/src/qemu-master/hw/ppc/e500.c:442:37: error: ‘/pic@’ directive output may be truncated writing 5 bytes into a region of size between 1 and 128 [-Werror=format-truncation=] snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); ^~~~~ In file included from /usr/include/stdio.h:862, from /home/hsp/src/qemu-master/include/qemu/osdep.h:68, from /home/hsp/src/qemu-master/hw/ppc/e500.c:17: /usr/include/bits/stdio2.h:64:10: note: ‘__builtin___snprintf_chk’ output between 11 and 138 bytes into a destination of size 128 return __builtin___snprintf_chk (__s, __n, __USE_FORTIFY_LEVEL - 1, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __bos (__s), __fmt, __va_arg_pack ()); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /home/hsp/src/qemu-master/hw/ppc/e500.c:470:39: error: ‘/global-utilities@’ directive output may be truncated writing 18 bytes into a region of size between 1 and 128 [-Werror=format-truncation=] snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, ^~~~~~~~~~~~~~~~~~ In file included from /usr/include/stdio.h:862, from /home/hsp/src/qemu-master/include/qemu/osdep.h:68, from /home/hsp/src/qemu-master/hw/ppc/e500.c:17: /usr/include/bits/stdio2.h:64:10: note: ‘__builtin___snprintf_chk’ output between 24 and 151 bytes into a destination of size 128 return __builtin___snprintf_chk (__s, __n, __USE_FORTIFY_LEVEL - 1, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __bos (__s), __fmt, __va_arg_pack ()); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /home/hsp/src/qemu-master/hw/ppc/e500.c:477:36: error: ‘/msi@’ directive output may be truncated writing 5 bytes into a region of size between 0 and 127 [-Werror=format-truncation=] snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); ^~~~~ In file included from /usr/include/stdio.h:862, from /home/hsp/src/qemu-master/include/qemu/osdep.h:68, from /home/hsp/src/qemu-master/hw/ppc/e500.c:17: /usr/include/bits/stdio2.h:64:10: note: ‘__builtin___snprintf_chk’ output between 12 and 139 bytes into a destination of size 128 return __builtin___snprintf_chk (__s, __n, __USE_FORTIFY_LEVEL - 1, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ __bos (__s), __fmt, __va_arg_pack ()); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fix this by converting e500 to use g_strdup_printf()+g_free() instead of snprintf(). This is done globally, even for call sites that don't break build, since this is the preferred practice in QEMU. Reported-by: Howard Spoelstra <hsp.cat7@gmail.com> Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 152568372989.443627.900708381919207053.stgit@bahia.lan Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-07qxl: fix local renderer crashGerd Hoffmann
Make sure we only ask the spice local renderer for display updates in case we have a valid primary surface. Without that spice is confused and throws errors in case a display update request (triggered by screendump for example) happens in parallel to a mode switch and hits the race window where the old primary surface is gone and the new isn't establisted yet. Cc: qemu-stable@nongnu.org Fixes: https://bugzilla.redhat.com//show_bug.cgi?id=1567733 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 20180427115528.345-1-kraxel@redhat.com
2018-05-07usb-host: skip open on pending postload bhGerd Hoffmann
usb-host emulates a device unplug after live migration, because the device state is unknown and unplug/replug makes sure the guest re-initializes the device into a working state. This can't be done in post-load though, so post-load just schedules a bottom half which executes after vmload is complete. It can happen that the device autoscan timer hits the race window between scheduling and running the bottom half, which in turn can triggers an assert(). Fix that issue by just ignoring the usb_host_open() call in case the bottom half didn't execute yet. Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1572851 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20180503062932.17233-1-kraxel@redhat.com
2018-05-07usb-mtp: Unconditionally check for the readonly bitBandan Das
Currently, it's only being checked if desc is NULL and so write support breaks upon specifying desc Signed-off-by: Bandan Das <bsd@redhat.com> Message-id: 20180503192028.14353-3-bsd@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-05-07usb-mtp: Add some NULL checks for issues pointed out by coverityBandan Das
CID 1390578: In usb_mtp_write_metadata, parent can never be NULL but just in case, add an assert CID 1390592: Check for o->format only if o !=NULL CID 1390604: Check s->data_out != NULL in usb_mtp_handle_data Signed-off-by: Bandan Das <bsd@redhat.com> Message-id: 20180503192028.14353-2-bsd@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2018-05-06RISC-V: Mark ROM read-only after copying in codeMichael Clark
The sifive_u machine already marks its ROM readonly however it has the wrong base address for its mask ROM. This patch fixes the sifive_u mask ROM base address. This commit makes all other boards consistently use mask_rom as the variable name for their ROMs. Boards that use device tree now check that that the device tree fits in the assigned ROM space using the new qemu_fdt_totalsize(void *fdt) interface, adding a bounds check and error message. This can detect truncation. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <Alistair.Francis@wdc.com>
2018-05-06RISC-V: No traps on writes to misa,minstret,mcycleMichael Clark
These fields are marked WARL (Write Any Values, Reads Legal Values) in the RISC-V Privileged Architecture Specification so instead of raising exceptions, illegal writes are silently dropped. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-05-06RISC-V: Make mtvec/stvec ignore vectored trapsMichael Clark
Vectored traps for asynchrounous interrupts are optional. The mtvec/stvec mode field is WARL and hence does not trap if an illegal value is written. Illegal values are ignored. Later we can add RISCV_FEATURE_VECTORED_TRAPS however until then the correct behavior for WARL (Write Any, Read Legal) fields is to drop writes to unsupported bits. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-05-06RISC-V: Add mcycle/minstret support for -icount autoMichael Clark
Previously the mycycle/minstret CSRs and rdcycle/rdinstret psuedo instructions would return the time as a proxy for an increasing instruction counter in the absence of having a precise instruction count. If QEMU is invoked with -icount, the mcycle/minstret CSRs and rdcycle/rdinstret psuedo instructions will return the instruction count. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10Michael Clark
Privileged ISA v1.9.1 defines mscounteren and mucounteren: * mscounteren contains a mask of counters available to S-mode * mucounteren contains a mask of counters available to U-mode Privileged ISA v1.10 defines mcounteren and scounteren: * mcounteren contains a mask of counters available to S-mode * scounteren contains a mask of counters available to U-mode mcounteren and scounteren CSR registers were implemented however they were not honoured for counter accesses when the privilege ISA was >= v1.10. This fix solves the issue by coalescing the counter enable registers. In addition the code now generates illegal instruction exceptions for accesses to the counter enabled registers depending on the privileged ISA version. - Coalesce mscounteren and mcounteren into one variable - Coalesce mucounteren and scounteren into one variable - Makes mcounteren and scounteren CSR accesses generate illegal instructions when the privileged ISA <= v1.9.1 - Makes mscounteren and mucounteren CSR accesses generate illegal instructions when the privileged ISA >= v1.10 Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com>
2018-05-06RISC-V: Allow S-mode mxr access when priv ISA >= v1.10Michael Clark
The mstatus.MXR alias in sstatus should only be writable by S-mode if the privileged ISA version >= v1.10. Also MXR was masked in sstatus CSR read but not sstatus CSR writes. Now we correctly mask sstatus.mxr in both read and write. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Clear mtval/stval on exceptions without infoMichael Clark
mtval/stval must be set on all exceptions but zero is a legal value if there is no exception specific info. Placing the instruction bytes for illegal instruction exceptions in mtval/stval is an optional feature and is currently not supported by QEMU RISC-V. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Hardwire satp to 0 for no-mmu caseMichael Clark
satp is WARL so it should not trap on illegal writes, rather it can be hardwired to zero and silently ignore illegal writes. It seems the RISC-V WARL behaviour is preferred to having to trap overhead versus simply reading back the value and checking if the write took (saves hundreds of cycles and more complex trap handling code). Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Update E and I extension orderMichael Clark
Section 22.8 Subset Naming Convention of the RISC-V ISA Specification defines the canonical order for extensions in the ISA string. It is silent on the position of the E extension however E is a substitute for I so it must come early in the extension list order. A comment is added to state E and I are mutually exclusive, as the E extension will be added to the RISC-V port in the future. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Remove erroneous comment from translate.cMichael Clark
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Remove EM_RISCV ELF_MACHINE indirectionMichael Clark
Pointless indirection. Other ports use EM_ constants directly. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Make virt header comment title consistentMichael Clark
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Make some header guards more specificMichael Clark
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Fix missing break statement in disassemblerMichael Clark
This fixes an issue when disassembling rv128 c.sqsp, where the code erroneously fell through to c.swsp. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Alistair Francis <Alistair.Francis@wdc.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-05-06RISC-V: Include instruction hex in disassemblyMichael Clark
This was added to help debug issues using -d in_asm. It is useful to see the instruction bytes, as one can detect if one is trying to execute ASCII or device-tree magic. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Remove unused class definitionsMichael Clark
Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Remove identity_translate from load_elfMichael Clark
When load_elf is called with NULL as an argument to the address translate callback, it does an identity translation. This commit removes the redundant identity_translate callback. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Use ROM base address and size from memmapMichael Clark
Another case of replacing hard coded constants, this time referring to the definition in the virt machine's memmap. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Make virt board description match spikeMichael Clark
This makes 'qemu-system-riscv64 -machine help' output more tidy and consistent. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-06RISC-V: Replace hardcoded constants with enum valuesMichael Clark
The RISC-V device-tree code has a number of hard-coded constants and this change moves them into header enums. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
2018-05-04Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20180504-1' into staging target-arm queue: * Emulate the SMMUv3 (IOMMU); one will be created in the 'virt' board if the commandline includes "-machine iommu=smmuv3" * target/arm: Implement v8M VLLDM and VLSTM * hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode * Some fixes to silence Coverity false-positives * arm: boot: set boot_info starting from first_cpu (fixes a technical bug not visible in practice) * hw/net/smc91c111: Convert away from old_mmio * hw/usb/tusb6010: Convert away from old_mmio * hw/char/cmsdk-apb-uart.c: Accept more input after character read * target/arm: Make MPUIR write-ignored on OMAP, StrongARM * hw/arm/virt: Add linux,pci-domain property # gpg: Signature made Fri 04 May 2018 18:54:49 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180504-1: (24 commits) hw/arm/virt: Introduce the iommu option hw/arm/virt-acpi-build: Add smmuv3 node in IORT table hw/arm/virt: Add SMMUv3 to the virt board target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route hw/arm/smmuv3: Abort on vfio or vhost case hw/arm/smmuv3: Implement translate callback hw/arm/smmuv3: Event queue recording helper hw/arm/smmuv3: Implement MMIO write operations hw/arm/smmuv3: Queue helpers hw/arm/smmuv3: Wired IRQ and GERROR helpers hw/arm/smmuv3: Skeleton hw/arm/smmu-common: VMSAv8-64 page table walk hw/arm/smmu-common: IOMMU memory region and address space setup hw/arm/smmu-common: smmu base device and datatypes target/arm: Implement v8M VLLDM and VLSTM hw/arm: Don't fail qtest due to missing SD card in -nodefaults mode target/arm: Tidy condition in disas_simd_two_reg_misc target/arm: Tidy conditions in handle_vec_simd_shri arm: boot: set boot_info starting from first_cpu hw/net/smc91c111: Convert away from old_mmio ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/virt: Introduce the iommu optionEric Auger
ARM virt machine now exposes a new "iommu" option. The SMMUv3 IOMMU is instantiated using -machine virt,iommu=smmuv3. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-15-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/virt-acpi-build: Add smmuv3 node in IORT tablePrem Mallappa
This patch builds the smmuv3 node in the ACPI IORT table. The RID space of the root complex, which spans 0x0-0x10000 maps to streamid space 0x0-0x10000 in smmuv3, which in turn maps to deviceid space 0x0-0x10000 in the ITS group. The guest must feature the IOMMU probe deferral series (https://lkml.org/lkml/2017/4/10/214) which fixes streamid multiple lookup. This bug is not related to the SMMU emulation. Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Shannon Zhao <zhaoshenglong@huawei.com> Message-id: 1524665762-31355-14-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/virt: Add SMMUv3 to the virt boardPrem Mallappa
Add code to instantiate an smmuv3 in virt machine. A new iommu integer member is introduced in VirtMachineState to store the type of the iommu in use. Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-13-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_routeEric Auger
In case the MSI is translated by an IOMMU we need to fixup the MSI route with the translated address. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Message-id: 1524665762-31355-12-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmuv3: Abort on vfio or vhost caseEric Auger
At the moment, the SMMUv3 does not support notification on TLB invalidation. So let's log an error as soon as such notifier gets enabled. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-11-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmuv3: Implement translate callbackEric Auger
This patch implements the IOMMU Memory Region translate() callback. Most of the code relates to the translation configuration decoding and check (STE, CD). Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Message-id: 1524665762-31355-10-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmuv3: Event queue recording helperEric Auger
Let's introduce a helper function aiming at recording an event in the event queue. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-9-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmuv3: Implement MMIO write operationsEric Auger
Now we have relevant helpers for queue and irq management, let's implement MMIO write operations. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-8-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmuv3: Queue helpersEric Auger
We introduce helpers to read/write into the command and event circular queues. smmuv3_write_eventq and smmuv3_cmq_consume will become static in subsequent patches. Invalidation commands are not yet dealt with. We do not cache data that need to be invalidated. This will change with vhost integration. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-7-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmuv3: Wired IRQ and GERROR helpersEric Auger
We introduce some helpers to handle wired IRQs and especially GERROR interrupt. SMMU writes GERROR register on GERROR event and SW acks GERROR interrupts by setting GERRORn. The Wired interrupts are edge sensitive hence the pulse usage. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-6-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmuv3: SkeletonPrem Mallappa
This patch implements a skeleton for the smmuv3 device. Datatypes and register definitions are introduced. The MMIO region, the interrupts and the queue are initialized. Only the MMIO read operation is implemented here. Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-5-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmu-common: VMSAv8-64 page table walkEric Auger
This patch implements the page table walk for VMSAv8-64. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Message-id: 1524665762-31355-4-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmu-common: IOMMU memory region and address space setupEric Auger
We set up the infrastructure to enumerate all the PCI devices attached to the SMMU and create an associated IOMMU memory region and address space. Those info are stored in SMMUDevice objects. The devices are grouped according to the PCIBus they belong to. A hash table indexed by the PCIBus pointer is used. Also an array indexed by the bus number allows to find the list of SMMUDevices. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04hw/arm/smmu-common: smmu base device and datatypesEric Auger
The patch introduces the smmu base device and class for the ARM smmu. Devices for specific versions will be derived from this base device. We also introduce some important datatypes. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Prem Mallappa <prem.mallappa@broadcom.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1524665762-31355-2-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04target/arm: Implement v8M VLLDM and VLSTMPeter Maydell
For v8M the instructions VLLDM and VLSTM support lazy saving and restoring of the secure floating-point registers. Even if the floating point extension is not implemented, these instructions must act as NOPs in Secure state, so they can be used as part of the secure-to-nonsecure call sequence. Fixes: https://bugs.launchpad.net/qemu/+bug/1768295 Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180503105730.5958-1-peter.maydell@linaro.org
2018-05-04hw/arm: Don't fail qtest due to missing SD card in -nodefaults modeThomas Huth
When running omap1/2 or pxa2xx based ARM machines with -nodefaults, they bail out immediately complaining about a "missing SecureDigital device". That's not how the "default" devices in vl.c are meant to work - it should be possible for a board to also start up without default devices. So let's turn the error message and exit() into a warning instead. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 1525326811-3233-1-git-send-email-thuth@redhat.com Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04target/arm: Tidy condition in disas_simd_two_reg_miscRichard Henderson
Path analysis shows that size == 3 && !is_q has been eliminated. Fixes: Coverity CID1385853 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180501180455.11214-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04target/arm: Tidy conditions in handle_vec_simd_shriRichard Henderson
The (size > 3 && !is_q) condition is identical to the preceeding test of bit 3 in immh; eliminate it. For the benefit of Coverity, assert that size is within the bounds we expect. Fixes: Coverity CID1385846 Fixes: Coverity CID1385849 Fixes: Coverity CID1385852 Fixes: Coverity CID1385857 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180501180455.11214-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-05-04arm: boot: set boot_info starting from first_cpuIgor Mammedov
Even though nothing is currently broken (since all boards use first_cpu as boot cpu), make sure that boot_info is set on all CPUs. If some board would like support heterogenuos setup (i.e. init boot_info on subset of CPUs) in future, it should add a reasonable API to do it, instead of starting assigning boot_info from some CPU and till the end of present CPUs list. Ref: "Message-ID: <CAFEAcA_NMWuA8WSs3cNeY6xX1kerO_uAcN_3=fK02BEhHJW86g@mail.gmail.com>" Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1525176522-200354-5-git-send-email-imammedo@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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