slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2024-11-02	linux-headers: loongarch: Add kvm_para.h	Bibo Mao
2024-11-02	linux-headers: Add unistd_64.h	Bibo Mao
2024-11-02	target/loongarch/kvm: Implement LoongArch PMU extension	Bibo Mao
2024-11-02	target/loongarch: Implement lbt registers save/restore function	Bibo Mao
2024-11-02	target/loongarch: Add loongson binary translation feature	Bibo Mao
2024-10-31	Merge tag 'pull-riscv-to-apply-20241031-1' of https://github.com/alistair23/q...	Peter Maydell
2024-10-31	Merge tag 'pull-target-arm-20241029' of https://git.linaro.org/people/pmaydel...	Peter Maydell
2024-10-31	target/riscv: Fix vcompress with rvv_ta_all_1s	Anton Blanchard
2024-10-31	target/riscv/kvm: clarify how 'riscv-aia' default works	Daniel Henrique Barboza
2024-10-31	target/riscv/kvm: set 'aia_mode' to default in error path	Daniel Henrique Barboza
2024-10-31	docs/specs: add riscv-iommu	Daniel Henrique Barboza
2024-10-31	qtest/riscv-iommu-test: add init queues test	Daniel Henrique Barboza
2024-10-31	hw/riscv/riscv-iommu: add DBG support	Tomasz Jeznach
2024-10-31	hw/riscv/riscv-iommu: add ATS support	Tomasz Jeznach
2024-10-31	hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)	Tomasz Jeznach
2024-10-31	test/qtest: add riscv-iommu-pci tests	Daniel Henrique Barboza
2024-10-31	hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug	Tomasz Jeznach
2024-10-31	hw/riscv: add riscv-iommu-pci reference device	Tomasz Jeznach
2024-10-31	pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device	Daniel Henrique Barboza
2024-10-31	hw/riscv: add RISC-V IOMMU base emulation	Tomasz Jeznach
2024-10-31	hw/riscv: add riscv-iommu-bits.h	Tomasz Jeznach
2024-10-31	exec/memtxattr: add process identifier to the transaction attributes	Tomasz Jeznach
2024-10-31	target/riscv: Expose zicfiss extension as a cpu property	Deepak Gupta
2024-10-31	disas/riscv: enable disassembly for compressed sspush/sspopchk	Deepak Gupta
2024-10-31	disas/riscv: enable disassembly for zicfiss instructions	Deepak Gupta
2024-10-30	target/riscv: compressed encodings for sspush and sspopchk	Deepak Gupta
2024-10-30	target/riscv: implement zicfiss instructions	Deepak Gupta
2024-10-30	target/riscv: update `decode_save_opc` to store extra word2	Deepak Gupta
2024-10-30	target/riscv: AMO operations always raise store/AMO fault	Deepak Gupta
2024-10-30	target/riscv: mmu changes for zicfiss shadow stack protection	Deepak Gupta
2024-10-30	target/riscv: tb flag for shadow stack instructions	Deepak Gupta
2024-10-30	target/riscv: introduce ssp and enabling controls for zicfiss	Deepak Gupta
2024-10-30	target/riscv: Add zicfiss extension	Deepak Gupta
2024-10-30	target/riscv: Expose zicfilp extension as a cpu property	Deepak Gupta
2024-10-30	disas/riscv: enable `lpad` disassembly	Deepak Gupta
2024-10-30	target/riscv: zicfilp `lpad` impl and branch tracking	Deepak Gupta
2024-10-30	target/riscv: tracking indirect branches (fcfi) for zicfilp	Deepak Gupta
2024-10-30	target/riscv: additional code information for sw check	Deepak Gupta
2024-10-30	target/riscv: save and restore elp state on priv transitions	Deepak Gupta
2024-10-30	target/riscv: Introduce elp state and enabling controls for zicfilp	Deepak Gupta
2024-10-30	target/riscv: Add zicfilp extension	Deepak Gupta
2024-10-30	target/riscv: expose *envcfg csr and priv to qemu-user as well	Deepak Gupta
2024-10-30	hw/char: sifive_uart: Print uart characters async	Alistair Francis
2024-10-30	hw/char: riscv_htif: Use blocking qemu_chr_fe_write_all	Alistair Francis
2024-10-30	hw/intc/riscv_aplic: Check and update pending when write sourcecfg	Yong-Xuan Wang
2024-10-30	target/riscv: Set vtype.vill on CPU reset	Rob Bradford
2024-10-30	hw/intc: Don't clear pending bits on IRQ lowering	Sergey Makarov
2024-10-30	hw/intc: Make zeroth priority register read-only	Sergey Makarov
2024-10-30	tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU	LIU Zhiwei
2024-10-30	target/riscv: Add max32 CPU for RV64 QEMU	LIU Zhiwei