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2024-09-22linux-user,openrisc: move to syscalltbl fileLaurent Vivier
Since kernel v6.11 openrisc has moved from syscall_nr.h file to syscall.tbl (See 77122bf9e3df ("openrisc: convert to generic syscall table")) Update linux-user scripts to be able to retrieve syscall numbers from linux syscall.tbl instead of syscall_nr.h. New syscall.tbl is imported from linux v6.11 using updated scripts/update-syscalltbl.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240920151034.859533-3-laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22linux-user,aarch64: move to syscalltbl fileLaurent Vivier
Since kernel v6.11 aarch64 has moved from syscall_nr.h file to syscall_64.tbl (See e632bca07c8e ("arm64: generate 64-bit syscall.tbl")) Update linux-user scripts to be able to retrieve syscall numbers from linux syscall_64.tbl instead of syscall_nr.h. New syscall_64.tbl is imported from linux v6.11 using updated scripts/update-syscalltbl.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240920151034.859533-2-laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22linux-user: update syscall.tbl to Linux v6.10Laurent Vivier
Updated running scripts/update-syscalltbl.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240918074256.720617-4-laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22linux-user, mips: update syscall-args-o32.c.inc to Linux v6.10Laurent Vivier
Updated running scripts/update-mips-syscall-args.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240918074256.720617-3-laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22linux-user: update syscall_nr.h to Linux v6.10Laurent Vivier
Automatically generated using scripts/gensyscalls.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-ID: <20240918074256.720617-2-laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22target/ppc: Fix lxvx/stxvx facility checkFabiano Rosas
The XT check for the lxvx/stxvx instructions is currently inverted. This was introduced during the move to decodetree. >From the ISA: Chapter 7. Vector-Scalar Extension Facility Load VSX Vector Indexed X-form lxvx XT,RA,RB if TX=0 & MSR.VSX=0 then VSX_Unavailable() if TX=1 & MSR.VEC=0 then Vector_Unavailable() ... Let XT be the value 32×TX + T. The code currently does the opposite: if (paired || a->rt >= 32) { REQUIRE_VSX(ctx); } else { REQUIRE_VECTOR(ctx); } This was already fixed for lxv/stxv at commit "2cc0e449d1 (target/ppc: Fix lxv/stxv MSR facility check)", but the indexed forms were missed. Cc: qemu-stable@nongnu.org Fixes: 70426b5bb7 ("target/ppc: moved stxvx and lxvx from legacy to decodtree") Signed-off-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Claudio Fontana <cfontana@suse.de> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Message-ID: <20240911141651.6914-1-farosas@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/s390x: Optimize cmpsel with constant 0/-1 argumentsRichard Henderson
These can be simplified to and/or/andc/orc, avoiding the load of the constantinto a register. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/s390x: Implement cmpsel_vecRichard Henderson
Do not allow cmpsel_vec to be expanded early, so that we can make the correct decision wrt the sense of the comparison. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/ppc: Optimize cmpsel with constant 0/-1 argumentsRichard Henderson
These can be simplified to and/or/andc/orc, avoiding the load of the constantinto a register. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/ppc: Implement cmpsel_vecRichard Henderson
Do not allow cmpsel_vec to be expanded early, so that we can make the correct decision wrt the sense of the comparison. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Implement vector TST{EQ,NE} for avx512Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Implement cmpsel_vec with avx512 insnsRichard Henderson
The avx512 vpblendm* instructions exactly implement cmpsel, using a predicate input. Of course this matches nicely with the avx512 predicate comparison instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Add predicate parameters to tcg_out_evex_opcRichard Henderson
Extend tcg_out_evex_opc to handle the predicate and zero-merging parameters of the evex prefix. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Implement cmp_vec with avx512 insnsRichard Henderson
The sse/avx instruction set only has EQ and GT as direct comparisons. Other signed comparisons can be generated from swapping and inversion. However unsigned comparisons are not available and must be transformed to signed comparisons by biasing the inputs. The avx512 instruction set has a complete set of comparisons, with results placed into a predicate register. We can produce the normal cmp_vec result by using VPMOVM2*. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Optimize cmpsel with constant 0 operand 3.Richard Henderson
These can be simplified to and/andc, avoiding the load of the zero into a register. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/optimize: Optimize bitsel_vecRichard Henderson
Fold matching true/false operands. Fold true/false operands with 0/-1 to simpler logicals. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/optimize: Optimize cmp_vec and cmpsel_vecRichard Henderson
Place immediate values second in the comparison. Place destination matches first in the true/false values. All of this mirrors what we do for integer setcond and movcond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/optimize: Fold movcond with true and false values identicalRichard Henderson
Fold "x = cond ? y : y" to "x = y". Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/s390x: Do not expand cmp_vec earlyRichard Henderson
Move expansion to opcode generation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/ppc: Do not expand cmp_vec earlyRichard Henderson
Move expansion to opcode generation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Do not expand cmpsel_vec earlyRichard Henderson
Expand during output instead of during opcode generation. Remove x86_vpblendvb_vec opcode, this this removes the only user. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Do not expand cmp_vec earlyRichard Henderson
Move most of expansion to opcode generation, leaving the conversion of unsigned to signed to be done in the early phase. Small inefficiencies, but not incorrect results, are introduced until cmpsel_vec is converted in the next patch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg/i386: Split out tcg_out_vex_modrm_typeRichard Henderson
Helper function to handle setting of VEXL based on the type of the operation. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg: Export vec_gen_6Richard Henderson
Add declaration to tcg-internal.h, making it available for use from tcg backend vector expanders. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg: Fix iteration step in 32-bit gvec operationTANG Tiancheng
The loop in the 32-bit case of the vector compare operation was incorrectly incrementing by 8 bytes per iteration instead of 4 bytes. This caused the function to process only half of the intended elements. Cc: qemu-stable@nongnu.org Fixes: 9622c697d1 (tcg: Add gvec compare with immediate and scalar operand) Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240904142739.854-2-zhiwei_liu@linux.alibaba.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-22tcg: Propagate new TCGOp to add_as_label_useRichard Henderson
The use of tcg_last_op does not interact well with TCGContext.emit_before_op, resulting in the label being linked to something other than the branch op. In this case it is easier to simply collect the emitted branch op and pass it directly to add_as_label_use. Reported-by: Elisha Hollander <just4now666666@gmail.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22tcg: Return TCGOp from tcg_gen_op[1-6]Richard Henderson
TCGOp to be propagated further in the next patch. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-19Merge tag 'pull-target-arm-20240919' of ↵Peter Maydell
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1 * target/arm: More conversions to decodetree of A64 SIMD insns * hw/char/stm32l4x5_usart.c: Enable USART ACK bit response * tests: update aarch64/sbsa-ref tests * kvm: minor Coverity nit fixes * docs/devel: Remove nested-papr.txt # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmbsIloZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3k96EACgUaTSEX1BNee0Xsk8wIHb # KebGryNymj7LPpWdRxiyQYmZbjfelZPJW7F2tr3iGfiphz+N5TIdRDQlPrRePNg4 # 5Ure0ShRgn+RlkjFe8r9yjrr3HEAXLnVb5fgzPqGEQ+UXWRVzr72+q+wrGFVuXtn # zfqxpc6F0TCxeyH88X6mpKkTeEjfuE++TIf885VVX6nB8qkkDUifRLjdrDcJoxp3 # BRrE0Ntob2W0NAHm/QTbATLDErsYXIzm6pX2hWy3DNEQrVHw2rJ1FAzsjt2J/8ZU # PC7hwmkPBsrnq5wcpBtOwloHzrIYuwUBI7ABPGctCPziCSw7N55vkgUmGWZ+nYHc # DwYGu3H84su0hBi/E9gxl8z/ATBvuAIVa1RLHvbYiwdd088DqxdBe1YLLRaZeKzP # oldQBzVegaN1n5n8tHO43b/38V7uknu3fDXGw/OrsO5DouDAj9NoRil1caRx4ZYd # dr4IiWKzmlW8wpWgoBnrRbycuNsi6b9HblOX1umjwubCGO+GFesBRAInUeg9gbuv # xolfYOScUE/nkTaqulAiPGqGZV8P0fqVMbXmXuowm7iIdw3JihEUm+mU18CTPFBd # P/6SH47lXTaQA0JJQmD4LKraZQFYzm5rlSvW/15/mnzutZXMUlWzvxK/E5fX3vhL # VUguR6XO8Cjb0cQJWohB1w== # =JklH # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Sep 2024 14:08:42 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240919' of https://git.linaro.org/people/pmaydell/qemu-arm: (38 commits) docs/devel: Remove nested-papr.txt target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1 kvm: Remove unreachable code in kvm_dirty_ring_reaper_thread() kvm: Make 'mmap_size' be 'int' in kvm_init_vcpu(), do_kvm_destroy_vcpu() tests: drop OpenBSD tests for aarch64/sbsa-ref tests: expand timeout information for aarch64/sbsa-ref tests: add FreeBSD tests for aarch64/sbsa-ref tests: use default cpu for aarch64/sbsa-ref hw/char/stm32l4x5_usart.c: Enable USART ACK bit response target/arm: Convert scalar [US]QSHRN, [US]QRSHRN, SQSHRUN to decodetree target/arm: Convert vector [US]QSHRN, [US]QRSHRN, SQSHRUN to decodetree target/arm: Convert SQSHL, UQSHL, SQSHLU (immediate) to decodetree target/arm: Widen NeonGenNarrowEnvFn return to 64 bits target/arm: Convert VQSHL, VQSHLU to gvec target/arm: Convert handle_scalar_simd_shli to decodetree target/arm: Convert handle_scalar_simd_shri to decodetree target/arm: Convert SHRN, RSHRN to decodetree target/arm: Split out subroutines of handle_shri_with_rndacc target/arm: Push tcg_rnd into handle_shri_with_rndacc target/arm: Convert SSHLL, USHLL to decodetree ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19docs/devel: Remove nested-papr.txtPeter Maydell
docs/devel/nested-papr.txt is entirely (apart from the initial paragraph) a partial copy of the kernel documentation https://docs.kernel.org/arch/powerpc/kvm-nested.html There's no benefit to the QEMU docs to converting this to rST, so instead delete it. Anybody needing to know the API and protocol for the guest to communicate with the hypervisor to created nested VMs should refer to the authoratitative documentation in the kernel docs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-id: 20240816133318.3603114-1-peter.maydell@linaro.org
2024-09-19target/arm: Correct ID_AA64ISAR1_EL1 value for neoverse-v1Peter Maydell
The Neoverse-V1 TRM is a bit confused about the layout of the ID_AA64ISAR1_EL1 register, and so its table 3-6 has the wrong value for this ID register. Trust instead section 3.2.74's list of which fields are set. This means that we stop incorrectly reporting FEAT_XS as present, and now report the presence of FEAT_BF16. Cc: qemu-stable@nongnu.org Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240917161337.3012188-1-peter.maydell@linaro.org
2024-09-19kvm: Remove unreachable code in kvm_dirty_ring_reaper_thread()Peter Maydell
The code at the tail end of the loop in kvm_dirty_ring_reaper_thread() is unreachable, because there is no way for execution to leave the loop. Replace it with a g_assert_not_reached(). (The code has always been unreachable, right from the start when the function was added in commit b4420f198dd8.) Resolves: Coverity CID 1547687 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240815131206.3231819-3-peter.maydell@linaro.org
2024-09-19kvm: Make 'mmap_size' be 'int' in kvm_init_vcpu(), do_kvm_destroy_vcpu()Peter Maydell
In kvm_init_vcpu()and do_kvm_destroy_vcpu(), the return value from kvm_ioctl(..., KVM_GET_VCPU_MMAP_SIZE, ...) is an 'int', but we put it into a 'long' logal variable mmap_size. Coverity then complains that there might be a truncation when we copy that value into the 'int ret' which we use for returning a value in an error-exit codepath. This can't ever actually overflow because the value was in an 'int' to start with, but it makes more sense to use 'int' for mmap_size so we don't do the widen-then-narrow sequence in the first place. Resolves: Coverity CID 1547515 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240815131206.3231819-2-peter.maydell@linaro.org
2024-09-19tests: drop OpenBSD tests for aarch64/sbsa-refMarcin Juszkiewicz
OpenBSD 7.3 we use is EoL. Both 7.4 and 7.5 releases do not work on anything above Neoverse-N1 due to PAC emulation: https://marc.info/?l=openbsd-arm&m=171050428327850&w=2 OpenBSD 7.6 is not yet released. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20240910-b4-move-to-freebsd-v5-4-0fb66d803c93@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19tests: expand timeout information for aarch64/sbsa-refMarcin Juszkiewicz
'Test might timeout' means nothing. Replace it with useful information that it is emulation of pointer authentication what makes this test run too long. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20240910-b4-move-to-freebsd-v5-3-0fb66d803c93@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19tests: add FreeBSD tests for aarch64/sbsa-refMarcin Juszkiewicz
FreeBSD has longer support cycle for stable release (14.x EoL in 2028) than OpenBSD (7.3 we use is already EoL). Also bugfixes are backported so we can stay on 14.x for longer. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20240910-b4-move-to-freebsd-v5-2-0fb66d803c93@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19tests: use default cpu for aarch64/sbsa-refMarcin Juszkiewicz
We want to run tests using default cpu without having to remember which Arm core is it. Change Neoverse-N1 (old default) test to use default cpu (Neoverse-N2 at the moment). Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20240910-b4-move-to-freebsd-v5-1-0fb66d803c93@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19hw/char/stm32l4x5_usart.c: Enable USART ACK bit responseJacob Abrams
SW modifying USART_CR1 TE bit should cuase HW to respond by altering USART_ISR TEACK bit, and likewise for RE and REACK bit. This resolves some but not all issues necessary for the official STM USART HAL driver to function as is. Fixes: 87b77e6e01ca ("hw/char/stm32l4x5_usart: Enable serial read and write") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2540 Signed-off-by: Jacob Abrams <satur9nine@gmail.com> Message-id: 20240911043255.51966-1-satur9nine@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Convert scalar [US]QSHRN, [US]QRSHRN, SQSHRUN to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-30-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Convert vector [US]QSHRN, [US]QRSHRN, SQSHRUN to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-29-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Convert SQSHL, UQSHL, SQSHLU (immediate) to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-28-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Widen NeonGenNarrowEnvFn return to 64 bitsRichard Henderson
While these functions really do return a 32-bit value, widening the return type means that we need do less marshalling between TCG types. Remove NeonGenNarrowEnvFn typedef; add NeonGenOne64OpEnvFn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240912024114.1097832-27-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Convert VQSHL, VQSHLU to gvecRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-26-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Convert handle_scalar_simd_shli to decodetreeRichard Henderson
This includes SHL and SLI. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Convert handle_scalar_simd_shri to decodetreeRichard Henderson
This includes SSHR, USHR, SSRA, USRA, SRSHR, URSHR, SRSRA, URSRA, SRI. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Convert SHRN, RSHRN to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Split out subroutines of handle_shri_with_rndaccRichard Henderson
There isn't a lot of commonality along the different paths of handle_shri_with_rndacc. Split them out to separate functions, which will be usable during the decodetree conversion. Simplify 64-bit rounding operations to not require double-word arithmetic. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Push tcg_rnd into handle_shri_with_rndaccRichard Henderson
We always pass the same value for round; compute it within common code. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Convert SSHLL, USHLL to decodetreeRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Use {, s}extract in handle_vec_simd_wshliRichard Henderson
Combine the right shift with the extension via the tcg extract operations. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-19target/arm: Convert handle_vec_simd_shli to decodetreeRichard Henderson
This includes SHL and SLI. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240912024114.1097832-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-22 12:51:25 +0000