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2024-06-21scripts/coverity-scan/COMPONENTS.md: Include libqmp in testlibsPeter Maydell
Add libqmp to the testlibs component. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240604145934.1230583-6-peter.maydell@linaro.org
2024-06-21scripts/coverity-scan/COMPONENTS.md: Fix monitor componentPeter Maydell
Update the 'monitor' component: * qapi/ and monitor/ are now subdirectories * add job-qmp.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240604145934.1230583-5-peter.maydell@linaro.org
2024-06-21scripts/coverity-scan/COMPONENTS.md: Add crypto headers in host/include to ↵Peter Maydell
the crypto component host/include/*/host/crypto/ are relatively new headers; add them to the crypto component. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240604145934.1230583-4-peter.maydell@linaro.org
2024-06-21scripts/coverity-scan/COMPONENTS.md: Fix 'char' componentPeter Maydell
The 'char' component: * includes the no-longer-present qemu-char.c, which has been long since split into the chardev/ backend code * also includes the hw/char devices Split it into two components: * char is the hw/char devices * chardev is the chardev backends with regexes matching our current sources. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240604145934.1230583-3-peter.maydell@linaro.org
2024-06-21scripts/coverity-scan/COMPONENTS.md: Update paths to match gitlab CIPeter Maydell
Since commit 83aa1baa069c we have been running the build for Coverity Scan as a Gitlab CI job, rather than the old setup where it was run on a local developer's machine. This is working well, but the absolute paths of files are different for the Gitlab CI job, which means that the regexes we use to identify Coverity components no longer work. With Gitlab CI builds the file paths are of the form /builds/qemu-project/qemu/accel/kvm/kvm-all.c rather than the old /qemu/accel/kvm/kvm-all.c and our regexes all don't match. Update all the regexes to start with .*/qemu/ . This will hopefully avoid the need to change them again in future if the build path changes again. This change was made with a search-and-replace of (/qemu)? to .*/qemu . Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240604145934.1230583-2-peter.maydell@linaro.org
2024-06-21hw/arm/xilinx_zynq: Fix IRQ/FIQ routingSebastian Huber
Fix the system bus interrupt line to CPU core assignment. Fixes: ddcf58e044ce0 ("hw/arm/xilinx_zynq: Support up to two CPU cores") Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240610052906.4432-1-sebastian.huber@embedded-brains.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-06-21hw/intc/arm_gic: Fix deactivation of SPI linesEdgar E. Iglesias
Julien reported that he has seen strange behaviour when running Xen on QEMU using GICv2. When Xen migrates a guest's vCPU from one pCPU to another while the vCPU is handling an interrupt, the guest is unable to properly deactivate interrupts. Looking at it a little closer, our GICv2 model treats deactivation of SPI lines as if they were PPI's, i.e banked per CPU core. The state for active interrupts should only be banked for PPI lines, not for SPI lines. Make deactivation of SPI lines unbanked, similar to how we handle writes to GICD_ICACTIVER. Reported-by: Julien Grall <julien@xen.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-id: 20240605143044.2029444-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-06-21hw/arm/sbsa-ref: switch to 1GHz timer frequencyMarcin Juszkiewicz
Updated firmware for QEMU CI is already in merge queue so we can move platform to be future proof. All supported cpus work fine with 1GHz timer frequency when firmware is fresh enough. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com> Message-id: 20240531093729.220758-2-marcin.juszkiewicz@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-06-21hw/net/can/xlnx-versal-canfd: Fix sorting of the tx queueShiva sagar Myana
Returning an uint32_t casted to a gint from g_cmp_ids causes the tx queue to become wrongly sorted when executing g_slist_sort. Fix this by always returning -1 or 1 from g_cmp_ids based on the ID comparison instead. Also, if two message IDs are the same, sort them by using their index and transmit the message at the lowest index first. Signed-off-by: Shiva sagar Myana <Shivasagar.Myana@amd.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20240603051732.3334571-1-Shivasagar.Myana@amd.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-06-19Merge tag 'pull-tcg-20240619' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson
tcg/loongarch64: Support 64- and 256-bit vectors tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointers util/bufferiszero: Split out host include files util/bufferiszero: Add loongarch64 vector acceleration accel/tcg: Fix typo causing tb->page_addr[1] to not be recorded target/sparc: use signed denominator in sdiv helper linux-user: Make TARGET_NR_setgroups affect only the current thread # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmZzRoMdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9Y7gf/ZUTGjCUdAO7W7J5e # Z3JLUNOfUHO6PxoE05963XJc+APwKiuL6Yo2bnJo6km7WM50CoaX9/7L9CXD7STg # s3eUJ2p7FfvOADZgO373nqRrB/2mhvoywhDbVJBl+NcRvRUDW8rMqrlSKIAwDIsC # kwwTWlCfpBSlUgm/c6yCVmt815+sGUPD2k/p+pIzAVUG6fGYAosC2fwPzPajiDGX # Q+obV1fryKq2SRR2dMnhmPRtr3pQBBkISLuTX6xNM2+CYhYqhBrAlQaOEGhp7Dx3 # ucKjvQFpHgPOSdQxb/HaDv81A20ZUQaydiNNmuKQcTtMx3MsQFR8NyVjH7L+fbS8 # JokjaQ== # =yVKz # -----END PGP SIGNATURE----- # gpg: Signature made Wed 19 Jun 2024 01:58:43 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-tcg-20240619' of https://gitlab.com/rth7680/qemu: (24 commits) tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointers target/sparc: use signed denominator in sdiv helper linux-user: Make TARGET_NR_setgroups affect only the current thread accel/tcg: Fix typo causing tb->page_addr[1] to not be recorded util/bufferiszero: Add loongarch64 vector acceleration util/bufferiszero: Split out host include files tcg/loongarch64: Enable v256 with LASX tcg/loongarch64: Support LASX in tcg_out_vec_op tcg/loongarch64: Split out vdvjukN in tcg_out_vec_op tcg/loongarch64: Remove temp_vec from tcg_out_vec_op tcg/loongarch64: Support LASX in tcg_out_{mov,ld,st} tcg/loongarch64: Split out vdvjvk in tcg_out_vec_op tcg/loongarch64: Support LASX in tcg_out_addsub_vec tcg/loongarch64: Simplify tcg_out_addsub_vec tcg/loongarch64: Support LASX in tcg_out_dupi_vec tcg/loongarch64: Use tcg_out_dup_vec in tcg_out_dupi_vec tcg/loongarch64: Support LASX in tcg_out_dupm_vec tcg/loongarch64: Support LASX in tcg_out_dup_vec tcg/loongarch64: Simplify tcg_out_dup_vec util/loongarch64: Detect LASX vector support ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Fix tcg_out_movi vs some pcrel pointersRichard Henderson
Simplify the logic for two-part, 32-bit pc-relative addresses. Rather than assume all such fit in int32_t, do some arithmetic and assert a result, do some arithmetic first and then check to see if the pieces are in range. Cc: qemu-stable@nongnu.org Fixes: dacc51720db ("tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi") Reviewed-by: Song Gao <gaosong@loongson.cn> Reported-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19target/sparc: use signed denominator in sdiv helperClément Chigot
The result has to be done with the signed denominator (b32) instead of the unsigned value passed in argument (b). Cc: qemu-stable@nongnu.org Fixes: 1326010322d6 ("target/sparc: Remove CC_OP_DIV") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2319 Signed-off-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240606144331.698361-1-chigot@adacore.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19linux-user: Make TARGET_NR_setgroups affect only the current threadIlya Leoshkevich
Like TARGET_NR_setuid, TARGET_NR_setgroups should affect only the calling thread, and not the entire process. Therefore, implement it using a syscall, and not a libc call. Cc: qemu-stable@nongnu.org Fixes: 19b84f3c35d7 ("added setgroups and getgroups syscalls") Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240614154710.1078766-1-iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19accel/tcg: Fix typo causing tb->page_addr[1] to not be recordedAnton Johansson
For TBs crossing page boundaries, the 2nd page will never be recorded/removed, as the index of the 2nd page is computed from the address of the 1st page. This is due to a typo, fix it. Cc: qemu-stable@nongnu.org Fixes: deba78709a ("accel/tcg: Always lock pages before translation") Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240612133031.15298-1-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19util/bufferiszero: Add loongarch64 vector accelerationRichard Henderson
Use inline assembly because no release compiler allows per-function selection of the ISA. Tested-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19util/bufferiszero: Split out host include filesRichard Henderson
Split out host/bufferiszero.h.inc for x86, aarch64 and generic in order to avoid an overlong ifdef ladder. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Enable v256 with LASXRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_vec_opRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Split out vdvjukN in tcg_out_vec_opRichard Henderson
Fixes a bug in the immediate shifts, because the exact encoding depends on the element size. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Remove temp_vec from tcg_out_vec_opRichard Henderson
Use TCG_VEC_TMP0 directly. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_{mov,ld,st}Richard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Split out vdvjvk in tcg_out_vec_opRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_addsub_vecRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Simplify tcg_out_addsub_vecRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_dupi_vecRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Use tcg_out_dup_vec in tcg_out_dupi_vecRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_dupm_vecRichard Henderson
Each element size has a different encoding, so code cannot be shared in the same way as with tcg_out_dup_vec. Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support LASX in tcg_out_dup_vecRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Simplify tcg_out_dup_vecRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19util/loongarch64: Detect LASX vector supportRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Support TCG_TYPE_V64Richard Henderson
We can implement this with fld_d, fst_d for load and store, and then use the normal v128 operations in registers. This will improve support for guests which use v64. Reviewed-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Handle i32 and i64 moves between gr and frRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Use fp load/store for I32 and I64 into vector regsRichard Henderson
Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19tcg/loongarch64: Import LASX, FP insnsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19Merge tag 'misc-20240619' of https://github.com/philmd/qemu into stagingRichard Henderson
Misc patches queue . Remove deprecated pc-i440fx-2.0 -> 2.3 machines (Phil) . Always use little endian audio format in virtio-snd (Phil) . Avoid using Monitor in INTERRUPT_STATS_PROVIDER::print_info (Phil) . Introduce x-query-interrupt-controllers QMP command (Phil) . Introduce pnv_chip_foreach_cpu() to remove one CPU_FOREACH use (Cédric) . Constify few uses of IOMMUTLBEvent (Phil) . Wire loongson_ipi device to loongson3_virt/TCG (Jiaxun) . Fix inclusion of tracing headers on s390x/TCG (Phil) . Add few shortcuts missing to readline (Manos) . Update ui/display entries in MAINTAINERS (Gerd) . Use qemu_add_mouse_change_notifier on Cocoa (Akihiko) . Fix Standard VGA screen blanking and cleanups (Gerd) . Fix USB/MTP reported "free space" value (Fabio) . Cast size_memop() returned value (Roman) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmZyuKYACgkQ4+MsLN6t # wN5guxAAvwJWbxQA8B4+gfiYaMK0AnM4leuCZ+8Sf+LhK32k2UkFA4NnKBkxGmO+ # 45NOEEEEv1Tukvtq1STHkYEdERJbHndpSFk2XmaYY09Ofo54vv2dXy6MD6GJriuA # Pr9Mivzs490RSPXmxhsa8GU5IE6CO3LamgpSeH8XxPTvCbRIiB8LcKsme6utBAZv # 9dHnEX5sXEEY2ZvArQd+eueyJfRyN4+1PpQkE9uH/wLIBqHAkHgSvFVaLo+PtA7T # xfcFvrawRTWIU+P1lojmCMb+mOj+YS7yigpkkYQC4SFm0PEv5J5nyhr/mhhiVuSS # tK8DNNi44F7/Z2CzEwbwk1PEnfKWtCgG2rEiR5uT6E8nmvxaOr2LfswBjLSwVDPS # mBOnjTMLqTBPKq8E8x2di1h2cJ9PZ90zZtWzYD8Eqoq+eqz/x+8z/qP4vifzO+NB # 7lj4IQZzLn+iktDGpjfh2RNoV9F9i9BwFGJqO2i0MzVftezJuGfe9olVOP2ErpnR # jqB7gzgc6g4tYiOK9WchuIeB/S9dU/5qqQxWwINWX0j4cHF6Qq71LyejCTfpqpf8 # jjF65XdGHcyVm9NAnr18MTzwdu3YYWf4w2OGIHg7iGLC0hv3U+EzEEMpv2E6pelM # iXgtqkRQm9qJaSrjfv0MUp9irjq01aIaHceFmP20QtkMP256E6c= # =Ed8Z # -----END PGP SIGNATURE----- # gpg: Signature made Wed 19 Jun 2024 03:53:26 AM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'misc-20240619' of https://github.com/philmd/qemu: (74 commits) exec: Make the MemOp enum cast explicit ui+display: rename is_buffer_shared() -> surface_is_allocated() ui+display: rename is_placeholder() -> surface_is_placeholder() stdvga: fix screen blanking ui/cocoa: Use qemu_add_mouse_change_notifier MAINTAINERS: drop spice+ui maintainership MAINTAINERS: drop virtio-gpu maintainership util/readline: Add C-u shortcut util/readline: Add C-n, C-p shortcuts util/readline: Fix lints for readline_handle_byte target/s390x: Use s390_skeys_get|set() helper hw/s390x: Introduce s390_skeys_get|set() helpers hw/mips/loongson3_virt: Wire up loongson_ipi device hw/intc/loongson_ipi: Replace ipi_getcpu with cpu_by_arch_id hw/intc/loongson_ipi: Provide per core MMIO address spaces hw/intc: Remove loongarch_ipi.c hw/usb/dev-mtp: Correctly report free space hw/usb: Remove unused 'host.h' header hw/i386/iommu: Constify IOMMUTLBEvent in vtd_page_walk_hook prototype memory: Constify IOMMUTLBEvent in memory_region_notify_iommu() ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-19exec: Make the MemOp enum cast explicitRoman Kiryanov
Make the MemOp enum cast explicit to use the QEMU headers with a C++ compiler. Signed-off-by: Roman Kiryanov <rkir@google.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240618224528.878425-1-rkir@google.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-06-19ui+display: rename is_buffer_shared() -> surface_is_allocated()Gerd Hoffmann
Boolean return value is reversed, to align with QEMU_ALLOCATED_FLAG, so all callers must be adapted. Also rename share_surface variable in vga_draw_graphic() to reduce confusion. No functional change. Suggested-by: Marc-André Lureau <marcandre.lureau@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Paul Durrant <paul@xen.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <20240605131444.797896-4-kraxel@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-06-19ui+display: rename is_placeholder() -> surface_is_placeholder()Gerd Hoffmann
No functional change. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240605131444.797896-3-kraxel@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-06-19stdvga: fix screen blankingGerd Hoffmann
In case the display surface uses a shared buffer (i.e. uses vga vram directly instead of a shadow) go unshare the buffer before clearing it. This avoids vga memory corruption, which in turn fixes unblanking not working properly with X11. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2067 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <20240605131444.797896-2-kraxel@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-06-19ui/cocoa: Use qemu_add_mouse_change_notifierAkihiko Odaki
This eliminates the polling in cocoa_refresh and implements the propagation of the mouse mode change from absolute to relative. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Phil Dennis-Jordan <phil@philjordan.eu> Tested-by: Phil Dennis-Jordan <phil@philjordan.eu> Message-ID: <20240322-mouse-v1-1-0b7d4d9bdfbf@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-06-19MAINTAINERS: drop spice+ui maintainershipGerd Hoffmann
Remove myself from spice and ui entries. Flip status to "Orphan" for entries which have nobody else listed. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-ID: <20240528083858.836262-5-kraxel@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-06-19MAINTAINERS: drop virtio-gpu maintainershipGerd Hoffmann
Remove myself from virtio-gpu entries. Flip status to "Orphan" for entries which have nobody else listed. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Message-ID: <20240528083858.836262-4-kraxel@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-06-19util/readline: Add C-u shortcutManos Pitsidianakis
Add support for the unix-line-discard readline action, which erases from the cursor position up to the beginning of the line. The default binding, C-u, was chosen. This is useful to quickly erase command input while working on the monitor interface. Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <6772067e1c0d4b1c5310e5446e9e3e1c6b3b5bc0.1718265822.git.manos.pitsidianakis@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-06-19util/readline: Add C-n, C-p shortcutsManos Pitsidianakis
C-n and C-p are the default bindings for readline's next-history and previous-history respectively. They have the same functionality as the Down and Up arrow keys. Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <9876594132d1f2e7210ab3f7ca01a82f95206447.1718265822.git.manos.pitsidianakis@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-06-19util/readline: Fix lints for readline_handle_byteManos Pitsidianakis
While they do not give warnings under our current buildsystem configuration, my clang's language server daemon was complaining about missing default: labels in switch statements. While at it, add /* fallthrough */ annotations where appropriate. This is a purely style and not functional change. Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-ID: <16f745ac7f5fef74498709ffd98857e76edff6aa.1718265822.git.manos.pitsidianakis@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-06-19target/s390x: Use s390_skeys_get|set() helperPhilippe Mathieu-Daudé
Commit c9274b6bf0 ("target/s390x: start moving TCG-only code to tcg/") moved mem_helper.c, but the trace-events file is still in the parent directory, so is the generated trace.h. Call the s390_skeys_get|set() helper, removing the need for the trace event shared with the tcg/ sub-directory, fixing the following build failure: In file included from ../target/s390x/tcg/mem_helper.c:33: ../target/s390x/tcg/trace.h:1:10: fatal error: 'trace/trace-target_s390x_tcg.h' file not found #include "trace/trace-target_s390x_tcg.h" Reported-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20240613104415.9643-3-philmd@linaro.org>
2024-06-19hw/s390x: Introduce s390_skeys_get|set() helpersPhilippe Mathieu-Daudé
s390_skeys_set() dispatch to S390SKeysClass::set_skeys(), and s390_skeys_get() to S390SKeysClass::get_skeys(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20240613104415.9643-2-philmd@linaro.org>
2024-06-19hw/mips/loongson3_virt: Wire up loongson_ipi deviceJiaxun Yang
Wire up loongson_ipi device for loongson3_virt machine, so we can have SMP support for TCG backend as well. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Acked-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240605-loongson3-ipi-v3-3-ddd2c0e03fa3@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-06-19hw/intc/loongson_ipi: Replace ipi_getcpu with cpu_by_arch_idJiaxun Yang
cpu_by_arch_id is doing the same thing as our ipi_getcpu logic. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-ID: <20240605-loongson3-ipi-v3-4-ddd2c0e03fa3@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-06-19hw/intc/loongson_ipi: Provide per core MMIO address spacesJiaxun Yang
The real IPI hardware have dedicated MMIO registers mapped into memory address space for every core. This is not used by LoongArch guest software but it is essential for CPU without IOCSR such as Loongson-3A1000. Implement it with existing infrastructure. Acked-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-ID: <20240605-loongson3-ipi-v3-2-ddd2c0e03fa3@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-21 21:43:56 +0000