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2023-01-06hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"Bin Meng
2023-01-06hw/riscv: sifive_e: Fix the number of interrupt sources of PLICBin Meng
2023-01-06hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLICBin Meng
2023-01-06hw/intc: sifive_plic: Update "num-sources" property default valueBin Meng
2023-01-06hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in ...Bin Meng
2023-01-06hw/intc: sifive_plic: Improve robustness of the PLIC config parserBin Meng
2023-01-06hw/intc: sifive_plic: Drop PLICMode_HBin Meng
2023-01-06hw/riscv: spike: Remove misleading commentsBin Meng
2023-01-06hw/riscv: Sort machines Kconfig options in alphabetical orderBin Meng
2023-01-06hw/riscv: Fix opentitan dependency to SIFIVE_PLICBin Meng
2023-01-06hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllersBin Meng
2023-01-06hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLICBin Meng
2023-01-06RISC-V: Add Zawrs ISA extension supportChristoph Muellner
2023-01-06target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+Bin Meng
2023-01-06target/riscv: Simplify helper_sret() a little bitBin Meng
2023-01-06target/riscv: Set pc_succ_insn for !rvc illegal insnRichard Henderson
2023-01-06target/riscv: Fix mret exception cause when no pmp rule is configuredBin Meng
2023-01-06hw/intc: sifive_plic: fix out-of-bound access of source_priority arrayJim Shu
2023-01-06hw/{misc, riscv}: pfsoc: add system controller as unimplementedConor Dooley
2023-01-06hw/riscv: pfsoc: add missing FICs as unimplementedConor Dooley
2023-01-06hw/misc: pfsoc: add fabric clocks to ioscbConor Dooley
2023-01-06target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()Bin Meng
2023-01-06target/riscv: support cache-related PMU events in virtual modeJim Shu
2023-01-06hw/riscv: virt: Remove the redundant ipi-id propertyAtish Patra
2023-01-06target/riscv: Typo fix in sstc() predicateAnup Patel
2023-01-06hw/intc: sifive_plic: Renumber the S irqs for numa supportFrédéric Pétrot
2023-01-06target/riscv: Add itrigger_enabled field to CPURISCVStateLIU Zhiwei
2023-01-06target/riscv: Enable native debug itriggerLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is enabledLIU Zhiwei
2023-01-06target/riscv: Add itrigger support when icount is not enabledLIU Zhiwei
2023-01-06target/riscv: generate virtual instruction exceptionMayuresh Chitale
2023-01-06target/riscv: smstateen check for h/s/envcfgMayuresh Chitale
2023-01-06target/riscv: Add smstateen supportMayuresh Chitale
2023-01-06hw/riscv/opentitan: add aon_timer base unimplWilfred Mallawa
2023-01-06hw/riscv/opentitan: bump opentitanWilfred Mallawa
2023-01-06tcg/riscv: Fix base register for user-only qemu_ld/stRichard Henderson
2023-01-06tcg/riscv: Fix reg overlap case in tcg_out_addsub2Richard Henderson
2023-01-06tcg/riscv: Fix range matched by TCG_CT_CONST_M12Richard Henderson
2023-01-06target/riscv: Fix PMP propagation for tlbLIU Zhiwei
2023-01-05Merge tag 'python-pull-request' of https://gitlab.com/jsnow/qemu into stagingPeter Maydell
2023-01-05Merge tag 'mem-2023-01-02' of https://github.com/davidhildenbrand/qemu into s...Peter Maydell
2023-01-04.gitlab-ci.d/windows: Work-around timeout and OpenGL problems of the MSYS2 jobsThomas Huth
2023-01-04python: add 3.11 to supported listJohn Snow
2023-01-04iotests/check: Fix typing for sys.exit() valueJohn Snow
2023-01-04Python: fix flake8 configJohn Snow
2023-01-04python/machine: Handle termination cases without QMPJohn Snow
2023-01-04python/machine: Add debug logging to key state changesJohn Snow
2023-01-04Merge tag 'pull-testing-next-231222-1' of https://gitlab.com/stsquad/qemu int...Peter Maydell
2023-01-04Merge tag 'pull-9p-20221223' of https://github.com/cschoenebeck/qemu into sta...Peter Maydell
2022-12-28hostmem: Honor multiple preferred nodes if possibleMichal Privoznik