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AgeCommit message (Expand)Author
2021-12-20target/riscv: rvv-1.0: floating-point compare instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer comparison instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width saturating add and subtract instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: widening integer multiply-add instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: narrowing integer right shift instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrowFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width bit shift instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: single-width averaging add and subtract instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: integer extension instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: whole register move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point scalar move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point move instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: integer scalar move instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: register gather instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: allow load element with sign-extendedFrank Chang
2021-12-20target/riscv: rvv-1.0: element index instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: iota instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: set-X-first mask bit instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: find-first-set mask bit instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: count population in mask instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point classify instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: floating-point square-root instructionFrank Chang
2021-12-20target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculationFrank Chang
2021-12-20target/riscv: rvv-1.0: update vext_max_elems() for load/store insnsFrank Chang
2021-12-20target/riscv: rvv-1.0: load/store whole register instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: fault-only-first unit stride loadFrank Chang
2021-12-20target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store i...Frank Chang
2021-12-20target/riscv: rvv-1.0: index load and store instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: stride load and store instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: configure instructionsFrank Chang
2021-12-20target/riscv: rvv-1.0: remove amo operations instructionsFrank Chang
2021-12-20target/riscv: rvv:1.0: add translation-time nan-box helper functionFrank Chang
2021-12-20target/riscv: introduce more imm value modes in translator functionsFrank Chang
2021-12-20target/riscv: rvv-1.0: update check functionsFrank Chang
2021-12-20target/riscv: rvv-1.0: add VMA and VTAFrank Chang
2021-12-20target/riscv: rvv-1.0: add fractional LMULFrank Chang
2021-12-20target/riscv: rvv-1.0: remove MLEN calculationsFrank Chang
2021-12-20target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registersFrank Chang
2021-12-20target/riscv: rvv-1.0: add vlenb registerGreentime Hu
2021-12-20target/riscv: rvv-1.0: add vcsr registerLIU Zhiwei
2021-12-20target/riscv: rvv-1.0: remove rvv related codes from fcsr registersFrank Chang
2021-12-20target/riscv: rvv-1.0: add translation-time vector context statusFrank Chang
2021-12-20target/riscv: rvv-1.0: introduce writable misa.v fieldFrank Chang
2021-12-20target/riscv: rvv-1.0: add sstatus VS fieldLIU Zhiwei
2021-12-20target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirtyFrank Chang
2021-12-20target/riscv: rvv-1.0: add mstatus VS fieldLIU Zhiwei
2021-12-20target/riscv: Use FIELD_EX32() to extract wd fieldFrank Chang
2021-12-20target/riscv: drop vector 0.7.1 and add 1.0 supportFrank Chang
2021-12-20target/riscv: zfh: add Zfhmin cpu propertyFrank Chang
2021-12-20target/riscv: zfh: implement zfhmin extensionFrank Chang
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