aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2022-06-22migration: rename 'pos' field in QEMUFile to 'bytes_processed'Daniel P. Berrangé
The field name 'pos' gives the misleading impression that the QEMUFile objects are seekable. This is not the case, as in general we just have an opaque stream. The users of this method are only interested in the total bytes processed. This switches to a new name that reflects the intended usage. Every QIOChannel backed impl of QEMUFile is currently ignoring the 'pos' field. The only QEMUFile impl using 'pos' as an offset for I/O is the block device vmstate. A later patch is introducing a QIOChannel impl for the vmstate, and to handle this it is tracking a file offset itself internally to the QIOChannel impl. So when we later eliminate the QEMUFileOps callbacks later, the 'pos' field will no longer be used from any I/O read/write methods. Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> dgilbert: Fixed long line
2022-06-22migration: rename rate limiting fields in QEMUFileDaniel P. Berrangé
This renames the following QEMUFile fields * bytes_xfer -> rate_limit_used * xfer_limit -> rate_limit_max The intent is to make it clear that 'bytes_xfer' is specifically related to rate limiting of data and applies to data queued, which need not have been transferred on the wire yet if a flush hasn't taken place. Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2022-06-22migration: remove unreachble RDMA code in save_hook implDaniel P. Berrangé
The QEMUFile 'save_hook' callback has a 'size_t size' parameter. The RDMA impl of this has logic that takes different actions depending on whether the value is zero or non-zero. It has commented out logic that would have taken further actions if the value was negative. The only place where the 'save_hook' callback is invoked is the ram_control_save_page() method, which passes 'size' through from its caller. The only caller of this method is in turn control_save_page(). This method unconditionally passes the 'TARGET_PAGE_SIZE' constant for the 'size' parameter. IOW, the only scenario for 'size' that can execute in the qemu_rdma_save_page method is 'size > 0'. The remaining code has been unreachable since RDMA support was first introduced 9 years ago. Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2022-06-22migration: switch to use QIOChannelNull for dummy channelDaniel P. Berrangé
This removes one further custom impl of QEMUFile, in favour of a QIOChannel based impl. Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2022-06-22io: add a QIOChannelNull equivalent to /dev/nullDaniel P. Berrangé
This is for code which needs a portable equivalent to a QIOChannelFile connected to /dev/null. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2022-06-22migration: Change zero_copy_send from migration parameter to migration ↵Leonardo Bras
capability When originally implemented, zero_copy_send was designed as a Migration paramenter. But taking into account how is that supposed to work, and how the difference between a capability and a parameter, it only makes sense that zero-copy-send would work better as a capability. Taking into account how recently the change got merged, it was decided that it's still time to make it right, and convert zero_copy_send into a Migration capability. Signed-off-by: Leonardo Bras <leobras@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Acked-by: Markus Armbruster <armbru@redhat.com> Acked-by: Peter Xu <peterx@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> dgilbert: always define the capability, even on non-Linux but error if set; avoids build problems with the capability
2022-06-22QIOChannelSocket: Fix zero-copy send so socket flush worksLeonardo Bras
Somewhere between v6 and v7 the of the zero-copy-send patchset a crucial part of the flushing mechanism got missing: incrementing zero_copy_queued. Without that, the flushing interface becomes a no-op, and there is no guarantee the buffer is really sent. This can go as bad as causing a corruption in RAM during migration. Fixes: 2bc58ffc2926 ("QIOChannelSocket: Implement io_writev zero copy flag & io_flush for CONFIG_LINUX") Reported-by: 徐闯 <xuchuangxclwt@bytedance.com> Signed-off-by: Leonardo Bras <leobras@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2022-06-22QIOChannelSocket: Introduce assert and reduce ifdefs to improve readabilityLeonardo Bras
During implementation of MSG_ZEROCOPY feature, a lot of #ifdefs were introduced, particularly at qio_channel_socket_writev(). Rewrite some of those changes so it's easier to read. Also, introduce an assert to help detect incorrect zero-copy usage is when it's disabled on build. Signed-off-by: Leonardo Bras <leobras@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> dgilbert: Fixed up thinko'd g_assert_unreachable->g_assert_not_reached
2022-06-22migration: Remove RDMA_UNREGISTRATION_EXAMPLEJuan Quintela
Nobody has ever showed up to unregister individual pages, and another set of patches written by Daniel P. Berrangé <berrange@redhat.com> just remove qemu_rdma_signal_unregister() function needed here. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2022-06-22Merge tag 'pull-aspeed-20220622' of https://github.com/legoater/qemu into ↵Richard Henderson
staging aspeed queue: * Extra avocado tests using buildroot images * Conversion of the I2C model to the registerfield interface * Support for the I2C new register interface on AST2600 * Various I2C enhancements * I2C support for the AST1030 * Improvement of the Aspeed SMC and m25p80 qtest # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmKyzCYACgkQUaNDx8/7 # 7KG+Aw/+MM3BlQfzDhjETkznqFbvp+aDcnKYwd/brizUC1y3paPFGc0xzD05x3QC # 2th44oYS934UwQ78EMkC0uNed/kHh+6aHaBrq/XylIg7Dbq5QeCBXwRGCNW6tgtc # K3ZSM20QM+XRCjmo9ys792NYPC+8tYpw7idb2AOeum7ic/ZaeT3h1FX1Mr57I3XE # PYwDEBEd4hJ3DroYzIP9YQvRBNu8/d5VoiNr3GLfNy3zrkhuJ4D4jUAEbHATG7Gb # k0A6o6bVAL85AUSq/ksceHqzWAnizh1q1o/k9UP83HIt1S3ghgK6RsAu4+9HKlP4 # lZ6MFfx3Nzf8u2y/FlOiuABEBUNsngjNmLo6B/qe/cZk60/nS56qOWSvuzPxqVDO # lI++SLY6R1D8q36H4eF/vq/AyLnXBxGqeq0DipPcnZVKdVVHUHppNly5efJ/7cWn # VybobblU48BCgjc/EoMVEy8L/t/uRjY3wmoKkfKLCObRrlcPxSrLPUP8+j8nR0JG # zDOh+CrxHTUbJGV6qRmZx9m2HQtbtH5k89UxskkUkscvVDqWhxqdFVnTWfXcmyP8 # LqTkEv7IV4ECM1zN5OVK9No46WCi5j24bxO3z7or4e04vgwjM41unV7HAFl8Z0/s # tyFQUG4dFAKHH7quU0F3qSxnORNyCy5ssEpmobujeifbiFMpNss= # =OsUe # -----END PGP SIGNATURE----- # gpg: Signature made Wed 22 Jun 2022 01:00:38 AM PDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20220622' of https://github.com/legoater/qemu: hw: m25p80: fixing individual test failure when tests are running in isolation aspeed/hace: Add missing newlines to unimp messages aspeed/i2c: Enable SLAVE_ADDR_RX_MATCH always hw/i2c/aspeed: add DEV_ADDR in old register mode hw/i2c/aspeed: rework raise interrupt trace event aspeed: Add I2C buses to AST1030 model aspeed/i2c: Add ast1030 controller models aspeed: i2c: Move regs and helpers to header file aspeed: i2c: Add PKT_DONE IRQ to trace aspeed: i2c: Add new mode support aspeed: i2c: Use reg array instead of individual vars aspeed: i2c: Migrate to registerfields API hw/registerfields: Add shared fields macros test/avocado/machine_aspeed.py: Add an I2C RTC test test/avocado/machine_aspeed.py: Add I2C tests to ast2600-evb test/avocado/machine_aspeed.py: Add I2C tests to ast2500-evb test/avocado/machine_aspeed.py: Add tests using buildroot images test/avocado/machine_aspeed.py: Move OpenBMC tests aspeed: Remove fake RTC device on ast2500-evb Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-22hw: m25p80: fixing individual test failure when tests are running in isolationIris Chen
Signed-off-by: Iris Chen <irischenlj@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed/hace: Add missing newlines to unimp messagesJoel Stanley
Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed/i2c: Enable SLAVE_ADDR_RX_MATCH alwaysCédric Le Goater
There is no 'slave match interrupt' enable bit in the Interrupt Control Register. Consider it is always enabled and extend the mask value 'bus->regs[intr_ctrl_reg]' with the SLAVE_ADDR_RX_MATCH bit when the interrupt is raised. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22hw/i2c/aspeed: add DEV_ADDR in old register modeKlaus Jensen
Add support for writing and reading the device address register in old register mode. On the AST2400 (only 1 slave address) * no upper bits On the AST2500 (2 possible slave addresses), * bit[31] : Slave Address match indicator * bit[30] : Slave Address Receiving pending On the AST2600 (3 possible slave addresses), * bit[31-30] : Slave Address match indicator * bit[29] : Slave Address Receiving pending The model could be more precise to take into account all fields but since the Linux driver is masking the register value being set, it should be fine. See commit 3fb2e2aeafb2 ("i2c: aspeed: disable additional device addresses on ast2[56]xx") from Zeiv. This can be addressed later. Signed-off-by: Klaus Jensen <k.jensen@samsung.com> [ clg: add details to commit log ] Message-Id: <20220601210831.67259-3-its@irrelevant.dk> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22hw/i2c/aspeed: rework raise interrupt trace eventKlaus Jensen
Build a single string instead of having several parameters on the trace event. Suggested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com> [ clg: simplified trace buffer creation ] Message-Id: <20220601210831.67259-2-its@irrelevant.dk> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed: Add I2C buses to AST1030 modelTroy Lee
Instantiate the I2C buses in AST1030 model and create two slave device for ast1030-evb. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> [ clg : - adapted to current AST1030 upstream models - changed AST2600 to AST1030 in comment - fixed typo in commit log ] Message-Id: <20220324100439.478317-3-troy_lee@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed/i2c: Add ast1030 controller modelsCédric Le Goater
Based on : https://lore.kernel.org/qemu-devel/20220324100439.478317-2-troy_lee@aspeedtech.com/ Cc: Troy Lee <troy_lee@aspeedtech.com> Cc: Jamin Lin <jamin_lin@aspeedtech.com> Cc: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed: i2c: Move regs and helpers to header fileJoe Komlodi
Moves register definitions and short commonly used inlined functiosn to the header file to help tidy up the implementation file. Signed-off-by: Joe Komlodi <komlodi@google.com> Change-Id: I34dff7485b6bbe3c9482715ccd94dbd65dc5f324 Message-Id: <20220331043248.2237838-8-komlodi@google.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed: i2c: Add PKT_DONE IRQ to traceJoe Komlodi
Signed-off-by: Joe Komlodi <komlodi@google.com> Change-Id: I566eb09f4b9016e24570572f367627f6594039f5 Message-Id: <20220331043248.2237838-7-komlodi@google.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed: i2c: Add new mode supportJoe Komlodi
On AST2600, I2C has a secondary mode, called "new mode", which changes the layout of registers, adds some minor behavior changes, and introduces a new way to transfer data called "packet mode". Most of the bit positions of the fields are the same between old and new mode, so we use SHARED_FIELD_XX macros to reuse most of the code between the different modes. For packet mode, most of the command behavior is the same compared to other modes, but there are some minor changes to how interrupts are handled compared to other modes. Signed-off-by: Joe Komlodi <komlodi@google.com> Change-Id: I072f8301964f623afc74af1fe50c12e5caef199e Message-Id: <20220331043248.2237838-6-komlodi@google.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed: i2c: Use reg array instead of individual varsJoe Komlodi
Using a register array will allow us to represent old-mode and new-mode I2C registers by using the same underlying register array, instead of adding an entire new set of variables to represent new mode. As part of this, we also do additional cleanup to use ARRAY_FIELD_ macros instead of FIELD_ macros on registers. Signed-off-by: Joe Komlodi <komlodi@google.com> Change-Id: Ib94996b17c361b8490c042b43c99d8abc69332e3 [ clg: use of memset in aspeed_i2c_bus_reset() ] Message-Id: <20220331043248.2237838-5-komlodi@google.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed: i2c: Migrate to registerfields APIJoe Komlodi
This cleans up some of the field accessing, setting, and clearing bitwise operations, and wraps them in macros instead. Signed-off-by: Joe Komlodi <komlodi@google.com> Change-Id: I33018d6325fa04376e7c29dc4a49ab389a8e333a Message-Id: <20220331043248.2237838-4-komlodi@google.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22hw/registerfields: Add shared fields macrosJoe Komlodi
Occasionally a peripheral will have different operating modes, where the MMIO layout changes, but some of the register fields have the same offsets and behaviors. To help support this, we add SHARED_FIELD_XX macros that create SHIFT, LENGTH, and MASK macros for the fields that are shared across registers, and accessors for these fields. An example use may look as follows: There is a peripheral with registers REG_MODE1 and REG_MODE2 at different addreses, and both have a field FIELD1 initialized by SHARED_FIELD(). Depending on what mode the peripheral is operating in, the user could extract FIELD1 via SHARED_ARRAY_FIELD_EX32(s->regs, R_REG_MODE1, FIELD1) or SHARED_ARRAY_FIELD_EX32(s->regs, R_REG_MODE2, FIELD1) Signed-off-by: Joe Komlodi <komlodi@google.com> Change-Id: Id3dc53e7d2f8741c95697cbae69a81bb699fa3cb Message-Id: <20220331043248.2237838-2-komlodi@google.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22test/avocado/machine_aspeed.py: Add an I2C RTC testCédric Le Goater
Add an RTC device and check that the output of the hwclock command matches the current year. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22test/avocado/machine_aspeed.py: Add I2C tests to ast2600-evbCédric Le Goater
Create a named I2C temperature sensor device on the command line, instantiate device from Linux since it is not part of the device tree, and check the temperature is correctly reported under sysfs. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22test/avocado/machine_aspeed.py: Add I2C tests to ast2500-evbCédric Le Goater
Create a named I2C temperature sensor device on the command line, instantiate device from Linux since it is not part of the device tree, and check the temperature is correctly reported under sysfs. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22test/avocado/machine_aspeed.py: Add tests using buildroot imagesCédric Le Goater
Buildroot images are smaller than the OpenBMC images and faster to run. Built from source using : http://patchwork.ozlabs.org/project/buildroot/list/?series=303465 Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22test/avocado/machine_aspeed.py: Move OpenBMC testsCédric Le Goater
It's easier to run. Keep test_arm_ast2600_debian() under the boot_linux_console.py file because it requires the extract_from_deb() helper. We could remove it when we have tests for the AST2600. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-22aspeed: Remove fake RTC device on ast2500-evbCédric Le Goater
The board has no such device. It might have been useful for some tests in the past, it's not anymore and the same can be achieved on the command line. Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-21Merge tag 'pull-tcg-20220621' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson
Speed empty timer list in qemu_clock_deadline_ns_all. Implement remainder for Power3.1 hosts. Optimize ppc host icache flushing. Cleanups to tcg_accel_ops_init. Fix mmio crash accessing unmapped physical memory. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmKyLesdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8O1wf5AW6JeeUTs2r3owsK # UpVaRqjlLpNeuktoOQoG8lbVzm1ulEv7zgXYJTZg4cc/83WQZ2G8WzTj3W+Qr/S9 # ECRd73Kou+fK3jTo8I+wPLQjLjkIV4xSABMGz/onxhoAeyS+xcAI4qGuSGrtIg2r # sQ61V4fWCwvQJdHMyG756Xsh8Xjf18mrNQZ5PLGkyn/e9UIAc4KH6FsgWJdinGEs # V/oibY20kCXpLxN0ajNmx3x4/NFs/ymMtn1z9fdhVGjAVPY0N6YsxjsGqd/WP/5U # ui/x0wAhl/VNK2M2+z3hVGfNlMpkzTVG2A3ndD+tYI3nofwTYb/UiakhID7ZX1cQ # yKDyAw== # =3Rhw # -----END PGP SIGNATURE----- # gpg: Signature made Tue 21 Jun 2022 01:45:31 PM PDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-tcg-20220621' of https://gitlab.com/rth7680/qemu: util/cacheflush: Optimize flushing when ppc host has coherent icache util/cacheflush: Merge aarch64 ctr_el0 usage util: Merge cacheflush.c and cacheinfo.c softmmu: Always initialize xlat in address_space_translate_for_iotlb qemu-timer: Skip empty timer lists before locking in qemu_clock_deadline_ns_all accel/tcg: Reorganize tcg_accel_ops_init() accel/tcg: Init TCG cflags in vCPU thread handler target/avr: Drop avr_cpu_memory_rw_debug() tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-21util/cacheflush: Optimize flushing when ppc host has coherent icacheNicholas Piggin
On linux, the AT_HWCAP bit PPC_FEATURE_ICACHE_SNOOP indicates that we can use a simplified 3 instruction flush sequence. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20220519141131.29839-1-npiggin@gmail.com> [rth: update after merging cacheflush.c and cacheinfo.c] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220621014837.189139-4-richard.henderson@linaro.org>
2022-06-21util/cacheflush: Merge aarch64 ctr_el0 usageRichard Henderson
Merge init_ctr_el0 into arch_cache_info. In flush_idcache_range, use the pre-computed line sizes from the global variables. Use CONFIG_DARWIN in preference to __APPLE__. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220621014837.189139-3-richard.henderson@linaro.org>
2022-06-21util: Merge cacheflush.c and cacheinfo.cRichard Henderson
Combine the two files into cacheflush.c. There's a couple of bits that would be helpful to share between the two, and combining them seems better than exporting the bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220621014837.189139-2-richard.henderson@linaro.org>
2022-06-21softmmu: Always initialize xlat in address_space_translate_for_iotlbRichard Henderson
The bug is an uninitialized memory read, along the translate_fail path, which results in garbage being read from iotlb_to_section, which can lead to a crash in io_readx/io_writex. The bug may be fixed by writing any value with zero in ~TARGET_PAGE_MASK, so that the call to iotlb_to_section using the xlat'ed address returns io_mem_unassigned, as desired by the translate_fail path. It is most useful to record the original physical page address, which will eventually be logged by memory_region_access_valid when the access is rejected by unassigned_mem_accepts. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1065 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220621153829.366423-1-richard.henderson@linaro.org>
2022-06-21qemu-timer: Skip empty timer lists before locking in qemu_clock_deadline_ns_allIdan Horowitz
This decreases qemu_clock_deadline_ns_all's share from 23.2% to 13% in a profile of icount-enabled aarch64-softmmu. Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220114004358.299534-2-idan.horowitz@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-21Merge tag 'pull-ppc-20220621' of https://gitlab.com/danielhb/qemu into stagingRichard Henderson
ppc patch queue for 2022-06-21: - tcg and target/ppc: vector divide instructions and a vbpermd fix for BE hosts - ppc440_uc.c: fix boot of sam460ex machine - target/ppc: fix stop state on cpu reset - xive2: Access direct mapped thread contexts from all chips - a couple of Coverity fixes # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCYrGSLAAKCRA82cqW3gMx # ZEL/AQDhEUUaztu+AWwnPKFZOP9VBU6vO2UIxZF1GHDRnoNlLQD+O6uADnIuxpxl # klUMX8h2RFIkC0zv6xGN285SzhzpyAw= # =/2K2 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 21 Jun 2022 02:41:00 AM PDT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20220621' of https://gitlab.com/danielhb/qemu: target/ppc: cpu_init: Clean up stop state on cpu reset target/ppc: fix unreachable code in fpu_helper.c target/ppc: avoid int32 multiply overflow in int_helper.c ppc/pnv: fix extra indent spaces with DEFINE_PROP* pnv/xive2: Access direct mapped thread contexts from all chips target/ppc: fix vbpermd in big endian hosts ppc: fix boot with sam460ex target/ppc: Implemented vector module quadword target/ppc: Implemented vector module word/doubleword target/ppc: Implemented remaining vector divide extended host-utils: Implemented signed 256-by-128 division host-utils: Implemented unsigned 256-by-128 division target/ppc: Implemented vector divide extended word target/ppc: Implemented vector divide quadword target/ppc: Implemented vector divide instructions Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-20accel/tcg: Reorganize tcg_accel_ops_init()Philippe Mathieu-Daudé
Reorg TCG AccelOpsClass initialization to emphasis icount mode share more code with single-threaded TCG. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323171751.78612-7-philippe.mathieu.daude@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-20accel/tcg: Init TCG cflags in vCPU thread handlerPhilippe Mathieu-Daudé
Move TCG cflags initialization to thread handler. Remove the duplicated assert checks. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220323171751.78612-6-philippe.mathieu.daude@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-20target/avr: Drop avr_cpu_memory_rw_debug()Bin Meng
CPUClass::memory_rw_debug() holds a callback for GDB memory access. If not provided, cpu_memory_rw_debug() is used by the GDB stub. Drop avr_cpu_memory_rw_debug() which does nothing special. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220322095004.70682-1-bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-20tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd]Matheus Kowalczuk Ferst
Power ISA v3.0 introduced mod[su][wd] insns that can be used to implement rem[u]_i{32,64}. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-20target/ppc: cpu_init: Clean up stop state on cpu resetFrederic Barrat
The 'resume_as_sreset' attribute of a cpu is set when a thread is entering a stop state on ppc books. It causes the thread to be re-routed to vector 0x100 when woken up by an exception. So it must be cleared on reset or a thread might be re-routed unexpectedly after a reset, when it was not in a stop state and/or when the appropriate exception handler isn't set up yet. Using skiboot, it can be tested by resetting the system when it is quiet and most threads are idle and in stop state. After the reset occurs, skiboot elects a primary thread and all the others wait in secondary_wait. The primary thread does all the system initialization from main_cpu_entry() and at some point, the decrementer interrupt starts ticking. The exception vector for the decrementer interrupt is in place, so that shouldn't be a problem. However, if that primary thread was in stop state prior to the reset, and because the resume_as_sreset parameters is still set, it is re-routed to exception vector 0x100. Which, at that time, is still defined as the entry point for BML. So that primary thread restarts as new and ends up being treated like any other secondary thread. All threads are now waiting in secondary_wait. It results in a full system hang with no message on the console, as the uart hasn't been init'ed yet. It's actually not obvious to realise what's happening if not tracing reset (-d cpu_reset). The fix is simply to clear the 'resume_as_sreset' attribute on reset. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220617095222.612212-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-20target/ppc: fix unreachable code in fpu_helper.cDaniel Henrique Barboza
Commit c29018cc7395 added an env->fpscr OR operation using a ternary that checks if 'error' is not zero: env->fpscr |= error ? FP_FEX : 0; However, in the current body of do_fpscr_check_status(), 'error' is granted to be always non-zero at that point. The result is that Coverity is less than pleased: Control flow issues (DEADCODE) Execution cannot reach the expression "0ULL" inside this statement: "env->fpscr |= (error ? 1073...". Remove the ternary and always make env->fpscr |= FP_FEX. Cc: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Cc: Richard Henderson <richard.henderson@linaro.org> Fixes: Coverity CID 1489442 Fixes: c29018cc7395 ("target/ppc: Implemented xvf*ger*") Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Message-Id: <20220602191048.137511-1-danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-20target/ppc: avoid int32 multiply overflow in int_helper.cDaniel Henrique Barboza
Coverity is not thrilled about the multiply operations being done in ger_rank8() and ger_rank2(), giving an error like the following: Integer handling issues (OVERFLOW_BEFORE_WIDEN) Potentially overflowing expression "sextract32(a, 4 * i, 4) * sextract32(b, 4 * i, 4)" with type "int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "int64_t" (64 bits, signed). Fix both instances where this occur by adding an int64_t cast in the first operand, forcing the result to be 64 bit. Fixes: Coverity CID 1489444, 1489443 Fixes: 345531533f26 ("target/ppc: Implemented xvi*ger* instructions") Cc: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Cc: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Message-Id: <20220602141449.118173-1-danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-20ppc/pnv: fix extra indent spaces with DEFINE_PROP*Daniel Henrique Barboza
The DEFINE_PROP* macros in pnv files are using extra spaces for no good reason. Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220602215351.149910-1-danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-20pnv/xive2: Access direct mapped thread contexts from all chipsFrederic Barrat
When accessing a thread context through the IC BAR, the offset of the page in the BAR identifies the CPU. From that offset, we can compute the PIR (processor ID register) of the CPU to do the data structure lookup. On P10, the current code assumes an access for node 0 when computing the PIR. Everything is almost in place to allow access for other nodes though. So this patch reworks how the PIR value is computed so that we can access all thread contexts through the IC BAR. The PIR is already correct on P9, so no need to modify anything there. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220602165310.558810-1-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-20target/ppc: fix vbpermd in big endian hostsMatheus Ferst
The extract64 arguments are not endian dependent as they are only used for bitwise operations. The current behavior in little-endian hosts is correct; since the indexes in VRB are in PowerISA-ordering, we should always invert the value before calling extract64. Also, using the VsrD macro, we can have a single EXTRACT_BIT definition for big and little-endian with the correct behavior. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220601125355.1266165-1-matheus.ferst@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-20ppc: fix boot with sam460exMichael S. Tsirkin
Recent changes to pcie_host corrected size of its internal region to match what it expects: only the low 28 bits are ever decoded. Previous code just ignored bit 29 (if size was 1 << 29) in the address which does not make much sense. We are now asserting on size > 1 << 28 instead, but PPC 4xx actually allows guest to configure different sizes, and some firmwares seem to set it to 1 << 29. This caused e.g. qemu-system-ppc -M sam460ex to exit with an assert when the guest writes a value to CFGMSK register when trying to map config space. This is done in the board firmware in ppc4xx_init_pcie_port() in roms/u-boot-sam460ex/arch/powerpc/cpu/ppc4xx/4xx_pcie.c It's not clear what the proper fix should be but for now let's force the size to 256MB, so anything outside the expected address range is ignored. Fixes: commit 1f1a7b2269 ("include/hw/pci/pcie_host: Correct PCIE_MMCFG_SIZE_MAX") Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220526224229.95183-1-mst@redhat.com> [danielhb: changed commit msg as BALATON Zoltan suggested] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-20target/ppc: Implemented vector module quadwordLucas Mateus Castro (alqotel)
Implement the following PowerISA v3.1 instructions: vmodsq: Vector Modulo Signed Quadword vmoduq: Vector Modulo Unsigned Quadword Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/744 Message-Id: <20220525134954.85056-9-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-20target/ppc: Implemented vector module word/doublewordLucas Mateus Castro (alqotel)
Implement the following PowerISA v3.1 instructions: vmodsw: Vector Modulo Signed Word vmoduw: Vector Modulo Unsigned Word vmodsd: Vector Modulo Signed Doubleword vmodud: Vector Modulo Unsigned Doubleword Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220525134954.85056-8-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-06-20target/ppc: Implemented remaining vector divide extendedLucas Mateus Castro (alqotel)
Implement the following PowerISA v3.1 instructions: vdivesd: Vector Divide Extended Signed Doubleword vdiveud: Vector Divide Extended Unsigned Doubleword vdivesq: Vector Divide Extended Signed Quadword vdiveuq: Vector Divide Extended Unsigned Quadword Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220525134954.85056-7-lucas.araujo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-02 12:09:41 +0000