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2011-10-08target-alpha: Honor icount for RPCC instruction.Richard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2011-10-08Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafBlue Swirl
* 'ppc-next' of git://repo.or.cz/qemu/agraf: (64 commits) ppc64: Fix linker script pseries: Implement set-time-of-day RTAS function pseries: Refactor spapr irq allocation PPC: Clean up BookE timer code PPC: booke timers KVM: PPC: Use HIOR setting for -M pseries with PR KVM KVM: Update kernel headers KVM: Update kernel headers PPC: Fix heathrow PIC to use little endian MMIO PPC: Fix via-cuda memory registration ppc: move ADB stuff from ppc_mac.h to adb.h openpic: Unfold write_IRQreg openpic: Unfold read_IRQreg ppc405: use RAM_ADDR_FMT instead of %08lx Gdbstub: handle read of fpscr vscsi: send the CHECK_CONDITION status down together with autosense data pseries: Implement hcall-bulk hypervisor interface Implement POWER7's CFAR in TCG ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages ppc: booke206: add "info tlb" support ...
2011-10-08ARM: fix segfaultBlue Swirl
Fix a bug in bccd9ec5f098668576342c83d90d6d6833d61d33, target-arm/op_helper.c missed a change unlike all other targets. This lead to a NULL pointer dereferences. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-06ppc64: Fix linker scriptAndreas Färber
Since commit 8733f609 (Fix linker scripts) linking on Linux/ppc64 fails: LINK ppc64-linux-user/qemu-ppc64 /usr/lib64/gcc/powerpc64-suse-linux/4.3/../../../../powerpc64-suse-linux/bin/ld:/home/afaerber/qemu/ppc64.ld:84: syntax error collect2: ld gab 1 als Ende-Status zurück make[1]: *** [qemu-ppc64] Fehler 1 make: *** [subdir-ppc64-linux-user] Fehler 2 Fix by removing a leftover line in the ppc64 linker script. Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06pseries: Implement set-time-of-day RTAS functionBreno Leitao
Currently there is no implementation for set-time-of-day rtas function, which causes the following warning "setting the clock failed (-1)" on the guest. This patch just creates this function, get the timedate diff and store in the papr environment, so that the correct value will be returned by get-time-of-day. In order to try it, just adjust the hardware time, run hwclock --systohc, so that, on when the system runs hwclock --hctosys, the value is correctly adjusted, i.e. the host time plus the timediff. Signed-off-by: Breno Leitao <brenohl@br.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06pseries: Refactor spapr irq allocationDavid Gibson
Paulo Bonzini changed the original spapr code, which manually assigned irq numbers for each virtual device, to allocate them automatically from the device initialization. That allowed spapr virtual devices to be constructed with -device, which is a good start. However, the way that patch worked doesn't extend nicely for the future when we want to support devices other than sPAPR VIO devices (e.g. virtio and PCI). This patch rearranges the irq allocation to be global across the sPAPR environment, so it can be used by other bus types as well. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Clean up BookE timer codeAlexander Graf
The BookE timer code had some written-but-not-read variables. Get rid of them. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: booke timersFabien Chouteau
While working on the emulation of the freescale p2010 (e500v2) I realized that there's no implementation of booke's timers features. Currently mpc8544 uses ppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (for example booke uses different SPR). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06KVM: PPC: Use HIOR setting for -M pseries with PR KVMAlexander Graf
When running with PR KVM, we need to set HIOR directly. Thankfully there is now a new interface to set registers individually so we can just use that and poke HIOR into the guest vcpu's HIOR register. While at it, this also sets SDR1 because -M pseries requires it to run. With this patch, -M pseries works properly with PR KVM. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06KVM: Update kernel headersAlexander Graf
Update HIOR and generic register get/set. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06KVM: Update kernel headersAlexander Graf
Removes ABI-breaking HIOR parts - KVM patch to follow. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Fix heathrow PIC to use little endian MMIOAlexander Graf
During the memory API conversion, the indication on little endianness of MMIO for the heathrow PIC got dropped. This patch adds it back again. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Fix via-cuda memory registrationAlexander Graf
Commit 23c5e4ca (convert to memory API) broke the VIA Cuda emulation layer by not registering the IO structs. This patch registers them properly and thus makes -M g3beige and -M mac99 work again. Tested-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06ppc: move ADB stuff from ppc_mac.h to adb.hLaurent Vivier
Allow to use ADB in non-ppc macintosh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06openpic: Unfold write_IRQregAlexander Graf
The helper function write_IRQreg was always called with a specific argument on the type of register to access. Inside the function we were simply doing a switch on that constant argument again. It's a lot easier to just unfold this into two separate functions and call each individually. Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06openpic: Unfold read_IRQregAlexander Graf
The helper function read_IRQreg was always called with a specific argument on the type of register to access. Inside the function we were simply doing a switch on that constant argument again. It's a lot easier to just unfold this into two separate functions and call each individually. Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06ppc405: use RAM_ADDR_FMT instead of %08lxStefan Hajnoczi
The RAM_ADDR_FMT macro hides the type of ram_addr_t so that format strings can be safely used. Make sure to use RAM_ADDR_FMT so that the build works on 32-bit hosts with Xen enabled. Whether Xen should affect ppc TCG targets is questionable but a separate issue. Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06Gdbstub: handle read of fpscrFabien Chouteau
Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06vscsi: send the CHECK_CONDITION status down together with autosense dataPaolo Bonzini
I introduced this bug in commit 05751d3 (vscsi: always use get_sense, 2011-08-03) because at the time there was no way to expose a sense condition to SLOF and Linux manages to work around the bug. However, the bug becomes evident now that SCSI devices also report unit attention on reset. SLOF also has problems dealing with unit attention conditions, so it still will not boot even with this fix (just like OpenBIOS). IBM folks are aware of their part of the bug. :-) Reported-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06pseries: Implement hcall-bulk hypervisor interfaceDavid Gibson
This patch adds support for the H_REMOVE_BULK hypercall on the pseries machine. Strictly speaking this isn't necessarym since the kernel will only attempt to use this if hcall-bulk is advertised in the device tree, which previously it was not. Adding this support may give a marginal performance increase, but more importantly it reduces the differences between the emulated machine and an existing PowerVM or kvm system, both of which already implement hcall-bulk. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06Implement POWER7's CFAR in TCGDavid Gibson
This patch implements support for the CFAR SPR on POWER7 (Come From Address Register), which snapshots the PC value at the time of a branch or an rfid. The latest powerpc-next kernel also catches it and can show it in xmon or in the signal frames. This works well enough to let recent kernels boot (which otherwise oops on the CFAR access). It hasn't been tested enough to be confident that the CFAR values are actually accurate, but one thing at a time. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pagesScott Wood
This definition is backward compatible with MAV=1.0 as long as the guest does not set reserved bits in MAS1/MAS4. Also, fix the shift in booke206_tlb_to_page_size -- it's the base that should be able to hold a 4G page size, not the shift count. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06ppc: booke206: add "info tlb" supportScott Wood
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06kvm: ppc: booke206: use MMU APIScott Wood
Share the TLB array with KVM. This allows us to set the initial TLB both on initial boot and reset, is useful for debugging, and could eventually be used to support migration. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06KVM: Update kernel headersAlexander Graf
Another round of KVM features, another round of kernel header updates :) Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06pseries: use macro for firmware filenameNishanth Aravamudan
For some time we've had a nicely defined macro with the filename for our firmware image. However we didn't actually use it in the place we're supposed to. This patch fixes it. Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06pseries: Add real mode debugging hcallsDavid Gibson
PAPR systems support several hypercalls intended for use in real mode debugging tools. These implement reads and writes to arbitrary guest physical addresses. This is useful for real mode software because it allows access to IO addresses and memory outside the RMA without going through the somewhat involved process of setting up the hash page table and enabling translation. We want these so that when we add real IO devices, the SLOF firmware can boot from them without having to enter virtual mode. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Fix sync instructions problem in SMPElie Richa
In the current emulation of the load-and-reserve (lwarx) and store-conditional (stwcx.) instructions, the internal reservation mechanism is taken into account, however each CPU has its own reservation information and this information is not synchronized between CPUs to perform proper synchronization. The following test case with 2 CPUs shows that the semantics of the "lwarx" and "stwcx." instructions are not preserved by the emulation. The test case does the following : - CPU0: reserve a memory location - CPU1: reserve the same memory location - CPU0: perform stwcx. on the location The last store-conditional operation succeeds while it is supposed to fail since the reservation was supposed to be lost at the second reserve operation. This (one line) patch fixes this problem in a very simple manner by removing the reservation of a CPU every time it is scheduled (in cpu_exec()). While this is a harsh workaround, it does not affect the guest code much because reservations are usually held for a very short time, that is an lwarx is almost always followed by an stwcx. a few instructions below. Therefore, in most cases, the reservation will be taken and consumed before a CPU switch occurs. However in the rare case where a CPU switch does occur between the lwarx and its corresponding stwcx. this patch solves a potential erroneous behavior of the synchronization instructions. Signed-off-by: Elie Richa <richa@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06pseries: More complete WIMG validation in H_ENTER codeDavid Gibson
Currently our implementation of the H_ENTER hypercall, which inserts a mapping in the hash page table assumes that only ordinary memory is ever mapped, and only permits mapping attribute bits accordingly (WIMG==0010). However, we intend to start adding emulated IO to the pseries platform (and real IO with PCI passthrough on kvm) which means this simple test will no longer suffice. This patch extends the h_enter validation code to check if the given address is a RAM address. If it is it enforces WIMG==0010, otherwise it assumes that it is an IO mapping and instead enforces WIMG=010x. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06pseries: interrupt controller should not have a 'reg' propertyDavid Gibson
The interrupt controller presented in the device tree for the pseries machine is manipulated by the guest only through hypervisor calls. It has no real or emulated registers for the guest to access. However, it currently has a bogus 'reg' property advertising a register window. Moreover, this property has an invalid format, being a 32-bit zero, when the #address-cells property on the root bus indicates that it needs a 64-bit address. Since the guest never attempts to manipulate the node directly, it works, but it is ugly and can cause warnings when manipulating the device tree in other tools (such as future firmware versions). This patch, therefore, corrects the problem by entirely removing the interrupt-controller node's 'reg' property. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06pseries: Add a phandle to the xicp interrupt controller device tree nodeDavid Gibson
Future devices we will be adding to the pseries machine (e.g. PCI) will need nodes in the device tree which explicitly reference the top-level interrupt controller via interrupt-parent or interrupt-map properties. In order to do this, the interrupt controller node needs an assigned phandle. This patch adds the appropriate property, in preparation. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06pseries: Bugfixes for interrupt numbering in XICS codeDavid Gibson
The implementation of the XICS interrupt controller contains several (difficult to trigger) bugs due to the fact that we were not 100% consistent with which irq numbering we used. In most places, global numbers were used as handled by the presentation layer, however a few functions took "local" numberings, that is the source number within the interrupt source controller which is offset from the global number. In most cases the function and its caller agreed on this, but in a few cases it didn't. This patch cleans this up by always using global numbering. Translation to the local number is now always and only done when we look up the individual interrupt source state structure. This should remove the existing bugs and with luck reduce the chances of re-introducing such bugs. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: SPAPR: Use KVM function for time infoAlexander Graf
One of the things we can't fake on PPC is the timer speed. So we need to extract the frequency information from the host and put it back into the guest device tree. Luckily, we already have functions for that from the non-pseries targets, so all we need to do is to connect the dots and the guest suddenly gets to know its real timer speeds. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Enable to use PAPR with PR style KVMAlexander Graf
When running PR style KVM, we need to tell the kernel that we want to run in PAPR mode now. This means that we need to pass some more register information down and enable papr mode. We also need to align the HTAB to htab_size boundary. Using this patch, -M pseries works with kvm even on non-hv kvm implementations, as long as the preceding kernel patches are in. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - match on CONFIG_PSERIES v2 -> v3: - remove HIOR pieces from PAPR patch (ABI breakage)
2011-10-06KVM: update kernel headersAlexander Graf
This patch updates the kvm kernel headers to the latest version. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: Add new target config for pseriesAlexander Graf
We only support -M pseries when certain prerequisites are met, such as a PPC64 guest and libfdt. To only gather these requirements in a single place, this patch introduces a new CONFIG_PSERIES variable that gets set when all prerequisites are met. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Bump CPU count to 15Alexander Graf
Now that we have everything in place, make the machine description aware of the fact that we can now handle 15 virtual CPUs! Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - Max cpus is 15 because of MPIC
2011-10-06MPC8544DS: Generate CPU nodes on initAlexander Graf
With this patch, we generate CPU nodes in the machine initialization, giving us the freedom to generate as many nodes as we want and as the machine supports, but only those. This is a first step towards a much cleaner device tree generation infrastructure, where we would not require precompiled dtb blobs anymore. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06MPC8544DS: Remove CPU nodesAlexander Graf
We want to generate the CPU nodes in machine init code, so remove them from the device tree definition that we precompile. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06device tree: give dt more sizeAlexander Graf
We currently load a device tree blob and then just take its size x2 to account for modifications we do inside. While this is nice and great, it fails when we have a small device tree as blob and lots of nodes added in machine init code. So for now, just make it 20k bigger than it was before. We maybe want to be more clever about this later. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06device tree: dont fail operationsAlexander Graf
When we screw up and issue an FDT command that doesn't work, we really need to know immediately and usually can't continue to create the machine. To make sure we don't need to add error checking in all device tree modification code users, we can just add the fail checks to the qemu abstract functions. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06device tree: add add_subnode commandAlexander Graf
We want to be able to create subnodes in our device tree, so export it through the qemu device tree abstraction framework. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Update cpu-release-addr property in cpu nodesAlexander Graf
The guest OS wants to know where the guest spins, so let's tell him while updating the CPU nodes with the frequencies anyways. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - use new spin table address
2011-10-06PPC: E500: Add PV spinning codeAlexander Graf
CPUs that are not the boot CPU need to run in spinning code to check if they should run off to execute and if so where to jump to. This usually happens by leaving secondary CPUs looping and checking if some variable in memory changed. In an environment like Qemu however we can be more clever. We can just export the spin table the primary CPU modifies as MMIO region that would event based wake up the respective secondary CPUs. That saves us quite some cycles while the secondary CPUs are not up yet. So this patch adds a PV device that simply exports the spinning table into the guest and thus allows the primary CPU to wake up secondary ones. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - change into MMIO scheme - map the secondary NIP instead of 0 1:1 - only map 64MB for TLB, same as u-boot - prepare code for 64-bit spinnings v2 -> v3: - remove r6 - set MAS2_M - map EA 0 - use second TLB1 entry v3 -> v4: - change to memoryops v4 -> v5: - fix endianness bugs v5 -> v6: - add header
2011-10-06PPC: E500: Remove unneeded CPU nodesAlexander Graf
We should only keep CPU nodes in the device tree around that we really have virtual CPUs for. So remove all superfluous entries that we just keep there in case someone wants to create a lot of vCPUs. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Update freqs for all CPUsAlexander Graf
Now that we can so nicely find out the host's frequencies, we should also make sure that we get them into all virtual CPUs' device tree nodes. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: KVM: Add stubs for kvm helper functionsAlexander Graf
We have a bunch of helper functions that don't have any stubs for them in case we don't have CONFIG_KVM enabled. That didn't bite us so far, because gcc can optimize them out pretty well, but we should really provide them. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - use uint64_t for clockfreq
2011-10-06PPC: KVM: Remove kvmppc_read_host_propertyAlexander Graf
We just got rid of the last user of kvmppc_read_host_property, so we can now safely remove it. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: bamboo: Use kvm api for freq and clock frequenciesAlexander Graf
Now that we have nice and shiny APIs to read out the host's clock and timebase frequencies, let's use them in the bamboo code as well! Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06PPC: E500: Remove mpc8544_copy_soc_cellAlexander Graf
We don't need mpc8544_copy_soc_cell anymore, since we're explicitly reading host values and writing guest values respectively. Signed-off-by: Alexander Graf <agraf@suse.de>
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