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2023-10-27hw/sd/pxa2xx: Do not open-code sysbus_create_simple()Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231020130331.50048-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/sd/pxa2xx: Realize sysbus device before accessing itPhilippe Mathieu-Daudé
sysbus_mmio_map() and sysbus_connect_irq() should not be called on unrealized device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231020130331.50048-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/xlnx-zynqmp: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-11-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/xlnx-versal: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-10-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/fsl-imx7: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-9-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/fsl-imx6ul: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-8-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/fsl-imx6: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-7-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/fsl-imx31: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-6-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/fsl-imx25: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/allwinner-r40: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-4-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/allwinner-h3: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27hw/arm/allwinner-a10: Remove 'hw/arm/boot.h' from headerPhilippe Mathieu-Daudé
"hw/arm/boot.h" is only required on the source file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-id: 20231025065316.56817-2-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-10-27target/arm: Fix syndrome for FGT traps on ERETPeter Maydell
In commit 442c9d682c94fc2 when we converted the ERET, ERETAA, ERETAB instructions to decodetree, the conversion accidentally lost the correct setting of the syndrome register when taking a trap because of the FEAT_FGT HFGITR_EL1.ERET bit. Instead of reporting a correct full syndrome value with the EC and IL bits, we only reported the low two bits of the syndrome, because the call to syn_erettrap() got dropped. Fix the syndrome values for these traps by reinstating the syn_erettrap() calls. Fixes: 442c9d682c94fc2 ("target/arm: Convert ERET, ERETAA, ERETAB to decodetree") Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024172438.2990945-1-peter.maydell@linaro.org
2023-10-27target/arm: Move ID_AA64DFR* feature tests togetherPeter Maydell
Move all the ID_AA64DFR* feature test functions together. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-7-peter.maydell@linaro.org
2023-10-27target/arm: Move ID_AA64PFR* tests togetherPeter Maydell
Move all the ID_AA64PFR* feature test functions together. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-6-peter.maydell@linaro.org
2023-10-27target/arm: Move ID_AA64ISAR* test functions togetherPeter Maydell
Move the feature test functions that test ID_AA64ISAR* fields together. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-5-peter.maydell@linaro.org
2023-10-27target/arm: Move ID_AA64MMFR0 tests up to before MMFR1 and MMFR2Peter Maydell
Move the ID_AA64MMFR0 feature test functions up so they are before the ones for ID_AA64MMFR1 and ID_AA64MMFR2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-4-peter.maydell@linaro.org
2023-10-27target/arm: Move ID_AA64MMFR1 and ID_AA64MMFR2 tests togetherPeter Maydell
Our list of isar_feature functions is not in any particular order, but tests on fields of the same ID register tend to be grouped together. A few functions that are tests of fields in ID_AA64MMFR1 and ID_AA64MMFR2 are not in the same place as the rest; move them into their groups. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-3-peter.maydell@linaro.org
2023-10-27target/arm: Move feature test functions to their own headerPeter Maydell
The feature test functions isar_feature_*() now take up nearly a thousand lines in target/arm/cpu.h. This header file is included by a lot of source files, most of which don't need these functions. Move the feature test functions to their own header file. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231024163510.2972081-2-peter.maydell@linaro.org
2023-10-27target/arm: Implement Neoverse N2 CPU modelPeter Maydell
Implement a model of the Neoverse N2 CPU. This is an Armv9.0-A processor very similar to the Cortex-A710. The differences are: * no FEAT_EVT * FEAT_DGH (data gathering hint) * FEAT_NV (not yet implemented in QEMU) * Statistical Profiling Extension (not implemented in QEMU) * 48 bit physical address range, not 40 * CTR_EL0.DIC = 1 (no explicit icache cleaning needed) * PMCR_EL0.N = 6 (always 6 PMU counters, not 20) Because it has 48-bit physical address support, we can use this CPU in the sbsa-ref board as well as the virt board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230915185453.1871167-3-peter.maydell@linaro.org
2023-10-27target/arm: Correct minor errors in Cortex-A710 definitionPeter Maydell
Correct a couple of minor errors in the Cortex-A710 definition: * ID_AA64DFR0_EL1.DebugVer is 9 (indicating Armv8.4 debug architecture) * ID_AA64ISAR1_EL1.APA is 5 (indicating more PAuth support) * there is an IMPDEF CPUCFR_EL1, like that on the Neoverse-N1 Fixes: e3d45c0a89576 ("target/arm: Implement cortex-a710") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230915185453.1871167-2-peter.maydell@linaro.org
2023-10-27Merge tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi
Convert target/sparc to decodetree. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmU5ruAdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9NWQgAjkWxZi9Je3yWR0x0 # mQmlx0zlyjK4PeMGS14mr0mxFAqvC5gFHNzw0WtLaVw9gyfm6EKXwervtm9mCg7F # PPQzF9IqSoKqGV2fFlWpVWmUPmKNhLY5hS7Pvampg8Tkt6X6NJQdbaUpEQW6U47I # C4/AAygaj6fd99BEZI36A2oxg6D0HM9cV1LUm43e+yQ1KCQaTO+3u8oDZA8MkXu1 # p2bxPXazClLe+ywwtR9tp28IgQszQ10NxECzhJ34ezLCbTreH//ycpPI2h8Xskdc # lDkCu3OJa8aIalGOpDL71Qemp9KfRYkOyPlahAZx3haZC24fnVvVRoMiV8Z5+iYk # gq2VnA== # =/gf2 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 26 Oct 2023 09:12:16 JST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-sp-20231025' of https://gitlab.com/rth7680/qemu: (94 commits) target/sparc: Remove disas_sparc_legacy target/sparc: Convert FZERO, FONE to decodetree target/sparc: Move FPACK16, FPACKFIX to decodetree target/sparc: Move FPCMP* to decodetree target/sparc: Convert FCMP, FCMPE to decodetree target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree target/sparc: Move FMOVq, FNEGq, FABSq to decodetree target/sparc: Move FdTOq, FxTOq to decodetree target/sparc: Move FiTOq, FsTOq to decodetree target/sparc: Move FqTOd, FqTOx to decodetree target/sparc: Move FqTOs, FqTOi to decodetree target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree target/sparc: Move gen_fop_FD insns to decodetree target/sparc: Move FDMULQ to decodetree target/sparc: Move FSMULD to decodetree target/sparc: Move gen_fop_QQQ insns to decodetree target/sparc: Move gen_fop_DDD insns to decodetree target/sparc: Move gen_fop_FFF insns to decodetree target/sparc: Move FSQRTq to decodetree target/sparc: Move gen_fop_DD insns to decodetree ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-27Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi
* target/i386: implement SHA instructions * target/i386: check CPUID_PAE to determine 36 bit processor address space * target/i386: improve validation of AVX instructions * require Linux 4.4 for KVM # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmU5Vi4UHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroNVbwf9HCx+C0MITWjQ+rEkmtiy/Cn+ZsF1 # gbaL31ahymEU3vUcKZX8Z4ycmBFw9b3yvotTVR38lE9p+sKtSaGKUGV0btpS7oBB # y8IfnVmg5X1j4PtyDxFlLD48qg//2kVgJ6wtaDTSAkgQMOPM9UgHgQD+Ks7kOo8v # rReL46XVPEZTWt3syX0y87mFinjK2hXGqIdsnJ1uT614BAVVIrmO6aFNNN1FlsRb # NGRZevJTfEWjWVfWOhUiZdUGDz74sOXdshZX/teadeDJLtWaw0uytMN9qoTN33h/ # OsdR2fO7h8ZknGEc2F1fJEVh4sOfO4fGYAAJGzHP9AjUDV1IVVYELb79dg== # =WYTo # -----END PGP SIGNATURE----- # gpg: Signature made Thu 26 Oct 2023 02:53:50 JST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (24 commits) kvm: i8254: require KVM_CAP_PIT2 and KVM_CAP_PIT_STATE2 kvm: i386: require KVM_CAP_SET_IDENTITY_MAP_ADDR kvm: i386: require KVM_CAP_ADJUST_CLOCK kvm: i386: require KVM_CAP_MCE kvm: i386: require KVM_CAP_SET_VCPU_EVENTS and KVM_CAP_X86_ROBUST_SINGLESTEP kvm: i386: require KVM_CAP_XSAVE kvm: i386: require KVM_CAP_DEBUGREGS kvm: i386: move KVM_CAP_IRQ_ROUTING detection to kvm_arch_required_capabilities kvm: unify listeners for PIO address space kvm: require KVM_CAP_IOEVENTFD and KVM_CAP_IOEVENTFD_ANY_LENGTH kvm: assume that many ioeventfds can be created kvm: drop reference to KVM_CAP_PCI_2_3 kvm: require KVM_IRQFD for kernel irqchip kvm: require KVM_IRQFD for kernel irqchip kvm: require KVM_CAP_SIGNAL_MSI kvm: require KVM_CAP_INTERNAL_ERROR_DATA kvm: remove unnecessary stub target/i386: check CPUID_PAE to determine 36 bit processor address space target/i386: validate VEX.W for AVX instructions target/i386: group common checks in the decoding phase ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-27Merge tag 'pull-aspeed-20231025' of https://github.com/legoater/qemu into ↵Stefan Hajnoczi
staging aspeed queue: * Update of Andrew's email * Split of AspeedSoCState per 2400/2600/10x0 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmU419UACgkQUaNDx8/7 # 7KHU+RAAxsGnrbUtKm7FZUm8pCW6zxe0A3Z1g70vDsJeiPuYA6qwI4cmDRn+bMHS # XL67s4htntTLQbE7Rs02uGIwG62rcU1vnUYRMw6KtvUXiM5zI+uUc0q3UYXNxNyR # U7Tvz8Yryig8tWdKqU/1weieF0LE01B2fQXiI6XF4p3aHvASqKQ1FAHiLrEaQ6/q # 2qt6sKO0My/zLkQxlQY+1j2JMvt9utbXzRFR42h1cKl1md81gRR+I2pkzUDFfPqZ # +HuQHUaipHEW9HNra1CRrSuTw/BTNks1CCTqv3eFhLhNWjAl6lpi/clNz6+TGA5k # kKsXqLe6xwRdxXaZU2VQ3QYrpsQw+zy4WDEHoaGCFrmtnketpCpw9ZE24pUXnA0s # p5rIJX9hv4McWgNmfFPv0G9M1Pp/4xiaOJQIN3lW7fEL9gkgA8zxEl1MCVlNwt+R # 4FZU6S152elfYxl2WZHSqOyShDq9zNKPl0kvkbqzQDLaG0CX9RaAVbEBS0ecssW+ # aHlnjcRHjS7lskfdAdG881lHObnUFsOzyIAW2GNyfJb8CNvxNfMLUxv/Opz2h9+V # vmYhaNIsUU3rHXUPYuZGjuxklKpXDhIl9vKkxIbBME14TSk8g7XdqrpeXXz7WG78 # jWQbbcapdaHW2ITWGhox9P4lBEgu6UT2X+rHt5yob1DPLPw7L60= # =NICz # -----END PGP SIGNATURE----- # gpg: Signature made Wed 25 Oct 2023 17:54:45 JST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [unknown] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20231025' of https://github.com/legoater/qemu: hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific hw/arm/aspeed: Extract code common to all boards to a common file MAINTAINERS: aspeed: Update Andrew's email address Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-10-25kvm: i8254: require KVM_CAP_PIT2 and KVM_CAP_PIT_STATE2Paolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: require KVM_CAP_SET_IDENTITY_MAP_ADDRPaolo Bonzini
This was introduced in KVM in Linux 2.6.32, we can require it unconditionally. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: require KVM_CAP_ADJUST_CLOCKPaolo Bonzini
This was introduced in KVM in Linux 2.6.33, we can require it unconditionally. KVM_CLOCK_TSC_STABLE was only added in Linux 4.9, for now do not require it (though it would allow the removal of some pretty yucky code). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: require KVM_CAP_MCEPaolo Bonzini
This was introduced in KVM in Linux 2.6.34, we can require it unconditionally. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: require KVM_CAP_SET_VCPU_EVENTS and KVM_CAP_X86_ROBUST_SINGLESTEPPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: require KVM_CAP_XSAVEPaolo Bonzini
This was introduced in KVM in Linux 2.6.36, and could already be used at the time to save/restore FPU data even on older processor. We can require it unconditionally and stop using KVM_GET/SET_FPU. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: require KVM_CAP_DEBUGREGSPaolo Bonzini
This was introduced in KVM in Linux 2.6.35, we can require it unconditionally. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: i386: move KVM_CAP_IRQ_ROUTING detection to kvm_arch_required_capabilitiesPaolo Bonzini
Simple code cleanup. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: unify listeners for PIO address spacePaolo Bonzini
Since we now assume that ioeventfds are present, kvm_io_listener is always registered. Merge it with kvm_coalesced_pio_listener in a single listener. Since PIO space does not have KVM memslots attached to it, the priority is irrelevant. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: require KVM_CAP_IOEVENTFD and KVM_CAP_IOEVENTFD_ANY_LENGTHPaolo Bonzini
KVM_CAP_IOEVENTFD_ANY_LENGTH was added in Linux 4.4, released in 2016. Assume that it is present. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: assume that many ioeventfds can be createdPaolo Bonzini
NR_IOBUS_DEVS was increased to 200 in Linux 2.6.34. By Linux 3.5 it had increased to 1000 and later ioeventfds were changed to not count against the limit. But the earlier limit of 200 would already be enough for kvm_check_many_ioeventfds() to be true, so remove the check. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: drop reference to KVM_CAP_PCI_2_3Paolo Bonzini
This is a remnant of pre-VFIO device assignment; it is not defined anymore by Linux and not used by QEMU. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: require KVM_IRQFD for kernel irqchipPaolo Bonzini
KVM_IRQFD was introduced in Linux 2.6.32, and since then it has always been available on architectures that support an in-kernel interrupt controller. We can require it unconditionally. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: require KVM_IRQFD for kernel irqchipPaolo Bonzini
KVM_IRQFD was introduced in Linux 2.6.32, and since then it has always been available on architectures that support an in-kernel interrupt controller. We can require it unconditionally. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: require KVM_CAP_SIGNAL_MSIPaolo Bonzini
This was introduced in KVM in Linux 3.5, we can require it unconditionally in kvm_irqchip_send_msi(). However, not all architectures have to implement it so check it only in x86, the only architecture that ever had MSI injection but not KVM_CAP_SIGNAL_MSI. ARM uses it to detect the presence of the ITS emulation in the kernel, introduced in Linux 4.8. Assume that it's there and possibly fail when realizing the arm-its-kvm device. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: require KVM_CAP_INTERNAL_ERROR_DATAPaolo Bonzini
This was introduced in KVM in Linux 2.6.33, we can require it unconditionally. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25kvm: remove unnecessary stubPaolo Bonzini
This function is only invoked from hw/intc/s390_flic_kvm.c, and therefore only if CONFIG_KVM is defined. Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25target/i386: check CPUID_PAE to determine 36 bit processor address spaceAni Sinha
PAE mode in x86 supports 36 bit address space. Check the PAE CPUID on the guest processor and set phys_bits to 36 if PAE feature is set. This is in addition to checking the presence of PSE36 CPUID feature for setting 36 bit phys_bits. Signed-off-by: Ani Sinha <anisinha@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-ID: <20230912120650.371781-1-anisinha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25target/i386: validate VEX.W for AVX instructionsPaolo Bonzini
Instructions in VEX exception class 6 generally look at the value of VEX.W. Note that the manual places some instructions incorrectly in class 4, for example VPERMQ which has no non-VEX encoding and no legacy SSE analogue. AMD does a mess of its own, as documented in the comment that this patch adds. Most of them are checked for VEX.W=0, and are listed in the manual (though with an omission) in table 2-16; VPERMQ and VPERMPD check for VEX.W=1, which is only listed in the instruction description. Others, such as VPSRLV, VPSLLV and the FMA3 instructions, use VEX.W to switch between a 32-bit and 64-bit operation. Fix more of the class 4/class 6 mismatches, and implement the check for VEX.W in TCG. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25target/i386: group common checks in the decoding phasePaolo Bonzini
In preparation for adding more similar checks, move the VEX.L=0 check and several X86_SPECIAL_* checks to a new field, where each bit represent a common check on unused bits, or a restriction on the processor mode. Likewise, many SVM intercepts can be checked during the decoding phase, the main exception being the selective CR0 write, MSR and IOIO intercepts. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25tests/tcg/i386: test-avx: add test cases for SHA new instructionsPaolo Bonzini
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25tests/tcg/i386: initialize more registers in test-avxPaolo Bonzini
Some instructions use YMM0 implicitly, or use YMM9 as a read-modify-write register destination. Initialize those registers as well. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25target/i386: implement SHA instructionsPaolo Bonzini
The implementation was validated with OpenSSL and with the test vectors in https://github.com/rust-lang/stdarch/blob/master/crates/core_arch/src/x86/sha.rs. The instructions provide a ~25% improvement on hashing a 64 MiB file: runtime goes down from 1.8 seconds to 1.4 seconds; instruction count on the host goes down from 5.8 billion to 4.8 billion with slightly better IPC too. Good job Intel. ;) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25tests/tcg: fix out-of-bounds access in test-avxPaolo Bonzini
This can cause differences between native and QEMU execution, due to ASLR. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-10-25target/sparc: Remove disas_sparc_legacyRichard Henderson
All instructions are now converted. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25target/sparc: Convert FZERO, FONE to decodetreeRichard Henderson
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-02 12:35:00 +0000