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2019-05-21s390x/cpumodel: add Deflate-conversion facilityChristian Borntraeger
add the deflate conversion facility. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20190429090250.7648-8-borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21s390x/cpumodel: enhanced sort facilityChristian Borntraeger
add the enhanced sort facility. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20190429090250.7648-7-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21s390x/cpumodel: vector enhancementsChristian Borntraeger
Add vector enhancements to the cpu model. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20190429090250.7648-6-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21s390x/cpumodel: msa9 facilityChristian Borntraeger
Provide the MSA9 facility (stfle.155). This also contains pckmo subfunctions for key wrapping. Keep them in a separate group to disable those as a block if necessary. This is for example needed when disabling key wrapping via the HMC. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20190429090250.7648-5-borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21s390x/cpumodel: Miscellaneous-Instruction-Extensions Facility 3Christian Borntraeger
Provide the "Miscellaneous-Instruction-Extensions Facility 3" via stfle.61. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20190429090250.7648-4-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21s390x/cpumodel: ignore csske for expansionChristian Borntraeger
csske will be removed in a future machine. Ignore it for expanding the cpu model. Otherwise qemu falls back to z9. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Cc: qemu-stable@nongnu.org Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20190429090250.7648-3-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21linux headers: update against Linux 5.2-rc1Cornelia Huck
commit a188339ca5a396acc588e5851ed7e19f66b0ebd9 Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-21update-linux-headers: handle new header fileCornelia Huck
We need to copy sve_context.h for aarch64. Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-17Merge tag 's390x-tcg-2019-05-17-2' into s390-next-stagingCornelia Huck
Implement all Vector Integer Instructions introduced with the "Vector Facility" for s390x TCG. # gpg: Signature made Fri 17 May 2019 01:37:40 PM CEST # gpg: using RSA key 4DDE10F700FF835A # gpg: Good signature from "David Hildenbrand <david@redhat.com>" [full] # gpg: aka "David Hildenbrand <davidhildenbrand@gmail.com>" [full] * tag 's390x-tcg-2019-05-17-2': (40 commits) s390x/tcg: Implement VECTOR TEST UNDER MASK s390x/tcg: Implement VECTOR SUM ACROSS WORD s390x/tcg: Implement VECTOR SUM ACROSS QUADWORD s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORD s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATION s390x/tcg: Implement VECTOR SUBTRACT s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL * s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETIC s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTE s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE) s390x/tcg: Implement VECTOR ELEMENT SHIFT s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICAL s390x/tcg: Implement VECTOR POPULATION COUNT s390x/tcg: Implement VECTOR OR WITH COMPLEMENT s390x/tcg: Implement VECTOR OR s390x/tcg: Implement VECTOR NOT EXCLUSIVE OR s390x/tcg: Implement VECTOR NOR ... Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR TEST UNDER MASKDavid Hildenbrand
Let's return the cc value directly via cpu_env. Unfortunately there isn't a simple way to calculate the value lazily - one would have to calculate and store e.g. the population count of the mask and the result so it can be evaluated in a cc helper. But as VTM only sets the cc, we can assume the value will be needed soon either way. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUM ACROSS WORDDavid Hildenbrand
Similar to VECTOR SUM ACROSS DOUBLEWORD. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUM ACROSS QUADWORDDavid Hildenbrand
Similar to VECTOR SUM ACROSS DOUBLEWORD, however without a loop and using 128-bit calculations. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUM ACROSS DOUBLEWORDDavid Hildenbrand
Perform the calculations without a helper. Only 16 bit or 32 bit values have to be added. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW COMPUTE BORROW INDICATIONDavid Hildenbrand
Mostly courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUBTRACT WITH BORROW INDICATIONDavid Hildenbrand
Fairly easy as only 128-bit handling is required. Simply perform the subtraction and then subtract the borrow. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUBTRACT COMPUTE BORROW INDICATIONDavid Hildenbrand
Let's keep it simple for now and handle 8/16 bit elements via helpers. Especially for 8/16, we could come up with some bit tricks. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SUBTRACTDavid Hildenbrand
We can use tcg_gen_sub2_i64() to do 128-bit subtraction and otherwise existing gvec helpers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SHIFT RIGHT LOGICAL *David Hildenbrand
Similar to VECTOR SHIFT RIGHT ARITHMETICAL. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SHIFT RIGHT ARITHMETICDavid Hildenbrand
Similar to VECTOR SHIFT LEFT ARITHMETIC. Add s390_vec_sar() similar to s390_vec_shr(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SHIFT LEFT DOUBLE BY BYTEDavid Hildenbrand
Inline expansion courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR SHIFT LEFT (BY BYTE)David Hildenbrand
We can reuse the existing 128-bit shift utility function. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ELEMENT SHIFTDavid Hildenbrand
We can use all the fancy new vector helpers implemented by Richard. One important thing to take care of is always to properly mask of unused bits from the shift count. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASKDavid Hildenbrand
Use the new vector expansion for GVecGen3i. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ELEMENT ROTATE LEFT LOGICALDavid Hildenbrand
Take care of properly taking the modulo of the count. We might later want to come back and create a variant of VERLL where the base register is 0, resulting in an immediate. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR POPULATION COUNTDavid Hildenbrand
Similar to VECTOR COUNT TRAILING ZEROES. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR OR WITH COMPLEMENTDavid Hildenbrand
Again, vector enhancements facility 1 material. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ORDavid Hildenbrand
Reuse a gvec helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR NOT EXCLUSIVE ORDavid Hildenbrand
Again, part of vector enhancement facility 1. The operation corresponds to an bitwise equality check. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR NORDavid Hildenbrand
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR NANDDavid Hildenbrand
Part of vector enhancements facility 1, but easy to implement. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR MULTIPLY *David Hildenbrand
Yet another set of variants. Implement it similar to VECTOR MULTIPLY AND ADD *. At least for one variant we have a gvec helper we can reuse. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR MULTIPLY AND ADD *David Hildenbrand
Quite some variants to handle. At least handle some 32-bit element variants via gvec expansion (we could also handle 16/32-bit variants for ODD and EVEN easily via gvec expansion, but let's keep it simple for now). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR (MAXIMUM|MINIMUM) (LOGICAL)David Hildenbrand
Luckily, we already have gvec helpers for all four cases. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR LOAD POSITIVEDavid Hildenbrand
Similar to VECTOR LOAD COMPLEMENT. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR LOAD COMPLEMENTDavid Hildenbrand
We can reuse an existing gvec helper for negating the values. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR GALOIS FIELD MULTIPLY SUM (AND ACCUMULATE)David Hildenbrand
A galois field multiplication in field 2 is like binary multiplication, however instead of doing ordinary binary additions, xor's are performed. So no carries are considered. Implement all variants via helpers. s390_vec_sar() and s390_vec_shr() will be reused later on. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR EXCLUSIVE ORDavid Hildenbrand
Easy, we can reuse an existing gvec helper. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR COUNT TRAILING ZEROSDavid Hildenbrand
Implement it similar to VECTOR COUNT LEADING ZEROS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR COUNT LEADING ZEROSDavid Hildenbrand
For 8/16, use the 32 bit variant and properly subtract the added leading zero bits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR COMPARE *David Hildenbrand
To carry out the comparison, we can reuse the existing gvec comparison function. In case the CC is to be computed, save the result vector and compute the CC lazily. The result is a vector consisting of all 1's for elements that matched and 0's for elements that didn't match. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ELEMENT COMPARE *David Hildenbrand
Fairly easy to implement, we can make use of the existing CC helpers cmps64 and cmpu64 - we siply have to sign extend the elements. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR CHECKSUMDavid Hildenbrand
Time to introduce read_vec_element_i32 and write_vec_element_i32. Take proper care of properly adding the carry. We can perform both additions including the carry via tcg_gen_add2_i32(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR AVERAGE LOGICALDavid Hildenbrand
Similar to VECTOR AVERAGE but without sign extension. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR AVERAGEDavid Hildenbrand
Handle 32/64-bit elements via gvec expansion and the 8/16 bits via ool helpers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR AND (WITH COMPLEMENT)David Hildenbrand
Easy, as we can reuse existing gvec helpers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ADD WITH CARRY COMPUTE CARRYDavid Hildenbrand
Similar to VECTOR ADD COMPUTE CARRY, however 128-bit handling only. Courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ADD WITH CARRYDavid Hildenbrand
Only slightly ugly, perform two additions. At least it is only supported for 128 bit elements. Introduce gen_gvec128_4_i64() similar to gen_gvec128_3_i64(). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ADD COMPUTE CARRYDavid Hildenbrand
128-bit handling courtesy of Richard H. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390x/tcg: Implement VECTOR ADDDavid Hildenbrand
Introduce two types of fancy new helpers that will be reused a couple of times 1. gen_gvec_fn_3: Call an existing tcg_gen_gvec_X function with 3 parameters, simplifying parameter passing 2. gen_gvec128_3_i64: Call a function that performs 128 bit calculations using two 64 bit values per vector. Luckily, for VECTOR ADD we already have everything we need. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Hildenbrand <david@redhat.com>
2019-05-17s390/css: handle CCW_FLAG_SKIPCornelia Huck
If a ccw has CCW_FLAG_SKIP set, and the command is of type read, read backwards, or sense, no data should be written to the guest for that command. Reviewed-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20190516133327.11430-1-cohuck@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
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