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2020-06-23target/arm: Make gen_swap_half() take separate src and destPeter Maydell
Make gen_swap_half() take a source and destination TCGv_i32 rather than modifying the input TCGv_i32; we're going to want to be able to use it with the more flexible function signature, and this also brings it into line with other functions like gen_rev16() and gen_revsh(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-12-peter.maydell@linaro.org
2020-06-23target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefsPeter Maydell
All the other typedefs like these spell "Op" with a lowercase 'p'; remane the NeonGenTwoSingleOPFn and NeonGenTwoDoubleOPFn typedefs to match. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-11-peter.maydell@linaro.org
2020-06-23target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFnPeter Maydell
The NeonGenOneOpFn typedef breaks with the pattern of the other NeonGen*Fn typedefs, because it is a TCGv_i64 -> TCGv_i64 operation but it does not have '64' in its name. Rename it to NeonGenOne64OpFn, so that the old name is available for a TCGv_i32 -> TCGv_i32 operation (which we will need in a subsequent commit). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-10-peter.maydell@linaro.org
2020-06-23target/arm: Convert Neon 2-reg-misc crypto operations to decodetreePeter Maydell
Convert the Neon-2-reg misc crypto ops (AESE, AESMC, SHA1H, SHA1SU1) to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-9-peter.maydell@linaro.org
2020-06-23target/arm: Convert vectorised 2-reg-misc Neon ops to decodetreePeter Maydell
Convert to decodetree the insns in the Neon 2-reg-misc grouping which we implement using gvec. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-8-peter.maydell@linaro.org
2020-06-23target/arm: Convert Neon VCVT f16/f32 insns to decodetreePeter Maydell
Convert the Neon insns in the 2-reg-misc group which are VCVT between f32 and f16 to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-7-peter.maydell@linaro.org
2020-06-23target/arm: Convert Neon 2-reg-misc VSHLL to decodetreePeter Maydell
Convert the VSHLL insn in the 2-reg-misc Neon group to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-6-peter.maydell@linaro.org
2020-06-23target/arm: Convert Neon narrowing moves to decodetreePeter Maydell
Convert the Neon narrowing moves VMQNV, VQMOVN, VQMOVUN in the 2-reg-misc group to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-5-peter.maydell@linaro.org
2020-06-23target/arm: Convert VZIP, VUZP to decodetreePeter Maydell
Convert the Neon VZIP and VUZP insns in the 2-reg-misc group to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-4-peter.maydell@linaro.org
2020-06-23target/arm: Convert Neon 2-reg-misc pairwise ops to decodetreePeter Maydell
Convert the pairwise ops VPADDL and VPADAL in the 2-reg-misc grouping to decodetree. At this point we can get rid of the weird CPU_V001 #define that was used to avoid having to explicitly list all the arguments being passed to some TCG gen/helper functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-3-peter.maydell@linaro.org
2020-06-23target/arm: Convert Neon 2-reg-misc VREV64 to decodetreePeter Maydell
Convert the Neon VREV64 insn from the 2-reg-misc grouping to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200616170844.13318-2-peter.maydell@linaro.org
2020-06-23util/oslib-posix : qemu_init_exec_dir implementation for MacDavid CARLIER
From 3025a0ce3fdf7d3559fc35a52c659f635f5c750c Mon Sep 17 00:00:00 2001 From: David Carlier <devnexen@gmail.com> Date: Tue, 26 May 2020 21:35:27 +0100 Subject: [PATCH] util/oslib-posix : qemu_init_exec_dir implementation for Mac Using dyld API to get the full path of the current process. Signed-off-by: David Carlier <devnexen@gmail.com> Message-id: CA+XhMqxwC10XHVs4Z-JfE0-WLAU3ztDuU9QKVi31mjr59HWCxg@mail.gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-23hw/arm/virt: Add 5.0 HW compat propsAndrew Jones
Cc: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-id: 20200616140803.25515-1-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-22Merge remote-tracking branch ↵Peter Maydell
'remotes/philmd-gitlab/tags/acceptance-testing-20200622' into staging Acceptance tests patches - List acceptance test reviewers in MAINTAINERS - Record/Replay tests from Pavel Dovgalyuk Example of use: $ avocado --show=app,replay run -t machine:vexpress-a9 tests/acceptance/replay_kernel.py Fetching asset from tests/acceptance/replay_kernel.py:ReplayKernel.test_arm_vexpressa9 (1/1) tests/acceptance/replay_kernel.py:ReplayKernel.test_arm_vexpressa9: replay: recording the execution... replay: finished the recording with log size 204784 bytes replay: elapsed time 6.44 sec replay: replaying the execution... replay: successfully finished the replay replay: elapsed time 7.97 sec replay: replay overhead 23.86% PASS (14.67 s) Travis-CI: https://travis-ci.org/github/philmd/qemu/jobs/700787719 # gpg: Signature made Mon 22 Jun 2020 09:58:13 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/acceptance-testing-20200622: tests/acceptance: record/replay tests with advcal images tests/acceptance: add record/replay test for m68k tests/acceptance: add record/replay test for ppc64 tests/acceptance: add record/replay test for arm tests/acceptance: add record/replay test for aarch64 tests/acceptance: add kernel record/replay test for x86_64 tests/acceptance: add base class record/replay kernel tests MAINTAINERS: Add an entry to review Avocado based acceptance tests Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-22Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-to-apply-20200619-3' into staging This is a range of patches for RISC-V. Some key points are: - Generalise the CPU init functions - Support the SiFive revB machine - Improvements to the Hypervisor implementation and error checking - Connect some OpenTitan devices - Changes to the sifive_u machine to support U-boot v2: - Fix missing realise assert # gpg: Signature made Fri 19 Jun 2020 17:34:34 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20200619-3: (32 commits) hw/riscv: sifive_u: Add a dummy DDR memory controller device hw/riscv: sifive_u: Sort the SoC memmap table entries hw/riscv: sifive_u: Support different boot source per MSEL pin state hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 target/riscv: Rename IBEX CPU init routine hw/riscv: sifive_u: Add a new property msel for MSEL pin state hw/riscv: sifive_u: Rename serial property get/set functions to a generic name hw/riscv: sifive_u: Add reset functionality hw/riscv: sifive_gpio: Do not blindly trigger output IRQs hw/riscv: sifive_u: Hook a GPIO controller hw/riscv: sifive_gpio: Add a new 'ngpio' property hw/riscv: sifive_gpio: Clean up the codes hw/riscv: sifive_u: Generate device tree node for OTP hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions target/riscv: Use a smaller guess size for no-MMU PMP riscv/opentitan: Connect the UART device riscv/opentitan: Connect the PLIC device hw/intc: Initial commit of lowRISC Ibex PLIC ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-21tests/acceptance: record/replay tests with advcal imagesPavel Dovgalyuk
This patch adds more record/replay tests with kernel images. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Tested-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <159073592589.20809.5156301499042635614.stgit@pasha-ThinkPad-X280> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> [PMD: Use os.path.join(), add avocado 'cpu' tags] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-06-21tests/acceptance: add record/replay test for m68kPavel Dovgalyuk
This patch adds a test for record/replay of the kernel image boot for m68k platform. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Tested-by: Philippe Mathieu-Daude <philmd@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <159073592033.20809.1838967871297177313.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-06-21tests/acceptance: add record/replay test for ppc64Pavel Dovgalyuk
This patch adds a test for record/replay of the kernel image boot for ppc64 platform. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Tested-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <159073591363.20809.15658672985367330140.stgit@pasha-ThinkPad-X280> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-06-21tests/acceptance: add record/replay test for armPavel Dovgalyuk
This patch adds a test for record/replay of the kernel image boot for two different arm platforms. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Tested-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <159073590785.20809.17654573764167037499.stgit@pasha-ThinkPad-X280> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-06-21tests/acceptance: add record/replay test for aarch64Pavel Dovgalyuk
This patch adds a test for record/replay of the kernel image boot for aarch64 platform. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Tested-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <159073590231.20809.9842179251741585482.stgit@pasha-ThinkPad-X280> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-06-21tests/acceptance: add kernel record/replay test for x86_64Pavel Dovgalyuk
This patch adds a test for record/replay an execution of x86_64 machine. Execution scenario includes simple kernel boot, which allows testing basic hardware interaction in RR mode. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Tested-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <159073589656.20809.14010247947948822435.stgit@pasha-ThinkPad-X280> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> [PMD: Skip test_x86_64_pc on Travis-CI] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-06-21tests/acceptance: add base class record/replay kernel testsPavel Dovgalyuk
This patch adds a base for testing kernel boot recording and replaying. Each test has the phase of recording and phase of replaying. Virtual machines just boot the kernel and do not interact with the network. Structure and image links for the tests are borrowed from boot_linux_console.py Testing controls the message pattern at the end of the kernel boot for both record and replay modes. In replay mode QEMU is also intended to finish the execution automatically. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgaluk@ispras.ru> Tested-by: Philippe Mathieu-Daude <philmd@redhat.com> Message-Id: <159073589099.20809.14078431743098373301.stgit@pasha-ThinkPad-X280> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> [PMD: Keep imports sorted alphabetically] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-06-21MAINTAINERS: Add an entry to review Avocado based acceptance testsPhilippe Mathieu-Daudé
Acceptance tests can test any piece of the QEMU codebase. As such, the directory holding them does not belong to a specific subsystem with designated maintainers. Each subsystem covered by a test is welcomed to add the test path to its section. See for example commits 71b290e70, b11785ca2 or 5d480ddde. Add an entry for to allow reviewers to be notified when acceptance / integration tests are added or modified. The designated reviewers are not maintainers, subsystem maintainers are expected to merge their tests. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: Cleber Rosa <crosa@redhat.com> Message-Id: <20200129212345.20547-30-philmd@redhat.com> Message-Id: <20200605165656.17578-1-philmd@redhat.com>
2020-06-19Merge remote-tracking branch ↵Peter Maydell
'remotes/kraxel/tags/audio-20200619-pull-request' into staging audio: bugfixes for jack backend and gus emulation. # gpg: Signature made Fri 19 Jun 2020 14:17:22 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/audio-20200619-pull-request: hw/audio/gus: Fix registers 32-bit access audio/jack: simplify the re-init code path audio/jack: honour the enable state of the audio device audio/jack: do not remove ports when finishing audio/jack: remove invalid set of input support bool audio/jack: remove unused stopped state audio/jack: fix invalid minimum buffer size check Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-19qht: Fix threshold rate calculationRichard Henderson
tests/qht-bench.c:287:29: error: implicit conversion from 'unsigned long' to 'double' changes value from 18446744073709551615 to 18446744073709551616 [-Werror,-Wimplicit-int-float-conversion] *threshold = rate * UINT64_MAX; ~ ^~~~~~~~~~ Fix this by splitting the 64-bit constant into two halves, each of which is individually perfectly representable, the sum of which produces the correct arithmetic result. This is very likely just a sticking plaster over some underlying incorrect code, but it will suppress the warning for the moment. Cc: Emilio G. Cota <cota@braap.org> Reported-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng
It is enough to simply map the SiFive FU540 DDR memory controller into the MMIO space using create_unimplemented_device(), to make the upstream U-Boot v2020.07 DDR memory initialization codes happy. Note we do not generate device tree fragment for the DDR memory controller. Since the controller data in device tree consumes a very large space (see fu540-hifive-unleashed-a00-ddr.dtsi in the U-Boot source), and it is only needed by U-Boot SPL but not any operating system, we choose not to generate the fragment here. This also means when testing with U-Boot SPL, the device tree has to come from U-Boot SPL itself, but not the one generated by QEMU on the fly. The memory has to be set to 8GiB to match the real HiFive Unleashed board when invoking QEMU (-m 8G). With this commit, QEMU can boot U-Boot SPL built for SiFive FU540 all the way up to loading U-Boot proper from MMC: $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800) Trying to boot from MMC1 Unhandled exception: Load access fault EPC: 0000000008009be6 TVAL: 0000000010050014 The above exception is expected because QSPI is unsupported yet. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-6-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng
Move the flash and DRAM to the end of the SoC memmap table. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-5-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng
SiFive FU540 SoC supports booting from several sources, which are controlled using the Mode Select (MSEL[3:0]) pins on the chip. Typically, the boot process runs through several stages before it begins execution of user-provided programs. The SoC supports booting from memory-mapped QSPI flash, which is how start_in_flash property is used for at present. This matches MSEL = 1 configuration (QSPI0). Typical booting flows involve the Zeroth Stage Boot Loader (ZSBL). It's not necessary for QEMU to implement the full ZSBL ROM codes, because we know ZSBL downloads the next stage program into the L2 LIM at address 0x8000000 and executes from there. We can bypass the whole ZSBL execution and use "-bios" to load the next stage program directly if MSEL indicates a ZSBL booting flow. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-4-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng
Per the SiFive manual, all E/U series CPU cores' reset vector is at 0x1004. Update our codes to match the hardware. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19target/riscv: Rename IBEX CPU init routineBin Meng
Current IBEX CPU init routine name seems to be too generic. Since it uses a different reset vector from the generic one, it merits a dedicated name. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-2-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng
On SiFive FU540 SoC, the value stored at physical address 0x1000 stores the MSEL pin state that is used to control the next boot location that ROM codes jump to. Add a new property msel to sifive_u machine for this. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-12-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-12-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng
In prepration to add more properties to this machine, rename the existing serial property get/set functions to a generic name. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-11-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-11-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_u: Add reset functionalityBin Meng
The HiFive Unleashed board wires GPIO pin#10 to the input of the system reset signal. Let's set up the GPIO pin#10 and insert a "gpio-restart" device tree node so that reboot is now functional with QEMU 'sifive_u' machine. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-10-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-10-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_gpio: Do not blindly trigger output IRQsBin Meng
At present the GPIO output IRQs are triggered each time any GPIO register is written. However this is not correct. We should only trigger the output IRQ when the pin is configured as output enable. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-9-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-9-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_u: Hook a GPIO controllerBin Meng
SiFive FU540 SoC integrates a GPIO controller with 16 GPIO lines. This hooks the exsiting SiFive GPIO model to the SoC, and adds its device tree data as well. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-8-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-8-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng
Add a new property to represent the number of GPIO pins supported by the GPIO controller. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-7-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-7-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_gpio: Clean up the codesBin Meng
Do various minor clean-ups to the exisiting codes for: - coding convention conformance - remove unnecessary blank lines - spell SiFive correctly Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-6-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_u: Generate device tree node for OTPBin Meng
Upstream U-Boot v2020.07 codes switch to access SiFive FU540 OTP based on device tree information. Let's generate the device tree node for OTP. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-5-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-5-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng
There is no need to retrieve all PLIC IRQ information in order to just connect the GEM IRQ. Use qdev_get_gpio_in() directly like what is done for other peripherals. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-4-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-4-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng
This was done in the virt & sifive_u codes, but opentitan codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng
This was done in the virt & sifive_u codes, but sifive_e codes were missed. Remove the riscv_ prefix of the machine* and soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1591625864-31494-2-git-send-email-bmeng.cn@gmail.com Message-Id: <1591625864-31494-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-19target/riscv: Use a smaller guess size for no-MMU PMPAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-06-19riscv/opentitan: Connect the UART deviceAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-19riscv/opentitan: Connect the PLIC deviceAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-06-19hw/intc: Initial commit of lowRISC Ibex PLICAlistair Francis
The Ibex core contains a PLIC that although similar to the RISC-V spec is not RISC-V spec compliant. This patch implements a Ibex PLIC in a somewhat generic way. As the current RISC-V PLIC needs tidying up, my hope is that as the Ibex PLIC move towards spec compliance this PLIC implementation can be updated until it can replace the current PLIC. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2020-06-19hw/char: Initial commit of Ibex UARTAlistair Francis
This is the initial commit of the Ibex UART device. Serial TX is working, while RX has been implemeneted but untested. This is based on the documentation from: https://docs.opentitan.org/hw/ip/uart/doc/ Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
2020-06-19riscv/opentitan: Fix the ROM sizeAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reported-by: Damien Hedde <damien.hedde@greensocs.com>
2020-06-19target/riscv: Implement checks for hfenceAlistair Francis
Call the helper_hyp_tlb_flush() function on hfence instructions which will generate an illegal insruction execption if we don't have permission to flush the Hypervisor level TLBs. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-06-19target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis
Also correct the name of the VVMA instruction. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2020-06-19target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-14 07:10:08 +0000