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2021-05-04Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210503' ↵Peter Maydell
into staging Aspeed patches : * Fixes for the DMA space * New model for ASPEED's Hash and Crypto Engine (Joel and Klaus) * Acceptance tests (Joel) * A fix for the XDMA model * Some extra features for the SMC controller. * Two new boards : rainier-bmc and quanta-q7l1-bmc (Patrick) # gpg: Signature made Mon 03 May 2021 06:23:36 BST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20210503: aspeed: Add support for the quanta-q7l1-bmc board hw/block: m25p80: Add support for mt25ql02g and mt25qu02g aspeed: Add support for the rainier-bmc board aspeed: Deprecate the swift-bmc machine tests/qtest: Rename m25p80 test in aspeed_smc test aspeed/smc: Add extra controls to request DMA aspeed/smc: Add a 'features' attribute to the object class hw/misc/aspeed_xdma: Add AST2600 support tests/acceptance: Test ast2600 machine tests/acceptance: Test ast2400 and ast2500 machines tests/qtest: Add test for Aspeed HACE aspeed: Integrate HACE hw: Model ASPEED's Hash and Crypto Engine hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use alias aspeed/i2c: Rename DMA address space aspeed/i2c: Fix DMA address mask aspeed/smc: Remove unused "sdram-base" property aspeed/smc: Use the RAM memory region for DMAs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-04Merge remote-tracking branch 'remotes/bsdimp/tags/pull-bsd-user-20210430' ↵Peter Maydell
into staging bsd-user: start to cleanup the mess A number of small cleanups to get started. All the checkpatch.pl warnings for bsdload.c have been fixed, as well as a warning from qemu.h (though more remain and this patch series fails the format check still). I've also fixed a compile-time warning about a missing break. # gpg: Signature made Fri 30 Apr 2021 16:40:08 BST # gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100 # gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown] # gpg: aka "Warner Losh <imp@bsdimp.com>" [unknown] # gpg: aka "Warner Losh <imp@freebsd.org>" [unknown] # gpg: aka "Warner Losh <imp@village.org>" [unknown] # gpg: aka "Warner Losh <wlosh@bsdimp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100 * remotes/bsdimp/tags/pull-bsd-user-20210430: bsd-user: style tweak: Put {} around all if/else/for statements bsd-user: put back a break; that had gone missing... bsd-user: style tweak: return is not a function, eliminate () bsd-user: style tweak: keyword space ( bsd-user: whitespace changes Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-03Merge remote-tracking branch 'remotes/philmd/tags/mips-20210502' into stagingPeter Maydell
MIPS patches queue - Fix CACHEE opcode - Add missing CP0 checks to nanoMIPS RDPGPR / WRPGPR opcodes - Remove isa_get_irq() call in PIIX4 south bridge - Add various missing fields to the MIPS CPU migration vmstate - Lot of code moved around to allow TCG or KVM only builds - Restrict non-virtualized machines to TCG - Add KVM mips64el cross-build jobs to gitlab-ci # gpg: Signature made Sun 02 May 2021 15:56:51 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd/tags/mips-20210502: (36 commits) gitlab-ci: Add KVM mips64el cross-build jobs hw/mips: Restrict non-virtualized machines to TCG target/mips: Move TCG source files under tcg/ sub directory target/mips: Move CP0 helpers to sysemu/cp0.c target/mips: Move exception management code to exception.c target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c target/mips: Move helper_cache() to tcg/sysemu/special_helper.c target/mips: Move Special opcodes to tcg/sysemu/special_helper.c target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope target/mips: Move tlb_helper.c to tcg/sysemu/ target/mips: Restrict mmu_init() to TCG target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolder target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG target/mips: Move physical addressing code to sysemu/physaddr.c target/mips: Move sysemu specific files under sysemu/ subfolder target/mips: Move cpu_signal_handler definition around target/mips: Add simple user-mode mips_cpu_tlb_fill() target/mips: Add simple user-mode mips_cpu_do_interrupt() target/mips: Introduce tcg-internal.h for TCG specific declarations meson: Introduce meson_user_arch source set for arch-specific user-mode ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-02Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-hex-20210502' ↵Peter Maydell
into staging Minor cleanups. Finish the rest of the hexagon integer instructions. # gpg: Signature made Sun 02 May 2021 15:38:17 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-hex-20210502: (31 commits) Hexagon (target/hexagon) CABAC decode bin Hexagon (target/hexagon) load into shifted register instructions Hexagon (target/hexagon) load and unpack bytes instructions Hexagon (target/hexagon) bit reverse (brev) addressing Hexagon (target/hexagon) circular addressing Hexagon (target/hexagon) add A4_addp_c/A4_subp_c Hexagon (target/hexagon) add A6_vminub_RdP Hexagon (target/hexagon) add A5_ACS (vacsh) Hexagon (target/hexagon) add F2_sfinvsqrta Hexagon (target/hexagon) add F2_sfrecipa instruction Hexagon (target/hexagon) compile all debug code Hexagon (target/hexagon) move QEMU_GENERATE to only be on during macros.h Hexagon (target/hexagon) cleanup reg_field_info definition Hexagon (target/hexagon) cleanup ternary operators in semantics Hexagon (target/hexagon) use softfloat for float-to-int conversions Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn Hexagon (target/hexagon) use softfloat default NaN and tininess Hexagon (target/hexagon) change type of softfloat_roundingmodes Hexagon (target/hexagon) remove unused carry_from_add64 function Hexagon (target/hexagon) change variables from int to bool when appropriate ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-02gitlab-ci: Add KVM mips64el cross-build jobsPhilippe Mathieu-Daudé
Add a new job to cross-build the mips64el target without the TCG accelerator (IOW: only KVM accelerator enabled). Only build the mips64el target which is known to work and has users. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-31-f4bug@amsat.org>
2021-05-02hw/mips: Restrict non-virtualized machines to TCGPhilippe Mathieu-Daudé
Only the malta and loongson3-virt machines support KVM. Restrict the other machines to TCG: - mipssim - magnum - pica61 - fuloong2e - boston Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-30-f4bug@amsat.org>
2021-05-02target/mips: Move TCG source files under tcg/ sub directoryPhilippe Mathieu-Daudé
To ease maintenance, move all TCG specific files under the tcg/ sub-directory. Adapt the Meson machinery. The following prototypes: - mips_tcg_init() - mips_cpu_do_unaligned_access() - mips_cpu_do_transaction_failed() can now be restricted to the "tcg-internal.h" header. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-29-f4bug@amsat.org>
2021-05-02target/mips: Move CP0 helpers to sysemu/cp0.cPhilippe Mathieu-Daudé
Opcodes accessing Coprocessor 0 are privileged. Move the CP0 helpers to sysemu/ and simplify the #ifdef'ry. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-28-f4bug@amsat.org>
2021-05-02target/mips: Move exception management code to exception.cPhilippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-27-f4bug@amsat.org>
2021-05-02target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.cPhilippe Mathieu-Daudé
Move TLB management helpers to tcg/sysemu/tlb_helper.c. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-26-f4bug@amsat.org>
2021-05-02target/mips: Move helper_cache() to tcg/sysemu/special_helper.cPhilippe Mathieu-Daudé
Move helper_cache() to tcg/sysemu/special_helper.c. The CACHE opcode is privileged and is not accessible in user emulation. However we get a link failure when restricting the symbol to sysemu. For now, add a stub helper to satisfy linking, which abort if ever called. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-25-f4bug@amsat.org>
2021-05-02target/mips: Move Special opcodes to tcg/sysemu/special_helper.cPhilippe Mathieu-Daudé
Move the Special opcodes helpers to tcg/sysemu/special_helper.c. Since mips_io_recompile_replay_branch() is set as CPUClass::io_recompile_replay_branch handler in cpu.c, we need to declare its prototype in "tcg-internal.h". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-24-f4bug@amsat.org>
2021-05-02target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scopePhilippe Mathieu-Daudé
The 3 map_address() handlers are local to tlb_helper.c, no need to have their prototype declared publically. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-23-f4bug@amsat.org>
2021-05-02target/mips: Move tlb_helper.c to tcg/sysemu/Philippe Mathieu-Daudé
Move tlb_helper.c to the tcg/sysemu/ subdir, along with the following 3 declarations to tcg-internal.h: - cpu_mips_tlb_flush() - cpu_mips_translate_address() - r4k_invalidate_tlb() Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/ are only build when sysemu mode is configured. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-22-f4bug@amsat.org>
2021-05-02target/mips: Restrict mmu_init() to TCGPhilippe Mathieu-Daudé
mmu_init() is only required by TCG accelerator. Restrict its declaration and call to TCG. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-21-f4bug@amsat.org>
2021-05-02target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolderPhilippe Mathieu-Daudé
Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder, adapting the Meson machinery. Move the opcode definitions to tcg/sysemu_helper.h.inc. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-20-f4bug@amsat.org>
2021-05-02target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCGPhilippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-19-f4bug@amsat.org>
2021-05-02target/mips: Move physical addressing code to sysemu/physaddr.cPhilippe Mathieu-Daudé
Declare get_physical_address() with local scope and move it along with mips_cpu_get_phys_page_debug() to sysemu/physaddr.c new file. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-18-f4bug@amsat.org>
2021-05-02target/mips: Move sysemu specific files under sysemu/ subfolderPhilippe Mathieu-Daudé
Move sysemu-specific files under the new sysemu/ subfolder and adapt the Meson machinery. Update the KVM MIPS entry in MAINTAINERS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-17-f4bug@amsat.org>
2021-05-02target/mips: Move cpu_signal_handler definition aroundPhilippe Mathieu-Daudé
We have 2 blocks guarded with #ifdef for sysemu, which are simply separated by the cpu_signal_handler definition. To simplify the following commits which involve various changes in internal.h, first join the sysemu-guarded blocks. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-16-f4bug@amsat.org>
2021-05-02target/mips: Add simple user-mode mips_cpu_tlb_fill()Philippe Mathieu-Daudé
tlb_helper.c's #ifdef'ry hides a quite simple user-mode implementation of mips_cpu_tlb_fill(). Copy the user-mode implementation (without #ifdef'ry) to tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry. This will allow us to restrict tlb_helper.c to sysemu. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-15-f4bug@amsat.org>
2021-05-02target/mips: Add simple user-mode mips_cpu_do_interrupt()Philippe Mathieu-Daudé
The #ifdef'ry hides that the user-mode implementation of mips_cpu_do_interrupt() simply sets exception_index = EXCP_NONE. Add this simple implementation to tcg/user/tlb_helper.c, and the corresponding Meson machinery to build this file when user emulation is configured. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-14-f4bug@amsat.org>
2021-05-02target/mips: Introduce tcg-internal.h for TCG specific declarationsPhilippe Mathieu-Daudé
We will gradually move TCG-specific declarations to a new local header: "tcg-internal.h". To keep review simple, first add this header with 2 TCG prototypes, which we are going to move in the next 2 commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-13-f4bug@amsat.org>
2021-05-02meson: Introduce meson_user_arch source set for arch-specific user-modePhilippe Mathieu-Daudé
Similarly to the 'target_softmmu_arch' source set which allows to restrict target-specific sources to system emulation, add the equivalent 'target_user_arch' set for user emulation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-12-f4bug@amsat.org>
2021-05-02target/mips: Extract load/store helpers to ldst_helper.cPhilippe Mathieu-Daudé
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-11-f4bug@amsat.org>
2021-05-02target/mips: Merge do_translate_address into cpu_mips_translate_addressPhilippe Mathieu-Daudé
Currently cpu_mips_translate_address() calls raise_mmu_exception(), and do_translate_address() calls cpu_loop_exit_restore(). This API split is dangerous, we could call cpu_mips_translate_address without returning to the main loop. As there is only one caller, it is trivial (and safer) to merge do_translate_address() back to cpu_mips_translate_address(). Reported-by: Richard Henderson <richard.henderson@linaro.org> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-10-f4bug@amsat.org>
2021-05-02target/mips: Declare mips_env_set_pc() inlined in "internal.h"Philippe Mathieu-Daudé
Rename set_pc() as mips_env_set_pc(), declare it inlined and use it in cpu.c and op_helper.c. Reported-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210428170410.479308-9-f4bug@amsat.org>
2021-05-02target/mips: Turn printfpr() macro into a proper functionPhilippe Mathieu-Daudé
Turn printfpr() macro into a proper function: fpu_dump_fpr(). Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-8-f4bug@amsat.org>
2021-05-02target/mips: Restrict mips_cpu_dump_state() to cpu.cPhilippe Mathieu-Daudé
As mips_cpu_dump_state() is only used once to initialize the CPUClass::dump_state handler, we can move it to cpu.c to keep it symbol local. Beside, this handler is used by all accelerators, while the translate.c file targets TCG. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-7-f4bug@amsat.org>
2021-05-02target/mips: Optimize CPU/FPU regnames[] arraysPhilippe Mathieu-Daudé
Since all entries are no more than 4 bytes (including nul terminator), can save space and pie runtime relocations by declaring regnames[] as array of 4 const char. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-6-f4bug@amsat.org>
2021-05-02target/mips: Make CPU/FPU regnames[] arrays globalPhilippe Mathieu-Daudé
The CPU/FPU regnames[] arrays is used in mips_tcg_init() and mips_cpu_dump_state(), which while being in translate.c is not specific to TCG. To be able to move mips_cpu_dump_state() to cpu.c, which is compiled for all accelerator, we need to make the regnames[] arrays global to target/mips/ by declaring them in "internal.h". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-5-f4bug@amsat.org>
2021-05-02target/mips: Move msa_reset() to new source filePhilippe Mathieu-Daudé
mips_cpu_reset() is used by all accelerators, and calls msa_reset(), which is defined in msa_helper.c. Beside msa_reset(), the rest of msa_helper.c is only useful to the TCG accelerator. To be able to restrict this helper file to TCG, we need to move msa_reset() out of it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-4-f4bug@amsat.org>
2021-05-02target/mips: Move IEEE rounding mode array to new source filePhilippe Mathieu-Daudé
restore_msa_fp_status() is declared inlined in fpu_helper.h, and uses the ieee_rm[] array. Therefore any code calling restore_msa_fp_status() must have access to this ieee_rm[] array. kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c, calls restore_msa_fp_status. Except this tiny array, the rest of fpu_helper.c is only useful for the TCG accelerator. To be able to restrict fpu_helper.c to TCG, we need to move the ieee_rm[] array to a new source file. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-3-f4bug@amsat.org>
2021-05-02target/mips: Simplify meson TCG rulesPhilippe Mathieu-Daudé
We already have the mips_tcg_ss source set for TCG-specific files, use it for mxu_translate.c and tx79_translate.c to simplify a bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-2-f4bug@amsat.org>
2021-05-02target/mips: Make check_cp0_enabled() return a booleanPhilippe Mathieu-Daudé
To avoid callers to emit dead code if check_cp0_enabled() raise an exception, let it return a boolean value, whether CP0 is enabled or not. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210420193453.1913810-4-f4bug@amsat.org>
2021-05-02target/mips: Migrate missing CPU fieldsPhilippe Mathieu-Daudé
Add various missing fields to the CPU migration vmstate: - CP0_VPControl & CP0_GlobalNumber (01bc435b44b 2016-02-03) - CMGCRBase (c870e3f52ca 2016-03-15) - CP0_ErrCtl (0d74a222c27 2016-03-25) - MXU GPR[] & CR (eb5559f67dc 2018-10-18) - R5900 128-bit upper half (a168a796e1c 2019-01-17) This is a migration break. Fixes: 01bc435b44b ("target-mips: implement R6 multi-threading") Fixes: c870e3f52ca ("target-mips: add CMGCRBase register") Fixes: 0d74a222c27 ("target-mips: make ITC Configuration Tags accessible to the CPU") Fixes: eb5559f67dc ("target/mips: Introduce MXU registers") Fixes: a168a796e1c ("target/mips: Introduce 32 R5900 multimedia registers") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210423220044.3004195-1-f4bug@amsat.org>
2021-05-02target/mips: Remove spurious LOG_UNIMP of MTHC0 opcodePhilippe Mathieu-Daudé
When running with '-d unimp' all MTHC0 opcode executed are logged as unimplemented... Add the proper 'return' statement missed from commit 5204ea79ea7. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210422081055.2349216-1-f4bug@amsat.org>
2021-05-02target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodesPhilippe Mathieu-Daudé
Per the nanoMIPS32 Instruction Set Technical Reference Manual, Revision 01.01, Chapter 3. "Instruction Definitions": The Read/Write Previous GPR opcodes "require CP0 privilege". Add the missing CP0 checks. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210421185007.2231855-1-f4bug@amsat.org>
2021-05-02target/mips: Fix CACHEE opcode (CACHE using EVA addressing)Philippe Mathieu-Daudé
The CACHEE opcode "requires CP0 privilege". The pseudocode checks in the ISA manual is: if is_eva and not C0.Config5.EVA: raise exception('RI') if not IsCoprocessor0Enabled(): raise coprocessor_exception(0) Add the missing checks. Inspired-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210420175426.1875746-1-f4bug@amsat.org>
2021-05-02hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQPhilippe Mathieu-Daudé
Since commit 078778c5a55 ("piix4: Add an i8259 Interrupt Controller") the TYPE_PIIX4_PCI_DEVICE exposes the ISA input IRQs as "isa" alias. Use this alias to get IRQ for the power management PCI function. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210324182902.692419-1-f4bug@amsat.org>
2021-05-02Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210501' ↵Peter Maydell
into staging Include cleanups. Decodetree enhancements for power10. # gpg: Signature made Sat 01 May 2021 19:50:22 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210501: decodetree: Extend argument set syntax to allow types decodetree: Add support for 64-bit instructions decodetree: More use of f-strings decodetree: Introduce whex and whexC helpers exec: Remove accel/tcg/ from include paths Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-01Hexagon (target/hexagon) CABAC decode binTaylor Simpson
The following instruction is added S2_cabacdecbin Rdd32=decbin(Rss32,Rtt32) Test cases added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-27-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) load into shifted register instructionsTaylor Simpson
The following instructions are added L2_loadalignb_io Ryy32 = memb_fifo(Rs32+#s11:1) L2_loadalignh_io Ryy32 = memh_fifo(Rs32+#s11:1) L4_loadalignb_ur Ryy32 = memb_fifo(Rt32<<#u2+#U6) L4_loadalignh_ur Ryy32 = memh_fifo(Rt32<<#u2+#U6) L4_loadalignb_ap Ryy32 = memb_fifo(Re32=#U6) L4_loadalignh_ap Ryy32 = memh_fifo(Re32=#U6) L2_loadalignb_pr Ryy32 = memb_fifo(Rx32++Mu2) L2_loadalignh_pr Ryy32 = memh_fifo(Rx32++Mu2) L2_loadalignb_pbr Ryy32 = memb_fifo(Rx32++Mu2:brev) L2_loadalignh_pbr Ryy32 = memh_fifo(Rx32++Mu2:brev) L2_loadalignb_pi Ryy32 = memb_fifo(Rx32++#s4:1) L2_loadalignh_pi Ryy32 = memh_fifo(Rx32++#s4:1) L2_loadalignb_pci Ryy32 = memb_fifo(Rx32++#s4:1:circ(Mu2)) L2_loadalignh_pci Ryy32 = memh_fifo(Rx32++#s4:1:circ(Mu2)) L2_loadalignb_pcr Ryy32 = memb_fifo(Rx32++I:circ(Mu2)) L2_loadalignh_pcr Ryy32 = memh_fifo(Rx32++I:circ(Mu2)) Test cases in tests/tcg/hexagon/load_align.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-26-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) load and unpack bytes instructionsTaylor Simpson
The following instructions are added L2_loadbzw2_io Rd32 = memubh(Rs32+#s11:1) L2_loadbzw4_io Rdd32 = memubh(Rs32+#s11:1) L2_loadbsw2_io Rd32 = membh(Rs32+#s11:1) L2_loadbsw4_io Rdd32 = membh(Rs32+#s11:1) L4_loadbzw2_ur Rd32 = memubh(Rt32<<#u2+#U6) L4_loadbzw4_ur Rdd32 = memubh(Rt32<<#u2+#U6) L4_loadbsw2_ur Rd32 = membh(Rt32<<#u2+#U6) L4_loadbsw4_ur Rdd32 = membh(Rt32<<#u2+#U6) L4_loadbzw2_ap Rd32 = memubh(Re32=#U6) L4_loadbzw4_ap Rdd32 = memubh(Re32=#U6) L4_loadbsw2_ap Rd32 = membh(Re32=#U6) L4_loadbsw4_ap Rdd32 = membh(Re32=#U6) L2_loadbzw2_pr Rd32 = memubh(Rx32++Mu2) L2_loadbzw4_pr Rdd32 = memubh(Rx32++Mu2) L2_loadbsw2_pr Rd32 = membh(Rx32++Mu2) L2_loadbsw4_pr Rdd32 = membh(Rx32++Mu2) L2_loadbzw2_pbr Rd32 = memubh(Rx32++Mu2:brev) L2_loadbzw4_pbr Rdd32 = memubh(Rx32++Mu2:brev) L2_loadbsw2_pbr Rd32 = membh(Rx32++Mu2:brev) L2_loadbsw4_pbr Rdd32 = membh(Rx32++Mu2:brev) L2_loadbzw2_pi Rd32 = memubh(Rx32++#s4:1) L2_loadbzw4_pi Rdd32 = memubh(Rx32++#s4:1) L2_loadbsw2_pi Rd32 = membh(Rx32++#s4:1) L2_loadbsw4_pi Rdd32 = membh(Rx32++#s4:1) L2_loadbzw2_pci Rd32 = memubh(Rx32++#s4:1:circ(Mu2)) L2_loadbzw4_pci Rdd32 = memubh(Rx32++#s4:1:circ(Mu2)) L2_loadbsw2_pci Rd32 = membh(Rx32++#s4:1:circ(Mu2)) L2_loadbsw4_pci Rdd32 = membh(Rx32++#s4:1:circ(Mu2)) L2_loadbzw2_pcr Rd32 = memubh(Rx32++I:circ(Mu2)) L2_loadbzw4_pcr Rdd32 = memubh(Rx32++I:circ(Mu2)) L2_loadbsw2_pcr Rd32 = membh(Rx32++I:circ(Mu2)) L2_loadbsw4_pcr Rdd32 = membh(Rx32++I:circ(Mu2)) Test cases in tests/tcg/hexagon/load_unpack.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-25-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) bit reverse (brev) addressingTaylor Simpson
The following instructions are added L2_loadrub_pbr Rd32 = memub(Rx32++Mu2:brev) L2_loadrb_pbr Rd32 = memb(Rx32++Mu2:brev) L2_loadruh_pbr Rd32 = memuh(Rx32++Mu2:brev) L2_loadrh_pbr Rd32 = memh(Rx32++Mu2:brev) L2_loadri_pbr Rd32 = memw(Rx32++Mu2:brev) L2_loadrd_pbr Rdd32 = memd(Rx32++Mu2:brev) S2_storerb_pbr memb(Rx32++Mu2:brev).=.Rt32 S2_storerh_pbr memh(Rx32++Mu2:brev).=.Rt32 S2_storerf_pbr memh(Rx32++Mu2:brev).=.Rt.H32 S2_storeri_pbr memw(Rx32++Mu2:brev).=.Rt32 S2_storerd_pbr memd(Rx32++Mu2:brev).=.Rt32 S2_storerinew_pbr memw(Rx32++Mu2:brev).=.Nt8.new S2_storerbnew_pbr memw(Rx32++Mu2:brev).=.Nt8.new S2_storerhnew_pbr memw(Rx32++Mu2:brev).=.Nt8.new Test cases in tests/tcg/hexagon/brev.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-24-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01Hexagon (target/hexagon) circular addressingTaylor Simpson
The following instructions are added L2_loadrub_pci Rd32 = memub(Rx32++#s4:0:circ(Mu2)) L2_loadrb_pci Rd32 = memb(Rx32++#s4:0:circ(Mu2)) L2_loadruh_pci Rd32 = memuh(Rx32++#s4:1:circ(Mu2)) L2_loadrh_pci Rd32 = memh(Rx32++#s4:1:circ(Mu2)) L2_loadri_pci Rd32 = memw(Rx32++#s4:2:circ(Mu2)) L2_loadrd_pci Rdd32 = memd(Rx32++#s4:3:circ(Mu2)) S2_storerb_pci memb(Rx32++#s4:0:circ(Mu2)) = Rt32 S2_storerh_pci memh(Rx32++#s4:1:circ(Mu2)) = Rt32 S2_storerf_pci memh(Rx32++#s4:1:circ(Mu2)) = Rt.H32 S2_storeri_pci memw(Rx32++#s4:2:circ(Mu2)) = Rt32 S2_storerd_pci memd(Rx32++#s4:3:circ(Mu2)) = Rtt32 S2_storerbnew_pci memb(Rx32++#s4:0:circ(Mu2)) = Nt8.new S2_storerhnew_pci memw(Rx32++#s4:1:circ(Mu2)) = Nt8.new S2_storerinew_pci memw(Rx32++#s4:2:circ(Mu2)) = Nt8.new L2_loadrub_pcr Rd32 = memub(Rx32++I:circ(Mu2)) L2_loadrb_pcr Rd32 = memb(Rx32++I:circ(Mu2)) L2_loadruh_pcr Rd32 = memuh(Rx32++I:circ(Mu2)) L2_loadrh_pcr Rd32 = memh(Rx32++I:circ(Mu2)) L2_loadri_pcr Rd32 = memw(Rx32++I:circ(Mu2)) L2_loadrd_pcr Rdd32 = memd(Rx32++I:circ(Mu2)) S2_storerb_pcr memb(Rx32++I:circ(Mu2)) = Rt32 S2_storerh_pcr memh(Rx32++I:circ(Mu2)) = Rt32 S2_storerf_pcr memh(Rx32++I:circ(Mu2)) = Rt32.H32 S2_storeri_pcr memw(Rx32++I:circ(Mu2)) = Rt32 S2_storerd_pcr memd(Rx32++I:circ(Mu2)) = Rtt32 S2_storerbnew_pcr memb(Rx32++I:circ(Mu2)) = Nt8.new S2_storerhnew_pcr memh(Rx32++I:circ(Mu2)) = Nt8.new S2_storerinew_pcr memw(Rx32++I:circ(Mu2)) = Nt8.new Test cases in tests/tcg/hexagon/circ.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1617930474-31979-23-git-send-email-tsimpson@quicinc.com> [rth: Squash <1619667142-29636-1-git-send-email-tsimpson@quicinc.com> removing gen_read_reg and gen_set_byte to avoid clang Werror.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01decodetree: Extend argument set syntax to allow typesRichard Henderson
Rather than force all structure members to be 'int', allow the type of the member to be specified. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01decodetree: Add support for 64-bit instructionsLuis Fernando Fujita Pires
Allow '64' to be specified for the instruction width command line params and use the appropriate extract and deposit functions in that case. This will be used to implement the new 64-bit Power ISA 3.1 instructions. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Message-Id: <CP2PR80MB3668E123E2EFDB0ACD3A46F1DA759@CP2PR80MB3668.lamprd80.prod.outlook.com> [rth: Drop the change to the field type; use bitop_width instead of separate variables for extract/deposit; use "ull" for 64-bit constants.] Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01decodetree: More use of f-stringsRichard Henderson
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01decodetree: Introduce whex and whexC helpersRichard Henderson
Form a hex constant of the appropriate insnwidth. Begin using f-strings on changed lines. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-03 16:22:53 +0000