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2024-08-20hw/ppc/Kconfig: Add missing SERIAL_ISA dependency to POWERNV machineBernhard Beschow
The machine calls serial_hds_isa_init() which is provided by serial-isa.c, guarded by SERIAL_ISA. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240814181534.218964-4-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-08-20target/sparc: Restrict STQF to sparcv9Richard Henderson
Prior to sparcv9, the same encoding was STDFQ. Cc: qemu-stable@nongnu.org Fixes: 06c060d9e5b ("target/sparc: Move simple fp load/store to decodetree") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240816072311.353234-2-richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-08-20contrib/plugins/execlog: Fix shadowed declaration warningPierrick Bouvier
Found on debian stable. ../contrib/plugins/execlog.c: In function ‘vcpu_tb_trans’: ../contrib/plugins/execlog.c:236:22: error: declaration of ‘n’ shadows a previous local [-Werror=shadow=local] 236 | for (int n = 0; n < all_reg_names->len; n++) { | ^ ../contrib/plugins/execlog.c:184:12: note: shadowed declaration is here 184 | size_t n = qemu_plugin_tb_n_insns(tb); | Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240814233645.944327-2-pierrick.bouvier@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-08-20tests/avocado: Mark ppc_hv_tests.py as non-flaky after fixed console interactionNicholas Piggin
Now that exec_command doesn't incorrectly consume console output, and guest time is set correctly, ppc_hv_tests.py is working more reliably. Try marking it non-flaky. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-ID: <20240805232814.267843-3-npiggin@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-08-20tests/avocado: exec_command should not consume console outputNicholas Piggin
_console_interaction reads data from the console even when there is only an input string to send, and no output data to wait on. This can cause lines to be missed by wait_for_console_pattern calls that follows an exec_command. Fix this by not reading the console if there is no pattern to wait for. This solves occasional hangs in ppc_hv_tests.py, usually when run on KVM hosts that are fast enough to output important lines quickly enough to be consumed by exec_command, so they get missed by subsequent wait for pattern calls. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240805232814.267843-2-npiggin@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-08-20linux-user/mips: Select Loongson CPU for Loongson binariesPhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240814133928.6746-5-philmd@linaro.org>
2024-08-20linux-user/mips: Select MIPS64R2-generic for Rel2 binariesPhilippe Mathieu-Daudé
Cc: YunQiang Su <syq@debian.org> Reported-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240814133928.6746-4-philmd@linaro.org>
2024-08-20linux-user/mips: Select Octeon68XX CPU for Octeon binariesPhilippe Mathieu-Daudé
The Octeon68XX CPU is available since commit 9a6046a655 ("target/mips: introduce Cavium Octeon CPU model"). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1722 Reported-by: Johnathan Hữu Trí <nhtri2003@gmail.com> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240814133928.6746-3-philmd@linaro.org>
2024-08-20linux-user/mips: Do not try to use removed R5900 CPUPhilippe Mathieu-Daudé
R5900 emulation was removed in commit 823f2897bd. Remove it from ELF parsing in order to avoid: $ qemu-mipsn32 ./test5900 qemu-mipsn32: unable to find CPU model 'R5900' This reverts commit 4d9e5a0eb7df6e98ac6cf5e16029f35dd05b9537. Fixes: 823f2897bd ("target/mips: Disable R5900 support") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240814133928.6746-2-philmd@linaro.org>
2024-08-20hw/remote/message.c: Don't directly invoke DeviceClass:resetPeter Maydell
Directly invoking the DeviceClass::reset method is a bad idea, because if the device is using three-phase reset then it relies on transitional reset machinery which is likely to disappear at some point. Reset the device in the standard way, by calling device_cold_reset(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240813165250.2717650-7-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-08-20hw/dma/xilinx_axidma: Use semicolon at end of statement, not commaPeter Maydell
In axidma_class_init() we accidentally used a comma at the end of a statement rather than a semicolon. This has no ill effects, but it's obviously not intended and it means that Coccinelle scripts for instance will fail to match on the two statements. Use a semicolon instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240813165250.2717650-6-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-08-20target/mips: Load PTE as DATAPhilippe Mathieu-Daudé
PTE is not CODE so load it as normal DATA access. Fixes: 074cfcb4da ("Implement hardware page table walker for MIPS32") Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240814090452.2591-4-philmd@linaro.org>
2024-08-20target/mips: Use correct MMU index in get_pte()Philippe Mathieu-Daudé
When refactoring page_table_walk_refill() in commit 4e999bf419 we missed the indirect call to cpu_mmu_index() in get_pte(): page_table_walk_refill() -> get_pte() -> cpu_ld[lq]_code() -> cpu_mmu_index() Since we don't mask anymore the modes in hflags, cpu_mmu_index() can return UM or SM, while we only expect KM or ERL. Fix by propagating ptw_mmu_idx to get_pte(), and use the cpu_ld/st_code_mmu() API with the correct MemOpIdx. Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Reported-by: Waldemar Brodkorb <wbx@uclibc-ng.org> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2470 Fixes: 4e999bf419 ("target/mips: Pass ptw_mmu_idx down from mips_cpu_tlb_fill") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240814090452.2591-3-philmd@linaro.org>
2024-08-20target/mips: Pass page table entry size as MemOp to get_pte()Philippe Mathieu-Daudé
In order to simplify the next commit, pass the PTE size as MemOp. Rename: native_shift -> native_op directory_shift -> directory_mop leaf_shift -> leaf_mop Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240814090452.2591-2-philmd@linaro.org>
2024-08-20qemu-options.hx: correct formatting -smbios type=4Heinrich Schuchardt
processor-family and processor-id can be assigned independently. Add missing brackets. Fixes: b5831d79671c ("smbios: add processor-family option") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240729204816.11905-1-heinrich.schuchardt@canonical.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-08-20hw/mips/loongson3_virt: Fix condition of IPI IOCSR connectionJiaxun Yang
>>> CID 1547264: Null pointer dereferences (REVERSE_INULL) >>> Null-checking "ipi" suggests that it may be null, but it has already been dereferenced on all paths leading to the check. Resolves: Coverity CID 1547264 Link: https://lore.kernel.org/qemu-devel/752417ad-ab72-4fed-8d1f-af41f15bc225@app.fastmail.com/ Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240621-loongson3-ipi-follow-v2-2-848eafcbb67e@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-08-20hw/mips/loongson3_virt: Store core_iocsr into LoongsonMachineStateJiaxun Yang
Link: https://lore.kernel.org/qemu-devel/972034d6-23b3-415a-b401-b8bc1cc515c9@linaro.org/ Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240621-loongson3-ipi-follow-v2-1-848eafcbb67e@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-08-16Merge tag 'pull-request-2024-08-16' of https://gitlab.com/thuth/qemu into ↵Richard Henderson
staging * Fix a potential build warning in the s390x target code * Check for the availability of __attribute__((gcc_struct)) on MSYS2 * Fix skipUnless decorators in Avocado tests * Add missing gtk-vnc package to the CI jobs # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAma+/YURHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbXdGhAAm5Dnm2y5WA3Cq4oFlFNvSbX41z9TKNoj # PbxeQdw2y+zMZ2C1KQX032uA2lL047SjuEv6ONLchWkQk8Dv8xukWlUXZjMr0zWi # HeVSpzGGJ2y8WzO+eN3sL1TDxs4Lhv3Wer/PZ8XFcIbZi3TWsYIJOxJ3sU7JLOOx # t6BJiBh52UKVmQ0XruZ/YPBQJVHJMqcbRI+GTGCfVTsFXDAXnn4dOpA60q6/JA1i # 1rUDSAjTY7y5rkon7PSP+JQindbD5i1IwUSG0b8jLFV5t9+DOX1Ot8l0DWSjOStP # 0GigoVtOuohv0fv5dZjaaZlynbkWzZqSaUiaRcp6Ksl4RUzYFvk9ViWrOT2Dp3H1 # G4OEk8XDOI74VpzCoxWDjNHkRFCNf+EcbbKrq0UW7JeBbQo8cW7a6SpHA2HhRO0D # ycg+BST3uEuIeU6oSZRwDfywJopWJawsqb3zEWLL3sn4ghCdYouNfVf5n24HaZpA # 1K0zQpNtNR1lv6LDWRehheC3KzKHARgFfOHrvBnuyTwxDtxboI3NfrPEZOPwZsZS # fkDWBG762ECbY6BLH1f/fqB3051qZnbau/i13f7WSl3nH/x52yz0UQFFHkVs2ljJ # eRj2tOA7moxSkpXB0f+prIk7ewv5+6BOO2zdzUz+xmloHHOIDjwwfzWppSuD2bRq # XVhd19De6Tg= # =Z9dn # -----END PGP SIGNATURE----- # gpg: Signature made Fri 16 Aug 2024 05:19:33 PM AEST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] * tag 'pull-request-2024-08-16' of https://gitlab.com/thuth/qemu: ci: refresh package lists with lcitool ci: add gtk-vnc to the deps tests/avocado: apply proper skipUnless decorator meson.build: Check for the availability of __attribute__((gcc_struct)) on MSYS2 target/s390x: fix build warning (gcc-12 -fsanitize=thread) Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-08-16ci: refresh package lists with lcitoolDaniel P. Berrangé
Refresh with the newly added gtk-vnc package Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-ID: <20240718094159.902024-3-berrange@redhat.com> [thuth: fixed conflicts in .gitlab-ci.d/cirrus/*.vars] Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-08-16ci: add gtk-vnc to the depsDaniel P. Berrangé
The gtk-vnc package is used by the vnc-display-test qtest program. Technically only gvnc is needed, but since we already pull in the gtk3 dep, it is harmless to depend on gtk-vnc. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240718094159.902024-2-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-08-16tests/avocado: apply proper skipUnless decoratorCleber Rosa
Commit 9b45cc993 added many cases of skipUnless for the sake of organizing flaky tests. But, Python decorators *must* follow what they decorate, so the newlines added should *not* exist there. Signed-off-by: Cleber Rosa <crosa@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-ID: <20240806173119.582857-3-crosa@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-08-16meson.build: Check for the availability of __attribute__((gcc_struct)) on MSYS2Thomas Huth
Since quite a while MSYS2 now supports Clang as a compiler, too. Unfortunately, this compiler is lacking the __attribute__((gcc_struct)) that we need for compiling on Windows. But since the compiler is available now, some people started to use it to compile QEMU on MSYS2, apparently ignoring the compiler warnings (see for example the ticket at https://gitlab.com/qemu-project/qemu/-/issues/2476 ). These builds are likely broken in a couple of spots, so let's make sure that we rather bail out early in the configuration phase instead of allowing the build to succeed with warnings. Message-ID: <20240815122719.727639-1-thuth@redhat.com> Tested-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-08-15target/s390x: fix build warning (gcc-12 -fsanitize=thread)Pierrick Bouvier
Found on debian stable. ../target/s390x/tcg/translate.c: In function ‘get_mem_index’: ../target/s390x/tcg/translate.c:398:1: error: control reaches end of non-void function [-Werror=return-type] 398 | } Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20240814224132.897098-4-pierrick.bouvier@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-08-15Update version for v9.1.0-rc2 releasev9.1.0-rc2Richard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-08-15Merge tag 'pull-lu-20240815' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson
linux-user: Preserve NULL hit in target_mmap subroutines # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAma9VDodHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/d+Af7B51RZ0KQGrOO/psY # UQZBYOa7WDLuv3cRdhPhXsRxs4bQtc4suF+2mrKQ5ODS6gh2SRJqMFqmlNvzF1QP # k0D7qia3pfzsQ2YZjWq0ccZC0WSEbvABConulNydZR2tSORLXZSPmj8h0bWQjDnO # fGVY0I1DdRCWjpfcy12PDo7F+uNKYacQUcrkPl9XvBJe8Ev9vCWqgGMU/rINKFSF # +Z3YNpcF8tqeGvp72/Kr20XHtlX7XGz4OLgsBjnG897UVRV1UMdIRP7fd7Y9BJaZ # YgCAjfJrgEWvUd5ICQvkX03xOfZ1Nx3iRS7rIgPJxdN0svgzPGQyrqi9O9TUsFWD # 0eJdeQ== # =nOnV # -----END PGP SIGNATURE----- # gpg: Signature made Thu 15 Aug 2024 11:04:58 AM AEST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [ultimate] * tag 'pull-lu-20240815' of https://gitlab.com/rth7680/qemu: linux-user: Preserve NULL hit in target_mmap subroutines Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-08-15linux-user: Preserve NULL hit in target_mmap subroutinesRichard Henderson
Do not pass guest_base to the host mmap instead of zero hint. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2353 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-08-15Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
* fix RAPL computations # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAma83sIUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroO4OAf/SCiETP35wStOQ1MDfQoW9BUltlyS # 0bHJ9fiVPUs8iVXoUOY83P33dBYLpkAutmdw38pxD9JDH99wM5e4Etgks1GxLjtj # aDWMyxskguVKxR0iT92jcM7kFZKYqzssIoXrPFq7cC4LYw9t5wOEUnPxRXBphlao # 1lLdkJlDzHsU/K+VSAdB81T/Og+E6BpcBZTLD9EONUvcqHSiGp65omNf+dPporkO # U2egOFqcbhH6+jdQoRwBeXvGnIny8nHLVyOEbZWygeZqfo2PWR5PQ3DqOR7sj5RT # w9DIxtkpMdHWT1D/+8etDnb3XWYRnZNLhK5B3w4HpZUcBecyxmcXj6nxXA== # =Uvzx # -----END PGP SIGNATURE----- # gpg: Signature made Thu 15 Aug 2024 02:43:46 AM AEST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: target/i386: Fix arguments for vmsr_read_thread_stat() Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-08-14target/i386: Fix arguments for vmsr_read_thread_stat()Anthony Harivel
Snapshot of the stat utime and stime for each thread, taken before and after the pause, must be stored in separate locations Signed-off-by: Anthony Harivel <aharivel@redhat.com> Link: https://lore.kernel.org/r/20240807124320.1741124-2-aharivel@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-08-14Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson
* fix --static compilation of hexagon * fix incorrect application of REX to MMX operands * fix crash on module load * update Italian translation # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAma7kZ4UHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOy7QgAriuxfgw3Yvu9UPPfEZT5V9p5XfDf # LceO3C6OABIkFoGSO8WK5dWfQy3oYbrwEXX/l/PW1lUc2DFrSUo9YtIfjelRkxoC # 0EAAbV5A+xCLYmujFqBSe/6usRj82uKjSET1KK1aCam7ONZLNZf2yb4OwdShvLSN # MPgtBOrwznR1qh3KJtLB6YSRC0Rie1hOxbXFpx1AklXYnIiqUdMjXOHSjs+Amva0 # VczuqwjtVdNDTPqbZlCXatPtZ8nwYeEOD2jOqgjAoEwwabZ1fFGDCNXlqEDLSdTm # Cc+IZPYU5a8+tVfH0DYEMgMSkRhDUqVZ/076L+pRi+Q8ClxWV8fKsf5qKw== # =jJtu # -----END PGP SIGNATURE----- # gpg: Signature made Wed 14 Aug 2024 03:02:22 AM AEST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: po: update Italian translation module: Prevent crash by resetting local_err in module_load_qom_all() target/i386: Assert MMX and XMM registers in range target/i386: Use unit not type in decode_modrm target/i386: Do not apply REX to MMX operands target/hexagon: don't look for static glib Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-08-14Merge tag 'pull-target-arm-20240813' of ↵Richard Henderson
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values * target/arm: Clear high SVE elements in handle_vec_simd_wshli * target/arm: Fix usage of MMU indexes when EL3 is AArch32 # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAma7eSIZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3gbJEACHhZAvP4f1vic8DNGPw8Yr # v+pRQON+vF+PDBSyNkYCRL5Gy1P257Aujw1ed2dpoDhMemC/co67W2zdzToCvDd5 # XZxlHb/iUCTeZbA/Zp66ZADlvVOdvvQL8EHbd4mSBEZp9rvPSmxatx4I5jstLiAV # 5HimP+AjjGMfklMu+RelW7A7WDRJ0h7F4PwXCA8tLeHPH5XHSkweGYt3OVfSlUAs # +RKiltByC/quujLHxrQcVtLZON1KKiB0P8VPRcaR1QIFARiR1IfLvzhKVpqyOlnV # 3a+ZILtCJE1YEM+h7Aunz/l9MQ0DZe5DzbIdKOQ7NUkerlhq81kriPp67yLv25lk # zgqkHGGDEnIGpSXdmbXTNLcGlH+5O+fWl2RMzYrSFJqvwyRu9egLLi6E0xaNCRvY # gdb6CGPhhu21C1o5Nax0CiaZe3vzzRvC5QsIJ0yww6y7VaGFVt/XRaKBdLHB97nZ # t/9ifa3fmhVEW6pQEy8VdAeFoxIT2lJ2xJgBdMwpZCJlCxB8xKU/rZfrXKS/UUqV # 9Klbcfrx1WFT7zrAWS0Ig7nPttJ+XgjYfgHI3q2e80F6xRmAmaAjnbtVRS+L3It9 # eZ4SmuzurWipRLpdmxdOX1IXdZD9rJMzk9IUIZoklctlR/D+75Iuy0N7gY8G2dbp # fmh38lEQZ0IC90VmNtWltw== # =So/3 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 14 Aug 2024 01:17:54 AM AEST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] * tag 'pull-target-arm-20240813' of https://git.linaro.org/people/pmaydell/qemu-arm: target/arm: Fix usage of MMU indexes when EL3 is AArch32 target/arm: Update translation regime comment for new features target/arm: Clear high SVE elements in handle_vec_simd_wshli hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-08-13po: update Italian translationPaolo Bonzini
Reported-by: bovirus <https://gitlab.com/bovirus> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2451 Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-08-13module: Prevent crash by resetting local_err in module_load_qom_all()Alexander Ivanov
Set local_err to NULL after it has been freed in error_report_err(). This avoids triggering assert(*errp == NULL) failure in error_setv() when local_err is reused in the loop. Signed-off-by: Alexander Ivanov <alexander.ivanov@virtuozzo.com> Reviewed-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Denis V. Lunev <den@openvz.org> Link: https://lore.kernel.org/r/20240809121340.992049-2-alexander.ivanov@virtuozzo.com [Do the same by moving the declaration instead. - Paolo] Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-08-13target/i386: Assert MMX and XMM registers in rangeRichard Henderson
The mmx assert would fire without the fix for #2495. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20240812025844.58956-4-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-08-13target/arm: Fix usage of MMU indexes when EL3 is AArch32Peter Maydell
Our current usage of MMU indexes when EL3 is AArch32 is confused. Architecturally, when EL3 is AArch32, all Secure code runs under the Secure PL1&0 translation regime: * code at EL3, which might be Mon, or SVC, or any of the other privileged modes (PL1) * code at EL0 (Secure PL0) This is different from when EL3 is AArch64, in which case EL3 is its own translation regime, and EL1 and EL0 (whether AArch32 or AArch64) have their own regime. We claimed to be mapping Secure PL1 to our ARMMMUIdx_EL3, but didn't do anything special about Secure PL0, which meant it used the same ARMMMUIdx_EL10_0 that NonSecure PL0 does. This resulted in a bug where arm_sctlr() incorrectly picked the NonSecure SCTLR as the controlling register when in Secure PL0, which meant we were spuriously generating alignment faults because we were looking at the wrong SCTLR control bits. The use of ARMMMUIdx_EL3 for Secure PL1 also resulted in the bug that we wouldn't honour the PAN bit for Secure PL1, because there's no equivalent _PAN mmu index for it. We could fix this in one of two ways: * The most straightforward is to add new MMU indexes EL30_0, EL30_3, EL30_3_PAN to correspond to "Secure PL1&0 at PL0", "Secure PL1&0 at PL1", and "Secure PL1&0 at PL1 with PAN". This matches how we use indexes for the AArch64 regimes, and preserves propirties like being able to determine the privilege level from an MMU index without any other information. However it would add two MMU indexes (we can share one with ARMMMUIdx_EL3), and we are already using 14 of the 16 the core TLB code permits. * The more complicated approach is the one we take here. We use the same MMU indexes (E10_0, E10_1, E10_1_PAN) for Secure PL1&0 than we do for NonSecure PL1&0. This saves on MMU indexes, but means we need to check in some places whether we're in the Secure PL1&0 regime or not before we interpret an MMU index. The changes in this commit were created by auditing all the places where we use specific ARMMMUIdx_ values, and checking whether they needed to be changed to handle the new index value usage. Note for potential stable backports: taking also the previous (comment-change-only) commit might make the backport easier. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2326 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240809160430.1144805-3-peter.maydell@linaro.org
2024-08-13target/arm: Update translation regime comment for new featuresPeter Maydell
We have a long comment describing the Arm architectural translation regimes and how we map them to QEMU MMU indexes. This comment has got a bit out of date: * FEAT_SEL2 allows Secure EL2 and corresponding new regimes * FEAT_RME introduces Realm state and its translation regimes * We now model the Cortex-R52 so that is no longer a hypothetical * We separated Secure Stage 2 and NonSecure Stage 2 MMU indexes * We have an MMU index per physical address spacea Add the missing pieces so that the list of architectural translation regimes matches the Arm ARM, and the list and count of QEMU MMU indexes in the comment matches the enum. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240809160430.1144805-2-peter.maydell@linaro.org
2024-08-13target/arm: Clear high SVE elements in handle_vec_simd_wshliRichard Henderson
AdvSIMD instructions are supposed to zero bits beyond 128. Affects SSHLL, USHLL, SSHLL2, USHLL2. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240717060903.205098-15-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-08-13hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL valuesZheyu Ma
This commit adds validation checks for the MCOPRE and MCOSEL values in the rcc_update_cfgr_register function. If the MCOPRE value exceeds 0b100 or the MCOSEL value exceeds 0b111, an error is logged and the corresponding clock mux is disabled. This helps in identifying and handling invalid configurations in the RCC registers. Reproducer: cat << EOF | qemu-system-aarch64 -display \ none -machine accel=qtest, -m 512M -machine b-l475e-iot01a -qtest \ stdio writeq 0x40021008 0xffffffff EOF Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2356 Signed-off-by: Zheyu Ma <zheyuma97@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-08-13target/i386: Use unit not type in decode_modrmRichard Henderson
Rather that enumerating the types that can produce MMX operands, examine the unit. No functional change. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20240812025844.58956-3-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-08-13target/i386: Do not apply REX to MMX operandsRichard Henderson
Cc: qemu-stable@nongnu.org Fixes: b3e22b2318a ("target/i386: add core of new i386 decoder") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2495 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Link: https://lore.kernel.org/r/20240812025844.58956-2-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-08-13target/hexagon: don't look for static glibAlyssa Ross
When cross compiling QEMU configured with --static, I've been getting configure errors like the following: Build-time dependency glib-2.0 found: NO ../target/hexagon/meson.build:303:15: ERROR: Dependency lookup for glib-2.0 with method 'pkgconfig' failed: Could not generate libs for glib-2.0: Package libpcre2-8 was not found in the pkg-config search path. Perhaps you should add the directory containing `libpcre2-8.pc' to the PKG_CONFIG_PATH environment variable Package 'libpcre2-8', required by 'glib-2.0', not found This happens because --static sets the prefer_static Meson option, but my build machine doesn't have a static libpcre2. I don't think it makes sense to insist that native dependencies are static, just because I want the non-native QEMU binaries to be static. Signed-off-by: Alyssa Ross <hi@alyssa.is> Link: https://lore.kernel.org/r/20240805104921.4035256-1-hi@alyssa.is Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-08-13Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into stagingRichard Henderson
Pull request Fix for hosts with an older libblkio. # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAma6MIoACgkQnKSrs4Gr # c8i+7gf/Q1vTYE9U1ksbmASQGVJSyCfZlKB0fNxgsGgdnhcIF2uipSxNiDTVVAgn # rKfMXCvFrPQ7cjbKiiHe4Aj9GqjI6nY6vimnuxqxq9FCd1+RiGGZWDRBfS+6ZQjg # 815BFB7tkc7ejoL5plMk95XHM+2uHHV0xvK/zelrZ5VOeWdot0yUgL1QLMpAvzMQ # dY3pwarG8txlnTrMuE+Ig03hjkPf0Z6aK6kdaI5xn9G6O1+799NYXpjqKNtDbisc # Sf9iq5hmbfASECBBUJH9iWrLdgnieADPebRbOAmDpUsM1bGV6UW9KHUE7zC0h394 # jz8fSjMOjY03rDQjOpzV1wtR8zwpDw== # =Asvz # -----END PGP SIGNATURE----- # gpg: Signature made Tue 13 Aug 2024 01:55:54 AM AEST # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] * tag 'block-pull-request' of https://gitlab.com/stefanha/qemu: block/blkio: use FUA flag on write zeroes only if supported Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-08-13Merge tag 'pull-target-arm-20240812' of ↵Richard Henderson
https://git.linaro.org/people/pmaydell/qemu-arm into staging * Fix BTI versus CF_PCREL * include: Fix typo in name of MAKE_IDENTFIER macro * docs: Various txt-to-rST conversions * hw/core/ptimer: fix timer zero period condition for freq > 1GHz * arm/virt: place power button pin number on a define # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAma5+4wZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pX3D/9UVutdg5TsB9N8y5mPaVSn # Yx0awBgxK5SHWeVgQJBkSdqh6LiGhhukR3VHfNanDELq24s0uLqLW86thgj+iB0H # 51rnVHJtWtT9mIt0Qq9BlXX8+j0th6hELy/z+/aYdrWI1pmKsGYgF1gRh1vXrg+I # 0s/S7kZY5CNDBbTXoBNtJfbZRe8fzyy5gUqc/tnw6Qonp8XM1OeG6sg/qF0KwzbB # 8R7IvnY7gaBWm3daXqrFoxYuR+9i6F8uaFflOm+CarKQc9foH6KEzmfLAYLfGkFZ # 2ZVHg3uC4k4OicyrpYcWsgumNTzOj8RTI4kV7M8NAj5TXCr+0pO6lnhlAKVGTWiL # nJrW62dN56w8NVOzcy0tB0xqTHnKIxioGZyU4RDVKHjD/Fy0x7LX7KVmaBEZgyxJ # oA4zY4KOrCNFsXQlqZgx38v/1hshnIYFN7V5AmfGEfbbKpBznKBQKmuyJ9VwSfGT # jLwlwU4VMJPsj2Rs70seEl6obgyZicAXIAbqPgtMsvt3H2kKI2jtsNPFka3WaY62 # 0jOEbbFrsKV1//ZExBZdFhqBH/CoiZMvM4jsq1Y/oxAxIWtGv5dmJJsAA3w33YE4 # kNWXfHKAAhydZKeQloMgeOdLliP5UiCfF1FltwAWkLo59GV3TkjwagDU8+pWs9OF # plOKWaKDUzkHq6G197uaBA== # =ftoZ # -----END PGP SIGNATURE----- # gpg: Signature made Mon 12 Aug 2024 10:09:48 PM AEST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] * tag 'pull-target-arm-20240812' of https://git.linaro.org/people/pmaydell/qemu-arm: arm/virt: place power button pin number on a define hw/core/ptimer: fix timer zero period condition for freq > 1GHz docs: Typo fix in live disk backup docs/interop/prl-xml.rst: Fix minor grammar nits docs/interop/prl-xml.txt: Convert to rST docs/interop/parallels.txt: Convert to rST docs/interop/nbd.txt: Convert to rST docs/specs/rocker.txt: Convert to rST include: Fix typo in name of MAKE_IDENTFIER macro target/arm: Fix BTI versus CF_PCREL Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-08-12block/blkio: use FUA flag on write zeroes only if supportedStefano Garzarella
libblkio supports BLKIO_REQ_FUA with write zeros requests only since version 1.4.0, so let's inform the block layer that the blkio driver supports it only in this case. Otherwise we can have runtime errors as reported in https://issues.redhat.com/browse/RHEL-32878 Fixes: fd66dbd424 ("blkio: add libblkio block driver") Cc: qemu-stable@nongnu.org Buglink: https://issues.redhat.com/browse/RHEL-32878 Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240808080545.40744-1-sgarzare@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-08-12arm/virt: place power button pin number on a defineMauro Carvalho Chehab
Having magic numbers inside the code is not a good idea, as it is error-prone. So, instead, create a macro with the number definition. Link: https://lore.kernel.org/qemu-devel/CAFEAcA-PYnZ-32MRX+PgvzhnoAV80zBKMYg61j2f=oHaGfwSsg@mail.gmail.com/ Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: ef0e7f5fca6cd94eda415ecee670c3028c671b74.1723121692.git.mchehab+huawei@kernel.org Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-08-12hw/core/ptimer: fix timer zero period condition for freq > 1GHzJianzhou Yue
The real period is zero when both period and period_frac are zero. Check the method ptimer_set_freq, if freq is larger than 1000 MHz, the period is zero, but the period_frac is not, in this case, the ptimer will work but the current code incorrectly recognizes that the ptimer is disabled. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2306 Signed-off-by: JianZhou Yue <JianZhou.Yue@verisilicon.com> Message-id: 3DA024AEA8B57545AF1B3CAA37077D0FB75E82C8@SHASXM03.verisilicon.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-08-12Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into stagingRichard Henderson
# -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEIV1G9IJGaJ7HfzVi7wSWWzmNYhEFAma5uNkACgkQ7wSWWzmN # YhFpLwf+J9+cBWKUze7FZkxNHU78GJ/b+oVQfLYPnrCRrVKoyTr9yiKfMDS8qf5/ # tPd+xFABwcHb8UL3EeAe9w5aB0QCqqdmZMFRkWuaZ7HEbZkYNt9cJck5iMdNaPBm # cKiFRLb8FDVA3aegCcsBqnwCxgFW+3P3rrnHQz1C+GQAOm7FER+HiFnYucjrrLSM # SaXZYIH/LPqL01gbZcbixQkhgL5XFWUToFXQEYECGS07uZZ1WSJkxIP6WZDchJ4+ # vYO8/fWXVdrjvDirraZQRYnurWQGpTUk0Ocn2R8MaJsF8TK031MrMRJ3YP9zXp4n # wMe0BZO/YG5oi2gFrJpYL2AZqh2MgQ== # =DhS+ # -----END PGP SIGNATURE----- # gpg: Signature made Mon 12 Aug 2024 05:25:13 PM AEST # gpg: using RSA key 215D46F48246689EC77F3562EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * tag 'net-pull-request' of https://github.com/jasowang/qemu: net: Fix '-net nic,model=' for non-help arguments Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-08-12net: Fix '-net nic,model=' for non-help argumentsDavid Woodhouse
Oops, don't *delete* the model option when checking for 'help'. Fixes: 64f75f57f9d2 ("net: Reinstate '-net nic, model=help' output as documented in man page") Reported-by: Hans <sungdgdhtryrt@gmail.com> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Cc: qemu-stable@nongnu.org Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Jason Wang <jasowang@redhat.com>
2024-08-09docs: Typo fix in live disk backupEric Blake
Add in the missing space in the section header. Fixes: 1084159b31 ("qapi: deprecate drive-backup", v6.2.0) Signed-off-by: Eric Blake <eblake@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-08-09docs/interop/prl-xml.rst: Fix minor grammar nitsPeter Maydell
Fix some minor grammar nits in the prl-xml documentation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 20240801170131.3977807-6-peter.maydell@linaro.org
2024-08-09docs/interop/prl-xml.txt: Convert to rSTPeter Maydell
Convert prl-xml.txt to rST format. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 20240801170131.3977807-5-peter.maydell@linaro.org
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-25 02:15:58 +0000