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2024-07-26target/ppc/mmu_common.c: Remove single use local variableBALATON Zoltan
2024-07-26target/ppc/mmu_common.c: Remove single use local variableBALATON Zoltan
2024-07-26target/ppc/mmu_common.c: Remove local name for a constantBALATON Zoltan
2024-07-26target/ppc: Reorganise and rename ppc_hash32_pp_prot()BALATON Zoltan
2024-07-26target/ppc : Update VSX storage access insns to use tcg_gen_qemu _ld/st_i128.Chinmay Rath
2024-07-26target/ppc: Update VMX storage access insns to use tcg_gen_qemu_ld/st_i128.Chinmay Rath
2024-07-26target/ppc: Move get/set_avr64 functions to vmx-impl.c.inc.Chinmay Rath
2024-07-26target/ppc: Move VSX fp compare insns to decodetree.Chinmay Rath
2024-07-26target/ppc: Move VSX vector storage access insns to decodetree.Chinmay Rath
2024-07-26target/ppc: Move VSX vector with length storage access insns to decodetree.Chinmay Rath
2024-07-26target/ppc: Moving VSX scalar storage access insns to decodetree.Chinmay Rath
2024-07-26target/ppc: Move VSX logical instructions to decodetree.Chinmay Rath
2024-07-26target/ppc: Move VSX arithmetic and max/min insns to decodetree.Chinmay Rath
2024-07-26target/ppc: Move ISA300 flag check out of do_helper_XX3.Chinmay Rath
2024-07-26target/ppc: Improve VMX integer add/sub saturate instructions.Chinmay Rath
2024-07-26target/ppc: Move VMX integer add/sub saturate insns to decodetree.Chinmay Rath
2024-07-26pnv/xive2: Dump more END state with 'info pic'Frederic Barrat
2024-07-26pnv/xive2: Refine TIMA 'info pic' outputFrederic Barrat
2024-07-26pnv/xive2: Move xive2_nvp_pic_print_info() to xive2.cFrederic Barrat
2024-07-26pnv/xive2: Fail VST entry address computation if table has no VSDFrederic Barrat
2024-07-26pnv/xive2: Set Translation Table for the NVC port spaceFrederic Barrat
2024-07-26pnv/xive2: Enable VST NVG and NVC index compressionFrederic Barrat
2024-07-26pnv/xive2: Configure Virtualization Structure Tables through the PCFrederic Barrat
2024-07-26pnv/xive2: Add NVG and NVC to cache watch facilityFrederic Barrat
2024-07-26pnv/xive: Support cache flush and queue sync inject with notificationsNicholas Piggin
2024-07-26pnv/xive2: Structure/define alignment changesMichael Kowal
2024-07-26pnv/xive2: XIVE2 Cache Watch, Cache Flush and Sync Injection supportFrederic Barrat
2024-07-26tests/qtest: Add pnv-spi-seeprom qtestChalapathi V
2024-07-26hw/ppc: SPI controller wiring to P10 chipChalapathi V
2024-07-26hw/block: Add Microchip's 25CSM04 to m25p80Chalapathi V
2024-07-26hw/ssi: Extend SPI modelChalapathi V
2024-07-26hw/ssi: Add SPI modelChalapathi V
2024-07-26ppc/pnv: Remove ppc target dependency from pnv_xscom.hChalapathi V
2024-07-26ppc/pnv: Add an LPAR per core machine optionNicholas Piggin
2024-07-26ppc/pnv: Implement POWER10 PC xscom registers for direct controlsNicholas Piggin
2024-07-26ppc/pnv: Add a CPU nmi and resume functionNicholas Piggin
2024-07-26ppc/pnv: Add big-core machine propertyNicholas Piggin
2024-07-26ppc/pnv: Add POWER10 ChipTOD quirk for big-coreNicholas Piggin
2024-07-26ppc/pnv: Implement Power9 CPU core thread state indirect registerNicholas Piggin
2024-07-26ppc/pnv: Implement big-core PVR for Power9/10Nicholas Piggin
2024-07-26ppc/pnv: Add allow for big-core differences in DT generationNicholas Piggin
2024-07-26ppc/pnv: Add a big-core mode that joins two regular coresNicholas Piggin
2024-07-26ppc: Add has_smt_siblings property to CPUPPCStateNicholas Piggin
2024-07-26target/ppc: Add helpers to check for SMT sibling threadsNicholas Piggin
2024-07-26ppc: Add a core_index to CPUPPCState for SMT vCPUsNicholas Piggin
2024-07-26ppc/pnv: Extend chip_pir class method to TIR as wellNicholas Piggin
2024-07-26ppc/pnv: use class attribute to limit SMT threads for different machinesNicholas Piggin
2024-07-26target/ppc: Move SPR indirect registers into PnvCoreNicholas Piggin
2024-07-26ppc/pnv: Move timebase state into PnvCoreNicholas Piggin
2024-07-26ppc/pnv: Add pointer from PnvCPUState to PnvCoreNicholas Piggin
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