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2016-03-04hw/intc/arm_gic.c: Implement GICv2 GICC_DIRPeter Maydell
The GICv2 introduces a new CPU interface register GICC_DIR, which allows an OS to split the "priority drop" and "deactivate interrupt" parts of interrupt completion. Implement this register. (Note that the register is at offset 0x1000 in the CPU interface, which means it is on a different 4K page from all the other registers.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1456854176-7813-1-git-send-email-peter.maydell@linaro.org
2016-03-04arm: boot: Support big-endian elfsPeter Crosthwaite
Support ARM big-endian ELF files in system-mode emulation. When loading an elf, determine the endianness mode expected by the elf, and set the relevant CPU state accordingly. With this, big-endian modes are now fully supported via system-mode LE, so there is no need to restrict the elf loading to the TARGET endianness so the ifdeffery on TARGET_WORDS_BIGENDIAN goes away. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fix typo in comments] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04loader: Add data swap option to load-elfPeter Crosthwaite
Some CPUs are of an opposite data-endianness to other components in the system. Sometimes elfs have the data sections layed out with this CPU data-endianness accounting for when loaded via the CPU, so byte swaps (relative to other system components) will occur. The leading example, is ARM's BE32 mode, which is is basically LE with address manipulation on half-word and byte accesses to access the hw/byte reversed address. This means that word data is invariant across LE and BE32. This also means that instructions are still LE. The expectation is that the elf will be loaded via the CPU in this endianness scheme, which means the data in the elf is reversed at compile time. As QEMU loads via the system memory directly, rather than the CPU, we need a mechanism to reverse elf data endianness to implement this possibility. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04loader: load_elf(): Add doc commentPeter Crosthwaite
Document the usage of load_elf() for clarity on current features. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04loader: add API to load elf headerPeter Crosthwaite
Add an API to load an elf header header from a file. Populates a buffer with the header contents, as well as a boolean for whether the elf is 64b or not. Both arguments are optional. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: Fix typo in comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: implement BE32 mode in system emulationPaolo Bonzini
System emulation only has a little-endian target; BE32 mode is implemented by adjusting the low bits of the address for every byte and halfword load and store. 64-bit accesses flip the low and high words. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [PC changes: * rebased against master (Jan 2016) ] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: implement setendPaolo Bonzini
Since this is not a high-performance path, just use a helper to flip the E bit and force a lookup in the hash table since the flags have changed. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: introduce tbflag for endiannessPeter Crosthwaite
Introduce a tbflags for endianness, set based upon the CPUs current endianness. This in turn propagates through to the disas endianness flag. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: a64: Add endianness supportPeter Crosthwaite
Set the dc->mo_endianness flag for AA64 and use it in all ldst ops. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: introduce disas flag for endiannessPaolo Bonzini
Introduce a disas flag for setting the CPU data endianness. This allows control of the endianness from the CPU state rather than hard-coding it to TARGET_WORDS_BIGENDIAN. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [ PC changes: * Split off as new patch from original: "target-arm: introduce tbflag for CPSR.E" * Wrote commit message from scratch ] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: pass DisasContext to gen_aa32_ld*/st*Paolo Bonzini
We'll need the DisasContext in the next patch to retrieve the desired endianness, so pass it as a whole to gen_aa32_ld*/st*. Unfortunately we cannot let those functions call get_mem_index, because of user-mode load/store instructions. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [ PC changes: * Fix long lines ] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: implement SCTLR.EEPeter Crosthwaite
Implement SCTLR.EE bit which controls data endianess for exceptions and page table translations. SCTLR.EE is mirrored to the CPSR.E bit on exception entry. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04linux-user: arm: handle CPSR.E correctly in strex emulationPaolo Bonzini
Now that CPSR.E is set correctly, prepare for when setend will be able to change it; bswap data in and out of strex manually by comparing SCTLR.B, CPSR.E and TARGET_WORDS_BIGENDIAN (we do not have the luxury of using TCGMemOps). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [ PC changes: * Moved SCTLR/CPSR logic to arm_cpu_data_is_big_endian ] Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04linux-user: arm: set CPSR.E/SCTLR.E0E correctly for BE modePeter Crosthwaite
If doing big-endian linux-user mode, set both the CPSR.E and SCTLR.E0E bits. This sets big-endian mode for data accesses. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04arm: cpu: handle BE32 user-mode as BEPeter Crosthwaite
endian with address manipulations on subword accesses (to give the illusion of BE). But user-mode cannot tell the difference and is already implemented as straight BE. So handle the difference in the endianess query, where USER mode is BE and system is not. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: cpu: Move cpu_is_big_endian to headerPeter Crosthwaite
There is a CPU data endianness test that is used to drive the virtio_big_endian test. Move this up to the header so it can be more generally used for endian tests. The KVM specific cpu_syncronize_state call is left behind in the virtio specific function. Rename it arm_cpu-data_is_big_endian() to more accurately capture that this is for data accesses only. Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini
bswap_code is a CPU property of sorts ("is the iside endianness the opposite way round to TARGET_WORDS_BIGENDIAN?") but it is not the actual CPU state involved here which is SCTLR.B (set for BE32 binaries, clear for BE8). Replace bswap_code with SCTLR.B, and pass that to arm_ld*_code. The next patches will make data fetches honor both SCTLR.B and CPSR.E appropriately. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> [PC changes: * rebased on master (Jan 2016) * s/TARGET_USER_ONLY/CONFIG_USER_ONLY * Use bswap_code() for disas_set_info() instead of raw sctlr_b ] Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04linux-user: arm: pass env to get_user_code_*Paolo Bonzini
This matches the idiom used by get_user_data_* later in the series, and will help when bswap_code will be replaced by SCTLR.B. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04linux-user: arm: fix coding style for some linux-user signal functionsPaolo Bonzini
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04bcm2835_mbox/property: replace ldl_phys/stl_phys with endian-specific accessesAndrew Baumann
PMM pointed out that ldl_phys and stl_phys are dependent on the CPU's endianness, whereas device model code should be independent of it. This changes the relevant Raspberry Pi devices to explicitly call the little-endian variants. Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1456880233-22568-1-git-send-email-Andrew.Baumann@microsoft.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-04hw/arm/virt: Assume EL3 boot rom will handle PSCI if one is providedPeter Maydell
If the user passes us an EL3 boot rom, then it is going to want to implement the PSCI interface itself. In this case, disable QEMU's internal PSCI implementation so it does not get in the way, and instead start all CPUs in an SMP configuration at once (the boot rom will catch them all and pen up the secondaries until needed). The boot rom code is also responsible for editing the device tree to include any necessary information about its own PSCI implementation before eventually passing it to a NonSecure guest. (This "start all CPUs at once" approach is what both ARM Trusted Firmware and UEFI expect, since it is what the ARM Foundation Model does; the other approach would be to provide some emulated hardware for "start the secondaries" but this is simplest.) This is a compatibility break, but I don't believe that anybody was using a secure boot ROM with an SMP configuration. Such a setup would be somewhat broken since there was nothing preventing nonsecure guest code from calling the QEMU PSCI function to start up a secondary core in a way that completely bypassed the secure world. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Message-id: 1456853976-7592-1-git-send-email-peter.maydell@linaro.org
2016-03-04hw/arm/virt: Make first flash device Secure-only if booting securePeter Maydell
If the virt board is started with the 'secure' property set to request a Secure setup, then make the first flash device be visible only to the Secure world. This is a breaking change, but I don't expect it to be noticed by anybody, because running TZ-aware guests isn't common and those guests are generally going to be booting from the flash and implicitly expecting their Non-secure guests to not touch it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-5-git-send-email-peter.maydell@linaro.org
2016-03-04hw/arm/virt: Load bios image to MemoryRegion, not physaddrPeter Maydell
If we're loading a BIOS image into the first flash device, load it into the flash's memory region specifically, not into the physical address where the flash resides. This will make a difference when the flash might be in the Secure address space rather than the Nonsecure one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-4-git-send-email-peter.maydell@linaro.org
2016-03-04loader: Add load_image_mr() to load ROM image to a MemoryRegionPeter Maydell
Add a new function load_image_mr(), which behaves like load_image_targphys() except that it loads the ROM image to a specified MemoryRegion rather than to a specified physical address. This is useful when a ROM blob needs to be loaded to a particular flash or ROM device but the address of that device in the machine's address space is not known. (For instance, ROMs in devices, or ROMs which might exist in a different address space to the system address space.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-3-git-send-email-peter.maydell@linaro.org Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
2016-03-04hw/arm/virt: Provide a secure-only RAM if booting in Secure modePeter Maydell
If we're booting in Secure mode, provide a secure-only RAM (just 16MB) so that secure firmware has somewhere to run from that won't be accessible to the Non-secure guest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1455288361-30117-2-git-send-email-peter.maydell@linaro.org
2016-03-04sdhci: Implement DeviceClass resetPeter Maydell
The sdhci device was missing a DeviceClass reset method; implement it. Poweron reset looks the same as reset commanded by the guest via the device registers, apart from modelling of the rpi 'pending insert interrupt on powerup' quirk. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Message-id: 1456493044-10025-3-git-send-email-peter.maydell@linaro.org
2016-03-04sd.c: Handle NULL block backend in sd_get_inserted()Peter Maydell
The sd.c SD card emulation code can be in a state where the SDState BlockBackend pointer is NULL; this is treated as "card not present". Add a missing check to sd_get_inserted() so that we don't segfault in this situation. (This could be provoked by the guest writing to the SDHCI register to do a reset on a xilinx-zynq-a9 board; it will also happen at startup when sdhci implements its DeviceClass reset method.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1456493044-10025-2-git-send-email-peter.maydell@linaro.org
2016-03-04virt: Lift the maximum RAM limit from 30GB to 255GBPeter Maydell
The virt board restricts guests to only 30GB of RAM. This is a hangover from the vexpress-a15 board, and there's no inherent reason for it. 30GB is smaller than you might reasonably want to provision a VM for on a beefy server machine. Raise the limit to 255GB. We choose 255GB because the available space we currently have below the 1TB boundary is up to the 512GB mark, but we don't want to paint ourselves into a corner by assigning it all to RAM. So we make half of it available for RAM, with the 256GB..512GB range available for future non-RAM expansion purposes. If we need to provide more RAM to VMs in the future then we need to: * allocate a second bank of RAM starting at 2TB and working up * fix the DT and ACPI table generation code in QEMU to correctly report two split lumps of RAM to the guest * fix KVM in the host kernel to allow guests with >40 bit address spaces The last of these is obviously the trickiest, but it seems reasonable to assume that anybody configuring a VM with a quarter of a terabyte of RAM will be doing it on a host with more than a terabyte of physical address space. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Tested-by: Wei Huang <wei@redhat.com> Message-id: 1456402182-11651-1-git-send-email-peter.maydell@linaro.org
2016-03-04target-arm: Correct handling of writes to CPSR mode bits from gdb in usermodePeter Maydell
In helper.c the expression (env->uncached_cpsr & CPSR_M) != CPSR_USER is always true; the right hand side was supposed to be ARM_CPU_MODE_USR (an error in commit cb01d391). Since the incorrect expression was always true, this just meant that commit cb01d391 had no effect. However simply changing the RHS here would reveal a logic error: if the mode is USR we wish to completely ignore the attempt to set the mode bits, which means that we must clear the CPSR_M bits from mask to avoid the uncached_cpsr bits being updated at the end of the function. Move the condition into the correct place in the code, fix its RHS constant, and add a comment about the fact that we must be doing a gdbstub write if we're in user mode. Fixes: https://bugs.launchpad.net/qemu/+bug/1550503 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1456764438-30015-1-git-send-email-peter.maydell@linaro.org
2016-03-03Merge remote-tracking branch 'remotes/amit-virtio-rng/tags/rng-for-2.6-1' ↵Peter Maydell
into staging rng: - implement a request queue for rng-random so multiple guest requests don't result in vq buffers getting forgotten - remove unused request cancellation code - a VM with multiple vq buffers, when migrated, could get in a situation where not all buffers are handed back to the guest. This is now fixed. # gpg: Signature made Thu 03 Mar 2016 12:18:54 GMT using RSA key ID 854083B6 # gpg: Good signature from "Amit Shah <amit@amitshah.net>" # gpg: aka "Amit Shah <amit@kernel.org>" # gpg: aka "Amit Shah <amitshah@gmx.net>" * remotes/amit-virtio-rng/tags/rng-for-2.6-1: virtio-rng: ask for more data if queue is not fully drained rng: add request queue support to rng-random rng: move request queue cleanup from RngEgd to RngBackend rng: move request queue from RngEgd to RngBackend rng: remove the unused request cancellation code MAINTAINERS: Add an entry for the include/sysemu/rng*.h files Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-03virtio-rng: ask for more data if queue is not fully drainedLadi Prosek
This commit effectively reverts: commit 4621c1768ef5d12171cca2aa1473595ecb9f1c9e Author: Amit Shah <amit.shah@redhat.com> Date: Wed Nov 21 11:21:19 2012 +0530 virtio-rng: remove extra request for entropy but instead of calling virtio_rng_process unconditionally, it first checks to see if the queue is empty as a little bit of optimization. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1456998514-19271-1-git-send-email-lprosek@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-03-03rng: add request queue support to rng-randomLadi Prosek
Requests are now created in the RngBackend parent class and the code path is shared by both rng-egd and rng-random. This commit fixes the rng-random implementation which processed only one request at a time and simply discarded all but the most recent one. In the guest this manifested as delayed completion of reads from virtio-rng, i.e. a read was completed only after another read was issued. By switching rng-random to use the same request queue as rng-egd, the unsafe stack-based allocation of the entropy buffer is eliminated and replaced with g_malloc. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1456994238-9585-5-git-send-email-lprosek@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-03-03rng: move request queue cleanup from RngEgd to RngBackendLadi Prosek
RngBackend is now in charge of cleaning up the linked list on instance finalization. It also exposes a function to finalize individual RngRequest instances, called by its child classes. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1456994238-9585-4-git-send-email-lprosek@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-03-03rng: move request queue from RngEgd to RngBackendLadi Prosek
The 'requests' field now lives in the RngBackend parent class. There are no functional changes in this commit. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1456994238-9585-3-git-send-email-lprosek@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-03-03rng: remove the unused request cancellation codeLadi Prosek
rng_backend_cancel_requests had no callers and none of the code deleted in this commit ever ran. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1456994238-9585-2-git-send-email-lprosek@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-03-03MAINTAINERS: Add an entry for the include/sysemu/rng*.h filesThomas Huth
These headers are used by the virtio-rng and rng backends code, so they should be listed in the same section in MAINTAINERS, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Amit Shah <amit.shah@redhat.com> Message-Id: <1456404260-26928-1-git-send-email-thuth@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com>
2016-03-01Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' ↵Peter Maydell
into staging # gpg: Signature made Tue 01 Mar 2016 15:48:04 GMT using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/tracing-pull-request: trace: Add a proper API to manage auto-generated events from the 'tcg' property trace: Add 'vcpu' event property to trace guest vCPU typedefs: Add CPUState trace: Add helper function to cast event arguments tcg: Move definition of type TCGv tcg: Add type for vCPU pointers trace: Remove unnecessary intermediate event copies trace: Extend API to manage event arguments vl: fix tracing initialization trace: use addresses instead of offsets in memory tracepoints trace: split subpage MMIOs into their own trace events. trace: docs: "simple" backend does support strings trace: drop trailing empty strings Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-01trace: Add a proper API to manage auto-generated events from the 'tcg' propertyLluís Vilanova
Formalizes the existence of the 'event_trans' and 'event_exec' event attributes, which until now were monkey-patched only when necessary. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 145640558759.20978.6374959404425591089.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-03-01trace: Add 'vcpu' event property to trace guest vCPULluís Vilanova
This property identifies events that trace vCPU-specific information. It adds a "CPUState*" argument to events with the property, identifying the vCPU raising the event. TCG translation events also have a "TCGv_env" implicit argument that is later used as the "CPUState*" argument at execution time. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 145641861797.30295.6991314023181842105.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-03-01typedefs: Add CPUStateLluís Vilanova
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 145641861239.30295.8564457138934628740.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-03-01trace: Add helper function to cast event argumentsLluís Vilanova
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 145641860680.30295.1873612736245870753.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-03-01tcg: Move definition of type TCGvLluís Vilanova
The target-dependant type TCGv must be defined in "tcg/tcg.h" before including the tracing helper wrappers in "tcg/tcg-op.h". It also makes more sense to define it here, where other TCG types are defined too. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 145641860129.30295.17554707227384022653.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-03-01tcg: Add type for vCPU pointersLluís Vilanova
Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The tracing infrastructure later needs to differentiate between regular pointers and pointers to vCPUs. Also changes all targets to use the new 'TCGv_env' type instead of the generic 'TCGv_ptr'. As of now, the change is merely cosmetic ('TCGv_env' translates into 'TCGv_ptr'), but that could change in the future to enforce the difference. Note that a 'TCGv_env' type (for 'CPUState') is not added, since all helpers currently receive the architecture-specific pointer ('CPUArchState'). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Acked-by: Richard Henderson <rth@twiddle.net> Message-id: 145641859552.30295.7821536833590725201.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-03-01trace: Remove unnecessary intermediate event copiesLluís Vilanova
The current code forces the use of a chain of ".original" dereferences, which looks odd. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-id: 145641858988.30295.7223459456488075843.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-03-01trace: Extend API to manage event argumentsLluís Vilanova
Lets the user manage event arguments as a list, and simplifies argument concatenation. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 145641858432.30295.3069911069472672646.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-03-01vl: fix tracing initializationDenis V. Lunev
we should call trace_init_backends() before trace_init_file() for CONFIG_TRACE_SIMPLE There is no difference for other cases. This problem was introduced by the commit commit 41fc57e44ed64cd4ab5393d83624afd897dabd4f Author: Paolo Bonzini <pbonzini@redhat.com> Date: Thu Jan 7 16:55:24 2016 +0300 trace: split trace_init_file out of trace_init_backends 'make check' was failed as a result if configured with --enable-trace-backends=simple Spotted by Alex Bennée. Signed-off-by: Denis V. Lunev <den@openvz.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-id: 1455036545-14870-1-git-send-email-den@openvz.org CC: Alex Bennée <alex.bennee@linaro.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-03-01trace: use addresses instead of offsets in memory tracepointsHollis Blanchard
When memory_region_ops tracepoints are enabled, calculate and record the absolute address being accessed. Otherwise, we only get offsets into the memory region instead of addresses. [Fixed "offset" -> "addr" in trace event format strings. --Stefan] Signed-off-by: Hollis Blanchard <hollis_blanchard@mentor.com> Message-id: 1454976185-30095-3-git-send-email-hollis_blanchard@mentor.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-03-01trace: split subpage MMIOs into their own trace events.Hollis Blanchard
Previously, a single MMIO could trigger the memory_region_ops tracepoint twice: once on its way into subpage ops, then later on its way into the model's ops. Also, the fields previously called "addr" are actually offsets into the memory region. Rename them to "offset" while we're editing the tracepoint definitions. Signed-off-by: Hollis Blanchard <hollis_blanchard@mentor.com> Message-id: 1454976185-30095-2-git-send-email-hollis_blanchard@mentor.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-03-01trace: docs: "simple" backend does support stringsHollis Blanchard
The simple tracing backend has supported strings for more than three years (62bab73213ba885426a781eb2741670b9f3cae36). Signed-off-by: Hollis Blanchard <hollis_blanchard@mentor.com> Message-id: 1454976185-30095-1-git-send-email-hollis_blanchard@mentor.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-03-01trace: drop trailing empty stringsGreg Kurz
Also fix a typo in the virtio_balloon_handle_output() trace while here. [The double-quoting was a limitation of the old tracetool.sh script. The modern tracetool.py script does not require double-quotes at the end of the line. See commit cf85cf8e972f3ad79f203be4edb7968d6e052293 ("trace: Format strings must begin/end with double quotes"). --Stefan] Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: 20160111173036.24764.59878.stgit@bahia.huguette.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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