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2016-09-07ppc: Don't update NIP in facility unavailable interruptsBenjamin Herrenschmidt
This is no longer necessary as the helpers will properly retrieve the return address when needed. Also remove gen_update_current_nip() which didn't seem to make much sense to me. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in DCR access routinesBenjamin Herrenschmidt
This is no longer necessary as the helpers will properly retrieve the return address when needed Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Fix source NIP on SLB related interruptsBenjamin Herrenschmidt
We need to pass it to the raise helper since we don't update it before the calls. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Make tlb_fill() use new exception helperBenjamin Herrenschmidt
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in lmw/stmw/icbiBenjamin Herrenschmidt
Instead, pass GETPC() result to the corresponding helpers. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in lswi/lswx/stswi/stswxBenjamin Herrenschmidt
Instead, pass GETPC() result to the corresponding helpers. This requires a bit of fiddling to get the PC (hopefully) right in the case where we generate a program check, though the hacks there are temporary, a subsequent patch will clean this all up by always having the nip already set to the right instruction when taking the fault. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [dwg: Fix trivial checkpatch warning] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: FP exceptions are always preciseBenjamin Herrenschmidt
We don't implement imprecise FP exceptions and using store_current which sets SRR1 to the *previous* instruction never makes sense for these. So let's be truthful and make them precise, which is allowed by the architecture. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update the NIP in floating point generated codeBenjamin Herrenschmidt
This is no longer necessary as the helpers will properly retrieve the return address. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Make float_check_status() pass the return addressBenjamin Herrenschmidt
Instead of relying on NIP having been updated already. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [dwg: Fold in fix to mark function always_inline] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Make float_invalid_op_excp() pass the return addressBenjamin Herrenschmidt
Instead of relying on NIP having been updated already Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Rename fload_invalid_op_excp to float_invalid_op_excpBenjamin Herrenschmidt
No other change Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move VSX ops out of translate.cBenjamin Herrenschmidt
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move VMX ops out of translate.cBenjamin Herrenschmidt
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move DFP ops out of translate.cBenjamin Herrenschmidt
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move embedded spe ops out of translate.cBenjamin Herrenschmidt
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move classic fp ops out of translate.cBenjamin Herrenschmidt
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Provide basic raise_exception_* functionsBenjamin Herrenschmidt
Instead of using the same helpers called from translate.c, let's have a bunch of functions that take the various argument combinations, especially the retaddr which will be needed in subsequent patches, and leave the helpers to be just that, helpers for translate.c We don't yet convert all users, we'll go through them in subsequent patches. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> -- v2. Fix raise_exception_ra() to properly pass raddr Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: introduce opc4 for Expanded OpcodeNikunj A Dadhania
ISA 3.0 has introduced EO - Expanded Opcode. Introduce third level indirect opcode table and corresponding parsing routines. EO (11:12) Expanded opcode field Formats: XX1 EO (11:15) Expanded opcode field Formats: VX, X, XX2 Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> [dwg: Trivial checkpatch fixup] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add maddhd and maddhdu instructionNikunj A Dadhania
maddhd: Multiply-Add High Doubleword maddhdu: Multiply-Add High Doubleword Unsigned Above two instruction are dual form and differ by 1 bit (31st bit) Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the higher dword in the target register(RT). Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add maddld instructionNikunj A Dadhania
maddld: Multiply-Add Low Doubleword Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the lower dword in the target register(RT). Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add setb instructionVivek Andrew Sha
The CR number is provided in the opcode as - BFA (11:13) Returns: -1 if bit 0 of CR field is set 1 if bit 1 of CR field is set 0 otherwise. Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com> [ reworded commit, used 32bit ops as crf is 32bits ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cmpeqb instructionNikunj A Dadhania
Search a byte in the stream of 8bytes provided in the register Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cnttzw[.] instructionNikunj A Dadhania
Add ISA3.0: Count trailing zeros word instruction. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cnttzd[.] instructionSandipan Das
Add ISA3.0 Count trailing zeros double word Signed-off-by: Sandipan Das <sandipandas1990@gmail.com> [ added ISA300 flag ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add modulo dword operationsNikunj A Dadhania
Adding following instructions for ISA3.0 support modud: Modulo Unsigned Dword modsd: Modulo Signed Dword Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add modulo word operationsNikunj A Dadhania
Adding following instructions: moduw: Modulo Unsigned Word modsw: Modulo Signed Word Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cmprb instructionNikunj A Dadhania
ISA 3.0 Compare Ranged Byte instruction useful for isupper/islower/isaplha kind of operation. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: adding addpcis instructionNikunj A Dadhania
ISA 3.0 instruction for adding immediate value shifted with next instruction address and return the result in the target register. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: Introduce POWER ISA 3.0 flagNikunj A Dadhania
This flag will be used for POWER9 instructions. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: Introduce Power9 familyAneesh Kumar K.V
The patch adds CPU PVR definition for POWER9 and enables QEMU to launch guests/linux-user in TCG mode. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> [ Added POWER9 alias, POWER9 SPAPR core and dropped MMU defines ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> [dwg: Dropped sPAPR core type again for now] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07hw/ppc: include fdt helper routine in a common fileCédric Le Goater
spapr_pci would also be a good candidate but the macro _FDT is slightly different. It returns and does not exit. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07xics_kvm: drop extra checking of kernel_xics_fdGreg Kurz
We abort a few lines above if kernel_xics_fd == -1. This is only code cleanup. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-06Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell
Block layer patches # gpg: Signature made Tue 06 Sep 2016 11:38:01 BST # gpg: using RSA key 0x7F09B272C88F2FD6 # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (36 commits) block: Allow node name for 'qemu-io' HMP command qemu-iotests: Log QMP traffic in debug mode block jobs: Improve error message for missing job ID coroutine: Assert that no locks are held on termination coroutine: Let CoMutex remember who holds it qcow2: fix iovec size at qcow2_co_pwritev_compressed test-coroutine: Fix coroutine pool corruption qemu-iotests: add vmdk for test backup compression in 055 qemu-iotests: test backup compression in 055 blockdev-backup: added support for data compression drive-backup: added support for data compression block: simplify blockdev-backup block: simplify drive-backup block/io: turn on dirty_bitmaps for the compressed writes block: remove BlockDriver.bdrv_write_compressed qcow: cleanup qcow_co_pwritev_compressed to avoid the recursion qcow: add qcow_co_pwritev_compressed vmdk: add vmdk_co_pwritev_compressed qcow2: cleanup qcow2_co_pwritev_compressed to avoid the recursion qcow2: add qcow2_co_pwritev_compressed ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-06Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160906-v2' into ↵Peter Maydell
staging First (big) chunk of s390x updates: - cpumodel support for s390x - various fixes and improvements # gpg: Signature made Tue 06 Sep 2016 16:09:53 BST # gpg: using RSA key 0xDECF6B93C6F02FAF # gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck/tags/s390x-20160906-v2: (38 commits) s390x/cpumodel: implement QMP interface "query-cpu-model-baseline" s390x/cpumodel: implement QMP interface "query-cpu-model-comparison" s390x/cpumodel: implement QMP interface "query-cpu-model-expansion" qmp: add QMP interface "query-cpu-model-baseline" qmp: add QMP interface "query-cpu-model-comparison" qmp: add QMP interface "query-cpu-model-expansion" s390x/kvm: don't enable key wrapping if msa3 is disabled s390x/kvm: let the CPU model control CMM(A) s390x/kvm: disable host model for problematic compat machines s390x/kvm: implement CPU model support s390x/kvm: allow runtime-instrumentation for "none" machine s390x/sclp: propagate hmfai s390x/sclp: propagate the mha via sclp s390x/sclp: propagate the ibc val (lowest and unblocked ibc) s390x/sclp: indicate sclp features s390x/sclp: introduce sclp feature blocks s390x/sclp: factor out preparation of cpu entries s390x/cpumodel: check and apply the CPU model s390x/cpumodel: let the CPU model handle feature checks s390x/cpumodel: expose features and feature groups as properties ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-09-06s390x/cpumodel: implement QMP interface "query-cpu-model-baseline"David Hildenbrand
Let's implement that interface by reusing our conversion code and lookup code for CPU definitions. In order to find a compatible CPU model, we first detect the maximum possible CPU generation and then try to find a maximum model, satisfying all base features (not exceeding the maximum generation). Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-31-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06s390x/cpumodel: implement QMP interface "query-cpu-model-comparison"David Hildenbrand
Let's implement that interface by reusing our convertion code implemented for expansion. We use CPU generations and CPU features to calculate the result. This means, that a zEC12 cannot simply be converted into a z13 by stripping of features. This is required, as other magic values (e.g. maximum address sizes) belong to a CPU generation and cannot simply be emulated by an older generation. Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-30-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06s390x/cpumodel: implement QMP interface "query-cpu-model-expansion"David Hildenbrand
In order to expand CPU models, we create temporary cpus that handle the feature/group parsing. Only CPU feature properties are expanded. When converting the data structure back, we always fall back to the static base CPU model, which is by definition migration-safe. Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-29-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06qmp: add QMP interface "query-cpu-model-baseline"David Hildenbrand
Let's provide a standardized interface to baseline two CPU models, to create a third, compatible one. This is especially helpful when two CPU models are not identical, but a CPU model is required that is guaranteed to run under both configurations, where the original models run. "query-cpu-model-baseline" takes two CPU models and returns a third, compatible model. The result will always be a static CPU model. Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-28-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06qmp: add QMP interface "query-cpu-model-comparison"David Hildenbrand
Let's provide a standardized interface to compare two CPU models. "query-cpu-model-compare" takes two models and returns how they compare in a specific configuration. The result will give guarantees about runnability. E.g. if a CPU model A is a subset of CPU model B, model A is guaranteed to run in configurations where model B runs, but not the other way around (might or might not run). Usually, CPU features or CPU generations are used to calculate the result. If a model is not guaranteed to run in a certain environment (e.g. incompatible), a compatible one can be created by "baselining" both models (follow up patch). Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-27-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06qmp: add QMP interface "query-cpu-model-expansion"David Hildenbrand
Let's provide a standardized interface to expand CPU models. This interface can be used by tooling to get details about a specific CPU model in a certain configuration, e.g. about the "host" model. To take care of all architectures, two detail levels for an expansion are introduced. Certain architectures might not support all detail levels. While "full" will expand and indicate all relevant properties/features of a CPU model, "static" expands to a static base CPU model, that will never change between QEMU versions and therefore have the same features when used under different compatibility machines. Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-26-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06s390x/kvm: don't enable key wrapping if msa3 is disabledDavid Hildenbrand
As the CPU model now controls msa3, trying to set wrapping keys without msa3 being around/enable in the kernel will produce misleading errors. So let's simply not configure key wrapping if msa3 is not enabled and make compat machines with disabled CPU model work correctly. Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-25-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06s390x/kvm: let the CPU model control CMM(A)David Hildenbrand
Starting with recent kernels, if the cmma attributes are available, we actually have hardware support. Enabling CMMA then means providing the guest VCPU with CMM, therefore enabling its CMM facility. Let's not blindly enable CMM anymore but let's control it using CPU models. For disabled CPU models, CMMA will continue to always get enabled. Also enable it in the applicable default models. Please note that CMM doesn't work with hugetlbfs, therefore we will warn the user and keep it disabled. Migrating from/to a hugetlbfs configuration works, as it will be disabled on both sides. Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-24-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06s390x/kvm: disable host model for problematic compat machinesDavid Hildenbrand
Compatibility machines that touch runtime-instrumentation should not be used with the CPU model. Otherwise the host model will look different, depending on the QEMU machine QEMU has been started with. So let's simply disable the host model for existing compatibility machines that all disable ri. This, in return, disables the CPU model for these compat machines completely. Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-23-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06s390x/kvm: implement CPU model supportDavid Hildenbrand
Let's implement our two hooks so we can support CPU models. Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-22-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06s390x/kvm: allow runtime-instrumentation for "none" machineDavid Hildenbrand
To be able to query the correct host model for the "none" machine, let's allow runtime-instrumentation for that machine. Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-21-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06s390x/sclp: propagate hmfaiDavid Hildenbrand
hmfai is provided on CPU models >= z196. Let's propagate it properly. Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-19-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06s390x/sclp: propagate the mha via sclpDavid Hildenbrand
The mha is provided in the CPU model, so get any CPU and extract the value. Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-18-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06s390x/sclp: propagate the ibc val (lowest and unblocked ibc)David Hildenbrand
If we have a lowest ibc, we can indicate the ibc to the guest. Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-17-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06s390x/sclp: indicate sclp featuresDavid Hildenbrand
We have three different blocks in the SCLP read-SCP information response that indicate sclp features. Let's prepare propagation. Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-16-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2016-09-06s390x/sclp: introduce sclp feature blocksDavid Hildenbrand
The sclp "read cpu info" and "read scp info" commands can include features for the cpu info and configuration characteristics (extended), decribing some advanced features available in the configuration. Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Message-Id: <20160905085244.99980-15-dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
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