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2024-03-06contrib/plugins/hotblocks: migrate to new per_vcpu APIPierrick Bouvier
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240304130036.124418-10-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-23-alex.bennee@linaro.org>
2024-03-06tests/plugin/bb: migrate to new per_vcpu APIPierrick Bouvier
Reviewed-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240304130036.124418-9-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-22-alex.bennee@linaro.org>
2024-03-06tests/plugin/insn: migrate to new per_vcpu APIPierrick Bouvier
Reviewed-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240304130036.124418-8-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-21-alex.bennee@linaro.org>
2024-03-06tests/plugin/mem: migrate to new per_vcpu APIPierrick Bouvier
Reviewed-by: Luc Michel <luc.michel@amd.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240304130036.124418-7-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-20-alex.bennee@linaro.org>
2024-03-06tests/plugin: add test plugin for inline operationsPierrick Bouvier
For now, it simply performs instruction, bb and mem count, and ensure that inline vs callback versions have the same result. Later, we'll extend it when new inline operations are added. Use existing plugins to test everything works is a bit cumbersome, as different events are treated in different plugins. Thus, this new one. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240304130036.124418-6-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-19-alex.bennee@linaro.org>
2024-03-06plugins: add inline operation per vcpuPierrick Bouvier
Extends API with three new functions: qemu_plugin_register_vcpu_{tb, insn, mem}_exec_inline_per_vcpu(). Those functions takes a qemu_plugin_u64 as input. This allows to have a thread-safe and type-safe version of inline operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240304130036.124418-5-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-18-alex.bennee@linaro.org>
2024-03-06plugins: implement inline operation relative to cpu_indexPierrick Bouvier
Instead of working on a fixed memory location, allow to address it based on cpu_index, an element size and a given offset. Result address: ptr + offset + cpu_index * element_size. With this, we can target a member in a struct array from a base pointer. Current semantic is not modified, thus inline operation still targets always the same memory location. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240304130036.124418-4-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-17-alex.bennee@linaro.org>
2024-03-06plugins: define qemu_plugin_u64Pierrick Bouvier
Additionally to the scoreboard, we define a qemu_plugin_u64, which is a simple struct holding a pointer to a scoreboard, and a given offset. This allows to have a scoreboard containing structs, without having to bring offset to operate on a specific field. Since most of the plugins are simply collecting a sum of per-cpu values, qemu_plugin_u64 directly support this operation as well. All inline operations defined later will use a qemu_plugin_u64 as input. New functions: - qemu_plugin_u64_add - qemu_plugin_u64_get - qemu_plugin_u64_set - qemu_plugin_u64_sum New macros: - qemu_plugin_scoreboard_u64 - qemu_plugin_scoreboard_u64_in_struct Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240304130036.124418-3-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-16-alex.bennee@linaro.org>
2024-03-06plugins: scoreboard APIPierrick Bouvier
We introduce a cpu local storage, automatically managed (and extended) by QEMU itself. Plugin allocate a scoreboard, and don't have to deal with how many cpus are launched. This API will be used by new inline functions but callbacks can benefit from this as well. This way, they can operate without a global lock for simple operations. At any point during execution, any scoreboard will be dimensioned with at least qemu_plugin_num_vcpus entries. New functions: - qemu_plugin_scoreboard_find - qemu_plugin_scoreboard_free - qemu_plugin_scoreboard_new Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20240304130036.124418-2-pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-15-alex.bennee@linaro.org>
2024-03-06tests/tcg: Add two follow-fork-mode testsIlya Leoshkevich
Add follow-fork-mode child and and follow-fork-mode parent tests. Check for the obvious pitfalls, such as lingering breakpoints, catchpoints, and single-step mode. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240219141628.246823-13-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-14-alex.bennee@linaro.org>
2024-03-06gdbstub: Implement follow-fork-mode childIlya Leoshkevich
Currently it's not possible to use gdbstub for debugging linux-user code that runs in a forked child, which is normally done using the `set follow-fork-mode child` GDB command. Purely on the protocol level, the missing piece is the fork-events feature. However, a deeper problem is supporting $Hg switching between different processes - right now it can do only threads. Implementing this for the general case would be quite complicated, but, fortunately, for the follow-fork-mode case there are a few factors that greatly simplify things: fork() happens in the exclusive section, there are only two processes involved, and before one of them is resumed, the second one is detached. This makes it possible to implement a simplified scheme: the parent and the child share the gdbserver socket, it's used only by one of them at any given time, which is coordinated through a separate socketpair. The processes can read from the gdbserver socket only one byte at a time, which is not great for performance, but, fortunately, the follow-fork-mode handling involves only a few messages. Advertise the fork-events support, and remember whether GDB has it as well. Implement the state machine that is initialized on fork(), decides the current owner of the gdbserver socket, and is terminated when one of the two processes is detached. The logic for the parent and the child is the same, only the initial state is different. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240219141628.246823-12-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-13-alex.bennee@linaro.org>
2024-03-06gdbstub: Introduce gdb_handle_detach_user()Ilya Leoshkevich
The upcoming follow-fork-mode child support needs to perform certain actions when GDB detaches from the stopped parent or the stopped child. Introduce a user-specific hook for this. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240219141628.246823-11-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-12-alex.bennee@linaro.org>
2024-03-06gdbstub: Introduce gdb_handle_set_thread_user()Ilya Leoshkevich
The upcoming follow-fork-mode child support needs to perform certain actions when GDB switches between the stopped parent and the stopped child. Introduce a user-specific hook for this. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240219141628.246823-10-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-11-alex.bennee@linaro.org>
2024-03-06gdbstub: Introduce gdb_handle_query_supported_user()Ilya Leoshkevich
The upcoming follow-fork-mode child support requires advertising the fork-events feature, which is user-specific. Introduce a user-specific hook for this. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240219141628.246823-9-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-10-alex.bennee@linaro.org>
2024-03-06gdbstub: Call gdbserver_fork() both in parent and in childIlya Leoshkevich
The upcoming follow-fork-mode child support requires post-fork message exchange between the parent and the child. Prepare gdbserver_fork() for this purpose. Rename it to gdbserver_fork_end() to better reflect its purpose. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240219141628.246823-8-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-9-alex.bennee@linaro.org>
2024-03-06{linux,bsd}-user: Pass pid to gdbserver_fork()Ilya Leoshkevich
The upcoming follow-fork-mode child support requires knowing the child pid. Pass it down. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240219141628.246823-7-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-8-alex.bennee@linaro.org>
2024-03-06{linux,bsd}-user: Pass pid to fork_end()Ilya Leoshkevich
The upcoming follow-fork-mode child support requires knowing the child pid. Pass it down. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240219141628.246823-6-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-7-alex.bennee@linaro.org>
2024-03-06gdbstub: Introduce gdbserver_fork_start()Ilya Leoshkevich
The upcoming follow-fork-mode child support requires knowing when fork() is about to happen in order to initialize its state. Add a hook for that. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240219141628.246823-5-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-6-alex.bennee@linaro.org>
2024-03-06{linux,bsd}-user: Update ts_tid after fork()Ilya Leoshkevich
Currently ts_tid contains the parent tid after fork(), which is not correct. So far it has not affected anything, but the upcoming follow-fork-mode child support relies on the correct value, so fix it. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Message-Id: <20240219141628.246823-4-iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-5-alex.bennee@linaro.org>
2024-03-06{linux,bsd}-user: Introduce get_task_state()Ilya Leoshkevich
A CPU's TaskState is stored in the CPUState's void *opaque field, accessing which is somewhat awkward due to having to use a cast. Introduce a wrapper and use it everywhere. Suggested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240219141628.246823-3-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-4-alex.bennee@linaro.org>
2024-03-06gdbstub: Support disablement in a multi-threaded processIlya Leoshkevich
The upcoming follow-fork-mode child support will require disabling gdbstub in the parent process, which may have multiple threads (which are represented as CPUs). Loop over all CPUs in order to remove breakpoints and disable single-step. Move the respective code into a separate function. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20240219141628.246823-2-iii@linux.ibm.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-3-alex.bennee@linaro.org>
2024-03-06tests: bump QOS_PATH_MAX_ELEMENT_SIZE againAlex Bennée
We "fixed" a bug with LTO builds with 100c459f194 (tests/qtest: bump up QOS_PATH_MAX_ELEMENT_SIZE) but it seems it has triggered again. The array is sized according to the maximum anticipated length of a path on the graph. However, the worst case for a depth-first search is to push all nodes on the graph. So it's not really LTO, it depends on the ordering of the constructors. Lets be more assertive raising QOS_PATH_MAX_ELEMENT_SIZE to make it go away again. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1186 (again) Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240305121005.3528075-2-alex.bennee@linaro.org>
2024-03-05Merge tag 'pull-target-arm-20240305' of ↵Peter Maydell
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * raspi: Implement Broadcom Serial Controller (BSC) for BCM2835 boards * hw/char/pl011: Add support for loopback * STM32L4x5: Implement RCC clock control device * target/arm: Do memory type alignment checks * atomic.h: Reword confusing comment for qatomic_cmpxchg * qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmXnI4gZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3p5ED/wOtAHA3PK+WbQhVhnji3+k # gdhvVcldf+HLaI2v4tfaW152xjY80/j3PQFNkzptoXENA9U51F47oNYOIfULLZZX # FTKmw/mjTBc2LqJ8gLpS8Wkr/PFtDq9JJzDwZd0MwguXpzIJp31JJpESvXlAqjjv # FhuAcqNNuGwI2SXCBmp2lPoEMn8ExLDoG9rmzjxVZeZCyzUjVnJYM61ykhC4ByvK # j5+/a7pUcpgHSX5cbq7kFloPOx3JXI5lS6xUKhGXXk75qHRwiQIsxMcPq8PD1+ok # yrmp7cySwK8I7AlIPdDjpJmhU0OiBu+PkYiXmHlF2nvaUy6M0nVX2lSTzqj6VpVV # 7yYhvWXHrtIA9AUspqTRsX7tP7iMJkco7qWfKSzYl+3pTbxS4+rEoee4jNR3hqsU # lbWC47sNVtTN507qIL1dcsu+BaeSsYVftfxtFql3odTqRB+ticsjDfKg69dRSFyk # SS0t8Zy3TdomcEoQkAv/ZSpkQnQUGavbRumCG58lJdiTwTuJUmGi1ufKBrD/GeKj # IlDEl9yvKiR8uvdjj6EQqr5kOj09mmN5nvokNsq5a4aNXBYoesszWK2xodzXE2x5 # M9DHJ3S8xnN++p1idS2bikwEklG1XVQ/q52bDXQkUmQSNerVS1PCvg9hzYqA+x53 # ihJtMcsmGVfxY8aQHyHweA== # =isAe # -----END PGP SIGNATURE----- # gpg: Signature made Tue 05 Mar 2024 13:52:08 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20240305' of https://git.linaro.org/people/pmaydell/qemu-arm: qemu-options.hx: Don't claim "-serial" has limit of 4 serial ports atomic.h: Reword confusing comment for qatomic_cmpxchg target/arm: Do memory type alignment check when translation enabled target/arm: Do memory type alignment check when translation disabled accel/tcg: Add TLB_CHECK_ALIGNED accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull exec/memattrs: Remove target_tlb_bit* target/arm: Support 32-byte alignment in pow2_align tests/qtest/stm32l4x5_rcc-test.c: Add tests for the STM32L4x5_RCC hw/arm/stm32l4x5_soc.c: Use the RCC Sysclk hw/misc/stm32l4x5_rcc: Add write protections to CR register hw/misc/stm32l4x5_rcc: Handle Register Updates hw/misc/stm32l4x5_rcc: Initialize PLLs and clock multiplexers hw/misc/stm32l4x5_rcc: Add an internal PLL Clock object hw/misc/stm32l4x5_rcc: Add an internal clock multiplexer object hw/misc/stm32l4x5_rcc: Implement STM32L4x5_RCC skeleton hw/char/pl011: Add support for loopback tests/qtest: Add testcase for BCM2835 BSC hw/arm: Connect BSC to BCM2835 board as I2C0, I2C1 and I2C2 hw/i2c: Implement Broadcom Serial Controller (BSC) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05qemu-options.hx: Don't claim "-serial" has limit of 4 serial portsSteven Shen
Before v2.12, the implementation of serial ports was limited to a value of MAX_SERIAL_PORTS = 4. We now dynamically allocate the data structures for serial ports, so this limit is no longer present, but the documentation for the -serial options still reads: "This option can be used several times to simulate up to 4 serial ports." Update to "This option can be used several times to simulate multiple serial ports." to avoid misleading. Signed-off-by: Steven Shen <steven.shen@jaguarmicro.com> Message-id: 20240305013016.2268-1-steven.shen@jaguarmicro.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05atomic.h: Reword confusing comment for qatomic_cmpxchgPeter Maydell
The qatomic_cmpxchg() and qatomic_cmpxchg__nocheck() macros have a comment that reads: Returns the eventual value, failed or not This is somewhere between cryptic and wrong, since the value actually returned is the value that was in memory before the cmpxchg. Reword to match how we describe these macros in atomics.rst. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-id: 20240223182035.1048541-1-peter.maydell@linaro.org
2024-03-05target/arm: Do memory type alignment check when translation enabledRichard Henderson
If translation is enabled, and the PTE memory type is Device, enable checking alignment via TLB_CHECK_ALIGNMENT. While the check is done later than it should be per the ARM, it's better than not performing the check at all. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301204110.656742-7-richard.henderson@linaro.org [PMM: tweaks to comment text] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05target/arm: Do memory type alignment check when translation disabledRichard Henderson
If translation is disabled, the default memory type is Device, which requires alignment checking. This is more optimally done early via the MemOp given to the TCG memory operation. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reported-by: Idan Horowitz <idan.horowitz@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301204110.656742-6-richard.henderson@linaro.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1204 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05accel/tcg: Add TLB_CHECK_ALIGNEDRichard Henderson
This creates a per-page method for checking of alignment. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301204110.656742-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05accel/tcg: Add tlb_fill_flags to CPUTLBEntryFullRichard Henderson
Allow the target to set tlb flags to apply to all of the comparators. Remove MemTxAttrs.byte_swap, as the bit is not relevant to memory transactions, only the page mapping. Adjust target/sparc to set TLB_BSWAP directly. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301204110.656742-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05exec/memattrs: Remove target_tlb_bit*Richard Henderson
These fields are no longer used since 937f224559. Target specific extensions to the page tables should be done with TARGET_PAGE_ENTRY_EXTRA. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301204110.656742-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05target/arm: Support 32-byte alignment in pow2_alignRichard Henderson
Now that we have removed TARGET_PAGE_BITS_MIN-6 from TLB_FLAGS_MASK, we can test for 32-byte alignment. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240301204110.656742-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05tests/qtest/stm32l4x5_rcc-test.c: Add tests for the STM32L4x5_RCCArnaud Minier
Tests: - the ability to change the sysclk of the device - the ability to enable/disable/configure the PLLs - if the clock multiplexers work - the register flags and the generation of irqs Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Acked-by: Thomas Huth <thuth@redhat.com> Message-id: 20240303140643.81957-9-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/arm/stm32l4x5_soc.c: Use the RCC SysclkArnaud Minier
Now that we can generate reliable clock frequencies from the RCC, remove the hacky definition of the sysclk in the b_l475e_iot01a initialisation code and use the correct RCC clock. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240303140643.81957-8-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/misc/stm32l4x5_rcc: Add write protections to CR registerArnaud Minier
Add write protections for the fields in the CR register. PLL configuration write protections (among others) have not been handled yet. This is planned in a future patch set. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240303140643.81957-7-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/misc/stm32l4x5_rcc: Handle Register UpdatesArnaud Minier
Update the RCC state and propagate frequency changes when writing to the RCC registers. Currently, ICSCR, CIER, the reset registers and the stop mode registers are not implemented. Some fields have not been implemented due to uncertainty about how to handle them (Like the clock security system or bypassing mecanisms). Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240303140643.81957-6-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/misc/stm32l4x5_rcc: Initialize PLLs and clock multiplexersArnaud Minier
Instantiate the whole clock tree and using the Clock multiplexers and the PLLs defined in the previous commits. This allows to statically define the clock tree and easily follow the clock signal from one end to another. Also handle three-phase reset now that we have defined a known base state for every object. (Reset handling based on hw/misc/zynq_sclr.c) Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240303140643.81957-5-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/misc/stm32l4x5_rcc: Add an internal PLL Clock objectArnaud Minier
This object represents the PLLs and their channels. The PLLs allow for a more fine-grained control of the clocks frequency. The migration handling is based on hw/misc/zynq_sclr.c. Three phase reset will be handled in a later commit. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Message-id: 20240303140643.81957-4-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/misc/stm32l4x5_rcc: Add an internal clock multiplexer objectArnaud Minier
This object is used to represent every multiplexer in the clock tree as well as every clock output, every presecaler, frequency multiplier, etc. This allows to use a generic approach for every component of the clock tree (except the PLLs). The migration handling is based on hw/misc/zynq_sclr.c. Three phase reset will be handled in a later commit. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240303140643.81957-3-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/misc/stm32l4x5_rcc: Implement STM32L4x5_RCC skeletonArnaud Minier
Add the necessary files to add a simple RCC implementation with just reads from and writes to registers. Also instantiate the RCC in the STM32L4x5_SoC. It is needed for accurate emulation of all the SoC clocks and timers. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240303140643.81957-2-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/char/pl011: Add support for loopbackTong Ho
This patch adds loopback for sent characters, sent BREAK, and modem-control signals. Loopback of send and modem-control is often used for uart self tests in real hardware but missing from current pl011 model, resulting in self-test failures when running in QEMU. This implementation matches what is observed in real pl011 hardware placed in loopback mode: 1. Input characters and BREAK events from serial backend are ignored, but 2. Both TX characters and BREAK events are still sent to serial backend, in addition to be looped back to RX. Signed-off-by: Tong Ho <tong.ho@amd.com> Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com> Message-id: 20240227054855.44204-1-tong.ho@amd.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05tests/qtest: Add testcase for BCM2835 BSCRayhan Faizel
Simple testcase for validating proper operation of read and write for all three BSC controllers. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240224191038.2409945-4-rayhan.faizel@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/arm: Connect BSC to BCM2835 board as I2C0, I2C1 and I2C2Rayhan Faizel
BCM2835 has three I2C controllers. All of them share the same interrupt line. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240224191038.2409945-3-rayhan.faizel@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05hw/i2c: Implement Broadcom Serial Controller (BSC)Rayhan Faizel
A few deficiencies in the current device model need to be noted. 1. FIFOs are not used. All sends and receives are done directly. 2. Repeated starts are not emulated. Repeated starts can be triggered in real hardware by sending a new read transfer request in the window time between transfer active set of write transfer request and done bit set of the same. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240224191038.2409945-2-rayhan.faizel@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05Merge tag 'pull-qapi-2024-03-04' of https://repo.or.cz/qemu/armbru into stagingPeter Maydell
QAPI patches patches for 2024-03-04 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmXlaSISHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTdZ8P/iMgqLoAFkCCjwfkUc/rqZUezK52Ynr7 # LYwOPI/xcYD7EnVogdRgFgjWFNoivQLP5yKsU/eRTk29pwdDzTscFm/0ztTQX/Gb # ypWV+GBcu5J8mKbp1KF5w68aDD8Bat4WRfEgDQ1DV7v6CoMiUzTiF3CGXkYzqK5Y # kYNq97vdEkBFvFdOl/7scs/XXN2jG27egDhMp68RTxnPHlXZiAO9/2Bul3uVe3x0 # fzQ2ViYv0qLnjE/PwENDqqE3Thv3Sxp5iEeQQ6GWi07EVh07UtHpOM3RYyrTU0Sb # VrTApSrg0oxlkOuR0CBd9Fi+timtbokBL0DWyUpXNTfIEZfLtA9H+8riUg3EOcDp # r7a4SI/27VdPxX6Kc6zA3bi+/j1o7CLTW2LGEwuZs52nmixoo1HTWPIFdyh13g/V # QjNbun0fViHb0FVLiyDlXF/7Y+EWUWIyqwwGqbvve1DyUHQmo3CUQAKGOpkeKSBe # 4eGciVDgpBoKhtw9Kv6LCDj2cwZKC8DxBMibf7GHkOnAsX2mnyuHcey7HvYNCoF+ # yYz7oIEXdlL2eWqg7CfBZK7lniCDln50RI4Ll1v+J4r1v1kRZGMLesTYXCdNc4ku # yb4kpU4t22/RODffLE7K+fc3Onwze3fcfxlZMN66F+wFtk4KdPR2aQBE66bB8J99 # vuSKlTbT4cGL # =s9AR # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Mar 2024 06:24:34 GMT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-qapi-2024-03-04' of https://repo.or.cz/qemu/armbru: migration: simplify exec migration functions qapi: New strv_from_str_list() qapi: New QAPI_LIST_LENGTH() docs/devel/writing-monitor-commands: Minor improvements docs/devel/writing-monitor-commands: Repair a decade of rot qapi: Reject "Returns" section when command doesn't return anything qga/qapi-schema: Fix guest-set-memory-blocks documentation qga/qapi-schema: Tweak documentation of fsfreeze commands qga/qapi-schema: Clean up "Returns" sections qga/qapi-schema: Delete useless "Returns" sections qga/qapi-schema: Move error documentation to new "Errors" sections qapi/yank: Tweak @yank's error description for consistency qapi: Clean up "Returns" sections qapi: Delete useless "Returns" sections qapi: Move error documentation to new "Errors" sections qapi: New documentation section tag "Errors" qapi: Slightly clearer error message for invalid "Returns" section qapi: Memorize since & returns sections Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-03-05Merge tag 'migration-next-pull-request' of https://gitlab.com/peterx/qemu ↵Peter Maydell
into staging Migartion pull request for 20240304 - Bryan's fix on multifd compression level API - Fabiano's mapped-ram series (base + multifd only) - Steve's amend on cpr document in qapi/ # -----BEGIN PGP SIGNATURE----- # # iIgEABYKADAWIQS5GE3CDMRX2s990ak7X8zN86vXBgUCZeUjKhIccGV0ZXJ4QHJl # ZGhhdC5jb20ACgkQO1/MzfOr1wbv5QD/ZexBUsmZA5qyxgGvZ2yvlUBEGNOvtmKY # kRdiYPU7khMA/0N43rn4LcqKCoq4+T+EAnYizGjIyhH/7BRUyn4DUxgO # =AeEn # -----END PGP SIGNATURE----- # gpg: Signature made Mon 04 Mar 2024 01:26:02 GMT # gpg: using EDDSA key B9184DC20CC457DACF7DD1A93B5FCCCDF3ABD706 # gpg: issuer "peterx@redhat.com" # gpg: Good signature from "Peter Xu <xzpeter@gmail.com>" [marginal] # gpg: aka "Peter Xu <peterx@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: B918 4DC2 0CC4 57DA CF7D D1A9 3B5F CCCD F3AB D706 * tag 'migration-next-pull-request' of https://gitlab.com/peterx/qemu: (27 commits) migration/multifd: Document two places for mapped-ram tests/qtest/migration: Add a multifd + mapped-ram migration test migration/multifd: Add mapped-ram support to fd: URI migration/multifd: Support incoming mapped-ram stream format migration/multifd: Support outgoing mapped-ram stream format migration/multifd: Prepare multifd sync for mapped-ram migration migration/multifd: Add incoming QIOChannelFile support migration/multifd: Add outgoing QIOChannelFile support migration/multifd: Add a wrapper for channels_created migration/multifd: Allow receiving pages without packets migration/multifd: Allow multifd without packets migration/multifd: Decouple recv method from pages migration/multifd: Rename MultiFDSend|RecvParams::data to compress_data tests/qtest/migration: Add tests for mapped-ram file-based migration migration/ram: Add incoming 'mapped-ram' migration migration/ram: Add outgoing 'mapped-ram' migration migration: Add mapped-ram URI compatibility check migration/ram: Introduce 'mapped-ram' migration capability migration/qemu-file: add utility methods for working with seekable channels io: fsync before closing a file channel ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # migration/ram.c
2024-03-05ui/cocoa: Remove stretch_video flagAkihiko Odaki
Evaluate [normalWindow styleMask] & NSWindowStyleMaskResizable instead. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-10-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-03-05ui/cocoa: Call console_select() with the BQLAkihiko Odaki
[-QemuCocoaView displayConsole:] can be called anytime so explicitly take the BQL before it calls console_select(). Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-9-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-03-05ui/cocoa: Make window resizableAkihiko Odaki
The window will be resizable when zoom-to-fit is on. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-8-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-03-05ui/cocoa: Remove normalWindowAkihiko Odaki
QemuCocoaView used to have fullScreenWindow but now it's gone, so we do no longer have to call the window specifically "normalWindow". Instead, refer to it with [-QemuCocoaView window]. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-7-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-03-05ui/cocoa: Let the platform toggle fullscreenAkihiko Odaki
It allows making the window full screen by clicking full screen button provided by the platform (the left-top green button) and save some code. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Rene Engel <ReneEngel80@emailn.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-ID: <20240224-cocoa-v12-6-e89f70bdda71@daynix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-17 16:40:30 +0000