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2023-07-11Merge tag 'mips-20230710' of https://github.com/philmd/qemu into stagingRichard Henderson
MIPS patches queue - Use clock API & divider for cp0_timer to avoid rounding issue (Jiaxun) - Implement Loongson CSR instructions (Jiaxun) - Implement Ingenic MXU ASE v1 rev2 (Siarhei) - Enable GINVx support for I6400 and I6500 cores (Marcin) - Generalize PCI IDE controller models (Bernhard) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmSsg5kACgkQ4+MsLN6t # wN6O4g/9GpirNnG1tizIEksI17PaAotgui2PYzml2nQLyQNmPs3lSfyDEfFpZLC6 # HGxglNjdvCgmIhRH1IuRKuJofp0r84NY+sktXjz2+As3opyjR66gVsSefWeupr7t # avZQQIBBOV3OYLzFkqjDpBflyKXz43MRW3r9ai4Dle/TwiE5GA1iKuQ6Rt55urtT # 045OdtFZTsIwTyg75pSXExAehOn5FQ4aqIODwfJYqvhkkVZ9lgWYSgUOsgDcGqPQ # eytpif6+m350Xme4BgqITMZkeIbyKcCcfU37JBqk/q6/gDDf18zSWpC7MNXea4ZR # so9ffZqms/xcIOfIO3uc4t9AZRHchiVjFHihCUKc0mBTzLy1QhQ4ybdQu3fUywaG # WziEFLrJ/qfWjixRxeDdBZamC2fSxYtcRNST7g+XttiMacvQC6aPFVfLDa+3Xjtt # TmIjx8oGdLB9BMrGMuHsOygfgi98eGbWQ2I5ZhzwBbJ7uFQdeTkMCswcAsVcj8pW # e7/ixw2e+SYFm0q9Z/QiZZ7LFDp/b3u7/ufXCUBX2r1gi7Xi+x60E6dm3Ge3XAsY # qSx9ZOlVNJlIs/ChP0KckHDMeFuCnRmNEvKC039syHWSy6VP8NO7fwwxK+XytyrK # aJMyPS97kVXuqriKZIGsV0KjLOz3neh0OdQTolPv1R5yb9tI6Xc= # =rtlE # -----END PGP SIGNATURE----- # gpg: Signature made Mon 10 Jul 2023 11:18:01 PM BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'mips-20230710' of https://github.com/philmd/qemu: (44 commits) hw/ide/piix: Move registration of VMStateDescription to DeviceClass hw/ide/pci: Replace some magic numbers by constants hw/ide: Extract bmdma_status_writeb() hw/ide: Extract IDEBus assignment into bmdma_init() hw/isa/vt82c686: Remove via_isa_set_irq() hw/ide/via: Wire up IDE legacy interrupts in host device hw/ide/pci: Expose legacy interrupts as named GPIOs target/mips: enable GINVx support for I6400 and I6500 target/mips/mxu: Add Q8SAD instruction target/mips/mxu: Add S32SFL instruction target/mips/mxu: Add Q8MADL instruction target/mips/mxu: Add Q16SCOP instruction target/mips/mxu: Add Q8MAC Q8MACSU instructions target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructions target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructions target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructions target/mips/mxu: Add D32SLL D32SLR D32SAR instructions target/mips/mxu: Add D32SARL D32SARW instructions target/mips/mxu: Add S32ALN S32LUI insns target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insns ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-11hw/ide/piix: Move registration of VMStateDescription to DeviceClassBernhard Beschow
The modern, declarative way to set up VM state handling is to assign to DeviceClass::vmsd attribute. There shouldn't be any change in behavior since dc->vmsd causes vmstate_register_with_alias_id() to be called on the instance during the instance init phase. vmstate_register() was also called during the instance init phase which forwards to vmstate_register_with_alias_id() internally. Checking the migration schema before and after this patch confirms: before: > qemu-system-x86_64 -S > qemu > migrate -d exec:cat>before.mig after: > qemu-system-x86_64 -S > qemu > migrate -d exec:cat>after.mig > analyze-migration.py -d desc -f before.mig > before.json > analyze-migration.py -d desc -f after.mig > after.json > diff before.json after.json -> empty Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20230531211043.41724-8-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-11hw/ide/pci: Replace some magic numbers by constantsBernhard Beschow
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20230531211043.41724-7-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-11hw/ide: Extract bmdma_status_writeb()Bernhard Beschow
Every TYPE_PCI_IDE device performs the same not-so-trivial bit manipulation by copy'n'paste code. Extract this into bmdma_status_writeb(), mirroring bmdma_cmd_writeb(). Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <20230531211043.41724-6-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-11hw/ide: Extract IDEBus assignment into bmdma_init()Bernhard Beschow
Every invocation of bmdma_init() is followed by `d->bmdma[i].bus = &d->bus[i]`. Resolve this redundancy by extracting it into bmdma_init(). Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20230531211043.41724-5-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-11hw/isa/vt82c686: Remove via_isa_set_irq()Bernhard Beschow
Now that via_isa_set_irq() is unused it can be removed. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20230531211043.41724-4-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-11hw/ide/via: Wire up IDE legacy interrupts in host deviceBernhard Beschow
Resolves circular depencency between IDE function and south bridge. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20230531211043.41724-3-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-11hw/ide/pci: Expose legacy interrupts as named GPIOsBernhard Beschow
Exposing the legacy IDE interrupts as GPIOs allows them to be connected in the parent device through qdev_connect_gpio_out(), i.e. without accessing private data of TYPE_PCI_IDE. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20230531211043.41724-2-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips: enable GINVx support for I6400 and I6500Marcin Nowakowski
GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores, so indicate that properly in CP0.Config5 register bits [16:15]. Cc: qemu-stable@nongnu.org Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230630072806.3093704-1-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q8SAD instructionSiarhei Volkau
The instruction implements SAD (sum-absolute-difference) operation which is used in motion estimation algorithms. The instruction handles four 8-bit data in parallel. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-34-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32SFL instructionSiarhei Volkau
The instruction shuffles 8 bytes in two registers by one of 4 predefined patterns. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-33-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q8MADL instructionSiarhei Volkau
The instruction is used to parallel multiply and accumulate four 8-bit data. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-32-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q16SCOP instructionSiarhei Volkau
The instruction is used to determine sign of four 16-bit packed data in parallel. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-31-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q8MAC Q8MACSU instructionsSiarhei Volkau
These instructions do parallel quad 8-bit multiply and accumulate. They are close to existing Q8MUL Q8MULSU so the generation function modified to support all of them. Also the patch fixes decoding of Q8MULSU according to tests on hardware. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-30-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32/D16/Q8- MOVZ/MOVN instructionsSiarhei Volkau
These instructions are: - single 32-bit - dual 16-bit packed - quad 8-bit packed conditional moves. They are grouped in pool20 in the source code. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-29-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D32/Q16- SLLV/SLRV/SARV instructionsSiarhei Volkau
These instructions are counterparts for D32/Q16-SLL/SLR/SAR with difference that the shift amount placed into GPR. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-28-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q16SLL Q16SLR Q16SAR instructionsSiarhei Volkau
These instructions are same data shift in various directions, thus one generation function is implemented for all three. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-27-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D32SLL D32SLR D32SAR instructionsSiarhei Volkau
These instructions are same data shift in various directions, thus one generation function is implemented for all three. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-26-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D32SARL D32SARW instructionsSiarhei Volkau
These instructions are dual 32-bit arithmetic shift right and pack LSBs to 2x 16-bit into a MXU register. The difference is the shift amount source: immediate or GP reg. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-25-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32ALN S32LUI insnsSiarhei Volkau
These instructions are part of pool16, see the grand opcode organization tree on top of the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-24-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32MUL S32MULU S32EXTR S32EXTRV insnsSiarhei Volkau
These instructions are part of pool15, see the grand opcode organization tree on top of the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-23-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S16LDD S16STD S16LDI S16SDI instructionsSiarhei Volkau
These instructions are all load/store a halfword from memory and put it into/get it from MXU register in various combinations. I-suffix instructions modify the base address GPR by offset provided. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-22-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S8STD S8LDI S8SDI instructionsSiarhei Volkau
These instructions are all load/store a byte from memory and put it into/get it from MXU register in various combinations. I-suffix instructions modify the base address GPR by offset provided. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-21-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q8ADDE Q8ACCE D8SUM D8SUMC instructionsSiarhei Volkau
These instructions are all dual 8-bit addition/subtraction in various combinations. Most instructions are grouped in pool14, see the opcode organization in the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-20-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q16ACC Q16ACCM D16ASUM instructionsSiarhei Volkau
These instructions are all dual 16-bit addition/subtraction in various combinations. The instructions are grouped in pool13, see the opcode organization in the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-19-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D32ADDC instructionSiarhei Volkau
The instruction adds two 32-bit values with respect to corresponding carry flags in MXU_CR. XRa += XRb + LeftCarry flag; XRd += XRc + RightCarry flag; Suddenly, it doesn't modify carry flags as a result of addition. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-18-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D32ACC D32ACCM D32ASUM instructionsSiarhei Volkau
These instructions are all dual 32-bit addition/subtraction in various combinations. The instructions are grouped in pool12, see the opcode organization in the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-17-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D32ADD instructionSiarhei Volkau
The instruction adds/subtracts two 32-bit values in XRb and XRc. Placing results in XRa and XRd and updates carry bits for each path in the MXU control register. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-16-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q16ADD instructionSiarhei Volkau
The instruction adds/subtracts four 16-bit packed in XRb and XRc. Placing packed 16-bit results in XRa and XRd. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-15-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S16MAD instructionSiarhei Volkau
The instruction is similar to multiply and accumulate but works with MXU registers set. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-14-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D16MADL instructionSiarhei Volkau
The instruction is similar to multiply and accumulate but works with MXU registers set. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-13-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D16MACF D16MACE instructionsSiarhei Volkau
These instructions are close to D16MAC so common generation function provided. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-12-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add D16MULF D16MULE instructionsSiarhei Volkau
These instructions are part of pool3, see the grand tree above in the file. The instructions are close to D16MUL so common generation function provided. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-11-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32CPS D16CPS Q8ABD Q16SAT insnsSiarhei Volkau
These instructions are part of pool2, see the grand tree above in the file. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-10-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q8ADD instructionSiarhei Volkau
This instruction is used to add/subtract quadruple 8-bit values to another quadruple in parallel. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-9-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insnsSiarhei Volkau
These instructions are part of pool1, see the grand tree above in the file. Q8ADD is part of pool1 too but belong to another category of instructions, thus will be made in later patches. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-8-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Fix D16MAX D16MIN Q8MAX Q8MIN instructionsSiarhei Volkau
These instructions were designed that they overwrite source register during partial storing of result. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-7-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add Q8SLT Q8SLTU instructionsSiarhei Volkau
These instructions are used to set bits depending on comparison result in each byte respectively. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-6-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add S32MADD/MADDU/MSUB/MSUBU instructionsSiarhei Volkau
These instructions used to multiply 2x32-bit GPR sources & accumulate result into 64-bit pair of XRF registers. These instructions stain HI/LO registers with the final result. Their opcode is close to the MIPS32R1 MADD[U]/MSUB[U], so it have to call decode_opc_special2_legacy when failing to find MXU opcode. Moreover, it solves issue with reinventing MUL and malfunction MULU/CLZ/CLO instructions. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-5-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips/mxu: Add LXW LXB LXH LXBU LXHU instructionsSiarhei Volkau
These instructions used to load from memory to GPR via indexed address divided by base and index parts in GPR registers. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-4-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips: Add support of two XBurst CPUsSiarhei Volkau
XBurstR1 - is the MIPS32R1 CPU which aims to cover all Ingenic SoCs older than JZ4770 and some newer. XBurstR2 - is the MIPS32R2 CPU which aims to cover all Ingenic SoCs starting from to JZ4770. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-3-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips: Add emulation of MXU instructions for 32-bit load/storeSiarhei Volkau
Add support for emulating: - S32LDDV and S32LDDVR - S32STD and S32STDR - S32STDV and S32STDVR MXU instructions. Add support for emulating MXU instructions with address register post-modify counterparts: - S32LDI and S32LDIR - S32LDIV and S32LDIVR - S32SDI and S32SDIR - S32SDIV and S32SDIVR Refactor support for emulating the S32LDD and S32LDDR instructions. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-2-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10hw/mips/loongson3_virt: Relax CPU restrictions for TCGJiaxun Yang
After implemented CPUCFG and CSR, we are now able to boot Linux kernel with Loongson-3A4000 CPU, so there is no point to restrict CPU type to 3A1000 only, instead we just check for presence of INSN_LOONGSON3A. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20230521214832.20145-3-jiaxun.yang@flygoat.com> [JY: Check for cpu_type_supports_isa(INSN_LOONGSON3A)] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips: Implement Loongson CSR instructionsJiaxun Yang
Loongson introduced CSR instructions since 3A4000, which looks similar to IOCSR and CPUCFG instructions we seen in LoongArch. Unfortunately we don't have much document about those instructions, bit fields of CPUCFG instructions and IOCSR registers can be found at 3A4000's user manual, while instruction encodings can be found at arch/mips/include/asm/mach-loongson64/loongson_regs.h from Linux Kernel. Our predefined CPUCFG bits are differ from actual 3A4000, since we can't emulate all CPUCFG features present in 3A4000 for now, we just enable bits for what we have in TCG. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20230521214832.20145-2-jiaxun.yang@flygoat.com> [JY: Fixed typo in ase_lcsr_available(), retrict GEN_FALSE_TRANS] [PMD: Fix meson's mips_softmmu_ss -> mips_system_ss, restrict AddressSpace/MemoryRegion to SysEmu] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10Merge tag 'qga-pull-2023-07-10' of https://github.com/kostyanf14/qemu into ↵Richard Henderson
staging qga-pull-2023-07-10 # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEwsLBCepDxjwUI+uE711egWG6hOcFAmSsBN8ACgkQ711egWG6 # hOfGzw/9HJl1sQQQWO/Nv3HOtiC7Nnk3d06Wx8nC3d3L4fyDDsyCm1gBQK2YX6x5 # jlDCwgf28DoSDgvznyRvoUrDaQ4QBwcd2Xc5ukQRxZ4K2zEfWjp/NI7AWzUxQ2ID # G1dAWrnY94qm8vkkjAV6ABpDZNMWQlahwcABG8S5rFWaIqv+TSsFD9qRbrcA/LsJ # hKbcGSuWEzQSYcFD4ctGbQP4JgQQOO5Yk/3S7PO0+j/04vaYoers/9ZhRc8WhxGs # WAqxMdmUMcuYU0VkDLRVaGfJ5TrlHqm/iHz9UnTNbWekGjeNiEMyGN3shWCKN2AE # mMXU2zd74dBdMhwIzSlz7MW0XuX3TLrI3DZ9W7lY+8FfafQi8Dd2FPfPdKNDhEp0 # NQ8N/W6LAXPkVWci3uSvw50K+Q0svWee6mZV3qI6DbD1a8dRKvlFvvL7FCvHt8eF # 7YIHanJEzHbday31dhaRBBDn0EehBsFiJVImyfKBrMxGPfhTva+rH4KWKIW2pGfU # 3Sqk3KJ+c0Byh1Rkv6LTeYQSUV4x/fwve/EnvBhau1CyuoFSR0/Eoyqzi3aX3koL # Ord9BUGgmEc3TzDj0LhonEWnlWmNcUm/ck9dZTkYcDWyLLaArJ5pW9iUU9eh9Vx/ # 56r3/Jyz4QM6CjFmWWGEsEFMrM0wMGxl9JQKRcc39Eo2GpgWtuI= # =zeI3 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 10 Jul 2023 02:17:19 PM BST # gpg: using RSA key C2C2C109EA43C63C1423EB84EF5D5E8161BA84E7 # gpg: Good signature from "Kostiantyn Kostiuk (Upstream PR sign) <kkostiuk@redhat.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: C2C2 C109 EA43 C63C 1423 EB84 EF5D 5E81 61BA 84E7 * tag 'qga-pull-2023-07-10' of https://github.com/kostyanf14/qemu: QGA VSS: Add log in functions begin/end QGA VSS: Print error in err_set QGA VSS: Replace 'fprintf(stderr' with qga_debug QGA VSS: Add wrapper to send log to debugger and stderr qga: Add tests for --allow-rpcs option qga: Add new option --allow-rpcs qga: Rename ga_disable_not_allowed -> ga_disable_not_allowed_freeze Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-10Merge tag 'pull-riscv-to-apply-20230710-1' of ↵Richard Henderson
https://github.com/alistair23/qemu into staging Third RISC-V PR for 8.1 * Use xl instead of mxl for disassemble * Factor out extension tests to cpu_cfg.h * disas/riscv: Add vendor extension support * disas/riscv: Add support for XVentanaCondOps * disas/riscv: Add support for XThead* instructions * Fix mstatus related problems * Fix veyron-v1 CPU properties * Fix the xlen for data address when MPRV=1 * opensbi: Upgrade from v1.2 to v1.3 * Enable 32-bit Spike OpenSBI boot testing * Support the watchdog timer of HiFive 1 rev b * Only build qemu-system-riscv$$ on rv$$ host * Add RVV registers to log * Restrict ACLINT to TCG * Add syscall riscv_hwprobe * Add support for BF16 extensions * KVM_RISCV_SET_TIMER macro is not configured correctly * Generate devicetree only after machine initialization is complete * virt: Convert fdt_load_addr to uint64_t * KVM: fixes and enhancements * Add support for the Zfa extension # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmSr+ekACgkQr3yVEwxT # gBMMGg//ZCcyH3KXB49c2KUIFO6FKYUxN9uC3giZCtuGyEH8T2yDgZVVXnxwU+Ij # +3Ej6T/ZdWMpePC9qf+xKzHWZk7Qc8Tcg+JgQbga573894yZInRwYl8HsSlEKA+Z # vlqSBPxTlp9rlDwGP/LjGljyIFqL4konk9zi3FL4ZXTF1iHUGrh/953Y3wIreEfl # KX5UznnWcgy2BqQT1vihMbM8qCVK6iryH+QZ6LiAsPMSX1rIzk8ectQryILzoIYh # bMiwCLVMyr4ZrUXjmGTF+7/WcOWwhhyfpdstf2iotKALelZtVHit0wHcty2GYQde # nvN83jJWu04DGXkPBUsqCUQXczGo1QHjJUH3RIRJzfOby/lGt4pSzHAfKA+iNUht # ikM3SdBsXMO+ogjTtTcCMb7/m2vsMoQP60VRts9Mh3YVD0cgr7RqpqRoEMugVYnr # ca8Vijf71mB+y+pq477eV1Q8BoKpr8xa1OlFkNKPC17uMD7HoDMI44QgFOgtYp10 # TMsqqyB75q6PZhSEwm63xbmH0Zpo8kSqT/E3MTtGTyPeuL8TNNNSkCmFaGYmRrbI # XEp7vG2RaDJOvDomS3nUhA5ruc8SaXd0q25q2gLYQfCsehfFqZAwuNB5xf1zS0M0 # ov1/gwaqU93t6nLbo2cCbb0plkIFKwwJ9KKjD06wJ4KPe0TGFzk= # =3XFD # -----END PGP SIGNATURE----- # gpg: Signature made Mon 10 Jul 2023 01:30:33 PM BST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20230710-1' of https://github.com/alistair23/qemu: (54 commits) riscv: Add support for the Zfa extension target/riscv/kvm.c: read/write (cbom|cboz)_blocksize in KVM target/riscv/kvm.c: add kvmconfig_get_cfg_addr() helper target/riscv: update multi-letter extension KVM properties target/riscv/cpu.c: create KVM mock properties target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext() target/riscv/cpu.c: add satp_mode properties earlier target/riscv/kvm.c: add multi-letter extension KVM properties target/riscv/kvm.c: update KVM MISA bits target/riscv: add KVM specific MISA properties target/riscv/cpu: add misa_ext_info_arr[] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids() target/riscv: use KVM scratch CPUs to init KVM properties target/riscv/cpu.c: restrict 'marchid' value target/riscv/cpu.c: restrict 'mimpid' value target/riscv/cpu.c: restrict 'mvendorid' value hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set target/riscv: skip features setup for KVM CPUs ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-10target/mips: Rework cp0_timer with clock APIJiaxun Yang
Previous implementation of MIPS cp0_timer computes a cp0_count_ns based on input clock. However rounding error of cp0_count_ns can affect precision of cp0_timer. Using clock API and a divider for cp0_timer, so we can use clock_ns_to_ticks/clock_ns_to_ticks to avoid rounding issue. Also workaround the situation that in such handler flow: count = read_c0_count() write_c0_compare(count) If timer had not progressed when compare was written, the interrupt would trigger again. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230521110037.90049-1-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10Merge tag 'pull-request-2023-07-10v2' of https://gitlab.com/thuth/qemu into ↵Richard Henderson
staging * s390x instruction emulation fixes and corresponding TCG tests * Extend the readconfig qtest * Introduce "-run-with chroot=..." and deprecate the old "-chroot" option * Speed up migration tests * Fix coding style in the coding style document # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmSsCYQRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbUhLw/+Mg74FGODwb/kdPSSY+ahEmutRaQG5z74 # zWnHFYTB0xLRxu5gwV09wcFt88RjkkdsKORtp1LBRahVaKYzYSq3PxMYsDii2pdr # Ma58RLZC/42shrzZmXEyl3ilxCCHjq2UCezX+4ca/zuTl/83znVN6Mrq28GUmp7v # 8yI78mPpZXEkLEN3cnnK3v7AsLwz439aHd3ADZ1IWUohGHQdDAj4nn5Yxp4SeIUj # sOmCcEfLj3emNM/TTL2suohuZNwYjyLQ5iqQJ/B7v/S88PbWQUA9Cq/KpEGBLk/D # fxDjbQ7+zpTTSQ+XihShtGdEnl4uPPixvJX43vriYDBQFsHKS7Y38cSAFVTDrQvh # 4fELCAPg8wXeoyMu7WZWINDA6dVdInCdmljHYpK+mQg7AtHu/CliPWzVUZyeW3XD # lwybNCoyJQcA4KPAyYrkau74JrLRGtLJJQ5XtQEDsK791xjeHt1hr42QY4YeHyjM # Utf6inp4D7RZ3O9p5EeKNVpFin5AE+RTvNZKLJicFRb0hFziUkCK61nRwS5gmvXA # I41av1L+mLI7jvu0M2ID1CfIhFf+/w4GKNkUlcutux7uz5mzxIj0oifsONEZGNo+ # NlVKKNxfQv2eRl+9sZPWNl8q11K3bvZbpvXZS5oSLIererWIIROaxcgzxpU+EGLT # 8HhF7RZdO8w= # =LLmM # -----END PGP SIGNATURE----- # gpg: Signature made Mon 10 Jul 2023 02:37:08 PM BST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [undefined] # gpg: aka "Thomas Huth <thuth@redhat.com>" [undefined] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2023-07-10v2' of https://gitlab.com/thuth/qemu: (21 commits) docs/devel: Fix coding style in style.rst tests/qtest: massively speed up migration-test tests/tcg/s390x: Fix test-svc with clang meson.build: Skip C++ detection unless we're targeting Windows os-posix: Allow 'chroot' via '-run-with' and deprecate the old '-chroot' option tests/qtest/readconfig: Test the docs/config/q35-*.cfg files tests/qtest: Move mkimg() and have_qemu_img() from libqos to libqtest tests/qtest/readconfig-test: Allow testing for arbitrary memory sizes tests/tcg/s390x: Test MVCRL with a large value in R0 tests/tcg/s390x: Test MDEB and MDEBR tests/tcg/s390x: Test LRA tests/tcg/s390x: Test LARL with a large offset tests/tcg/s390x: Test EPSW target/s390x: Fix relative long instructions with large offsets target/s390x: Fix LRA when DAT is off target/s390x: Fix LRA overwriting the top 32 bits on DAT error target/s390x: Fix MVCRL with a large value in R0 target/s390x: Fix MDEB and MDEBR target/s390x: Fix EPSW CC reporting linux-user: elfload: Add more initial s390x PSW bits ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-10docs/devel: Fix coding style in style.rstThomas Huth
As defined earlier in this file, the opening curly brace of functions should be placed on a separate line. So we should do it in the examples here, too. Fixes: 821f296756 ("docs: document use of automatic cleanup functions in glib") Reported-by: Konstantin Kostiuk <kkostiuk@redhat.com> Message-Id: <20230710092638.161625-1-thuth@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-07-10tests/qtest: massively speed up migration-testDaniel P. Berrangé
The migration test cases that actually exercise live migration want to ensure there is a minimum of two iterations of pre-copy, in order to exercise the dirty tracking code. Historically we've queried the migration status, looking for the 'dirty-sync-count' value to increment to track iterations. This was not entirely reliable because often all the data would get transferred quickly enough that the migration would finish before we wanted it to. So we massively dropped the bandwidth and max downtime to guarantee non-convergance. This had the unfortunate side effect that every migration took at least 30 seconds to run (100 MB of dirty pages / 3 MB/sec). This optimization takes a different approach to ensuring that a mimimum of two iterations. Rather than waiting for dirty-sync-count to increment, directly look for an indication that the source VM has dirtied RAM that has already been transferred. On the source VM a magic marker is written just after the 3 MB offset. The destination VM is now montiored to detect when the magic marker is transferred. This gives a guarantee that the first 3 MB of memory have been transferred. Now the source VM memory is monitored at exactly the 3MB offset until we observe a flip in its value. This gives us a guaranteed that the guest workload has dirtied a byte that has already been transferred. Since we're looking at a place that is only 3 MB from the start of memory, with the 3 MB/sec bandwidth, this test should complete in 1 second, instead of 30 seconds. Once we've proved there is some dirty memory, migration can be set back to full speed for the remainder of the 1st iteration, and the entire of the second iteration at which point migration should be complete. On a test machine this further reduces the migration test time from 8 minutes to 1 minute 40. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20230601161347.1803440-11-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-24 07:52:24 +0000