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2020-02-28hw: Do not initialize MachineClass::is_default to 0Philippe Mathieu-Daudé
The MachineClass is already zeroed on creation. Note: The code setting is_default=0 in hw/i386/pc_piix.c is different (related to compat options). When adding a new versioned machine, we want it to be the new default, so we have to mark the previous one as not default. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20200207161948.15972-2-philmd@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-02-28hw/nmi: Fix the NMI() macro, based on INTERFACE_CHECK()Philippe Mathieu-Daudé
There is no declaration of the 'NMI' type. INTERFACE_CHECK() returns an abstract type (see commit aa1b35b975d8). The abstract type corresponding to the TYPE_NMI interface is 'NMIState'. Fixes: 9cb805fd267 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20191207094823.20707-1-philmd@redhat.com> Reviewed-by: Gavin Shan <gshan@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2020-02-28Merge remote-tracking branch ↵Peter Maydell
'remotes/pmaydell/tags/pull-target-arm-20200228' into staging target-arm queue: * hw/arm: Use TYPE_PL011 to create serial port * target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn * hw/arm/integratorcp: Map the audio codec controller * GICv2: Correctly implement the limited number of priority bits * target/arm: refactoring of VFP related feature checks and decode * xilinx_zynq: Fix USB port instantiation * acceptance tests for n800, n810, integratorcp * Implement v8.3-RCPC, v8.4-RCPC, v8.3-CCIDX * arm_gic_kvm: Don't assume kernel can provide a GICv2 (provide better error message for user error) # gpg: Signature made Fri 28 Feb 2020 16:38:04 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20200228: (33 commits) hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 target/arm: Implement ARMv8.3-CCIDX target/arm: Implement v8.4-RCPC target/arm: Implement v8.3-RCPC target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer tests/acceptance: Extract boot_integratorcp() from test_integratorcp() tests/acceptance: Add a test for the integratorcp arm machine tests/acceptance: Add a test for the N800 and N810 arm machines hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class hw/arm/xilinx_zynq: Fix USB port instantiation target/arm: Split VMINMAXNM decode target/arm: Split VFM decode target/arm: Add formats for some vfp 2 and 3-register insns target/arm: Remove ARM_FEATURE_VFP* linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP target/arm: Move the vfp decodetree calls next to the base isa target/arm: Move VLLDM and VLSTM to vfp.decode target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2Peter Maydell
In our KVM GICv2 realize function, we try to cope with old kernels that don't provide the device control API (KVM_CAP_DEVICE_CTRL): we try to use the device control, and if that fails we fall back to assuming that the kernel has the old style KVM_CREATE_IRQCHIP and that it will provide a GICv2. This doesn't cater for the possibility of a kernel and hardware which only provide a GICv3, which is very common now. On that setup we will abort() later on in kvm_arm_pmu_set_irq() when we try to wire up an interrupt to the GIC we failed to create: qemu-system-aarch64: PMU: KVM_SET_DEVICE_ATTR: Invalid argument qemu-system-aarch64: failed to set irq for PMU Aborted If the kernel advertises KVM_CAP_DEVICE_CTRL we should trust it if it says it can't create a GICv2, rather than assuming it has one. We can then produce a more helpful error message including a hint about the most probable reason for the failure. If the kernel doesn't advertise KVM_CAP_DEVICE_CTRL then it is truly ancient by this point but we might as well still fall back to a KVM_CREATE_IRQCHIP GICv2. With this patch then the user misconfiguration which previously caused an abort now prints: qemu-system-aarch64: Initialization of device kvm-arm-gic failed: error creating in-kernel VGIC: No such device Perhaps the host CPU does not support GICv2? Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Tested-by: Andrew Jones <drjones@redhat.com> Message-id: 20200225182435.1131-1-peter.maydell@linaro.org
2020-02-28target/arm: Implement ARMv8.3-CCIDXPeter Maydell
The ARMv8.3-CCIDX extension makes the CCSIDR_EL1 system ID registers have a format that uses the full 64 bit width of the register, and adds a new CCSIDR2 register so AArch32 can get at the high 32 bits. QEMU doesn't implement caches, so we just treat these ID registers as opaque values that are set to the correct constant values for each CPU. The only thing we need to do is allow 64-bit values in our cssidr[] array and provide the CCSIDR2 accessors. We don't set the CCIDX field in our 'max' CPU because the CCSIDR constant values we use are the same as the ones used by the Cortex-A57 and they are in the old 32-bit format. This means that the extra regdef added here is unused currently, but it means that whenever in the future we add a CPU that does need the new 64-bit format it will just work when we set the cssidr values and the ID registers for it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224182626.29252-1-peter.maydell@linaro.org
2020-02-28target/arm: Implement v8.4-RCPCPeter Maydell
The v8.4-RCPC extension implements some new instructions: * LDAPUR, LDAPURB, LDAPURH, LDAPRSB, LDAPRSH, LDAPRSW * STLUR, STLURB, STLURH These are all in a new subgroup of encodings that sits below the top-level "Loads and Stores" group in the Arm ARM. The STLUR* instructions have standard store-release semantics; the LDAPUR* have Load-AcquirePC semantics, but (as with LDAPR*) we choose to implement them as the slightly stronger Load-Acquire. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224172846.13053-4-peter.maydell@linaro.org
2020-02-28target/arm: Implement v8.3-RCPCPeter Maydell
The v8.3-RCPC extension implements three new load instructions which provide slightly weaker consistency guarantees than the existing load-acquire operations. For QEMU we choose to simply implement them with a full LDAQ barrier. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224172846.13053-3-peter.maydell@linaro.org
2020-02-28target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0Peter Maydell
We missed an instance of using FIELD_EX32 on a 64-bit ID register, in isar_feature_aa64_pmu_8_4(). Fix it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224172846.13053-2-peter.maydell@linaro.org
2020-02-28tests/acceptance/integratorcp: Verify Tux is displayed on framebufferPhilippe Mathieu-Daudé
Add a test that verifies the Tux logo is displayed on the framebuffer. We simply follow the OpenCV "Template Matching with Multiple Objects" tutorial, replacing Lionel Messi by Tux: https://docs.opencv.org/4.2.0/d4/dc6/tutorial_py_template_matching.html When OpenCV and NumPy are installed, this test can be run using: $ AVOCADO_ALLOW_UNTRUSTED_CODE=hmmm \ avocado --show=app,framebuffer run -t device:framebuffer \ tests/acceptance/machine_arm_integratorcp.py JOB ID : 8c46b0f8269242e87d738247883ea2a470df949e JOB LOG : avocado/job-results/job-2020-01-31T21.38-8c46b0f/job.log (1/1) tests/acceptance/machine_arm_integratorcp.py:IntegratorMachine.test_framebuffer_tux_logo: framebuffer: found Tux at position [x, y] = (0, 0) PASS (3.96 s) RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0 JOB TIME : 4.23 s Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Message-id: 20200225172501.29609-5-philmd@redhat.com Message-Id: <20200131211102.29612-3-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28tests/acceptance: Extract boot_integratorcp() from test_integratorcp()Philippe Mathieu-Daudé
As we want to re-use this code, extract it as a new function. Since we are using the PL011 serial console, add a Avocado tag to ease filtering of tests. Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200225172501.29609-4-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28tests/acceptance: Add a test for the integratorcp arm machineThomas Huth
There is a kernel and initrd available on github which we can use for testing this machine. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200225172501.29609-3-philmd@redhat.com Message-Id: <20200131170233.14584-1-thuth@redhat.com> [PMD: Renamed test method, moved description from class to method] Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28tests/acceptance: Add a test for the N800 and N810 arm machinesThomas Huth
Old kernels from the Meego project can be used to check that Linux is at least starting on these machines. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200225172501.29609-2-philmd@redhat.com Message-Id: <20200129131920.22302-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb classGuenter Roeck
Xilinx USB devices are now instantiated through TYPE_CHIPIDEA, and xlnx support in the EHCI code is no longer needed. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20200215122354.13706-3-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28hw/arm/xilinx_zynq: Fix USB port instantiationGuenter Roeck
USB ports on Xilinx Zync must be instantiated as TYPE_CHIPIDEA to work. Linux expects and checks various chipidea registers, which do not exist with the basic ehci emulation. This patch series fixes the problem. Without this patch, USB ports fail to instantiate under Linux. ci_hdrc ci_hdrc.0: doesn't support host ci_hdrc ci_hdrc.0: no supported roles With this patch, USB ports are instantiated, and it is possible to boot from USB drive. ci_hdrc ci_hdrc.0: EHCI Host Controller ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1 ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00 usb 1-1: new full-speed USB device number 2 using ci_hdrc usb 1-1: not running at top speed; connect to a high speed hub usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x81 has invalid maxpacket 512, setting to 64 usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x2 has invalid maxpacket 512, setting to 64 usb-storage 1-1:1.0: USB Mass Storage device detected scsi host0: usb-storage 1-1:1.0 Signed-off-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20200215122354.13706-2-linux@roeck-us.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Split VMINMAXNM decodeRichard Henderson
Passing the raw op field from the manual is less instructive than it might be. Do the full decode and use the existing helpers to perform the expansion. Since these are v8 insns, VECLEN+VECSTRIDE are already RES0. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224222232.13807-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Split VFM decodeRichard Henderson
Passing the raw o1 and o2 fields from the manual is less instructive than it might be. Do the full decode and let the trans_* functions pass in booleans to a helper. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224222232.13807-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Add formats for some vfp 2 and 3-register insnsRichard Henderson
Those vfp instructions without extra opcode fields can share a common @format for brevity. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224222232.13807-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Remove ARM_FEATURE_VFP*Richard Henderson
We have converted all tests against these features to ISAR tests. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224222232.13807-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAPRichard Henderson
Use isar feature tests instead of feature bit tests. Although none of QEMUs current cpus have VFPv3 without D32, replace the large comment explaining why with one line that sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions. Mirror the test sequence used in the linux kernel. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200224222232.13807-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Move the vfp decodetree calls next to the base isaRichard Henderson
Have the calls adjacent as an intermediate step toward actually merging the decodes. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200224222232.13807-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Move VLLDM and VLSTM to vfp.decodeRichard Henderson
Now that we no longer have an early check for ARM_FEATURE_VFP, we can use the proper ISA check in trans_VLLDM_VLSTM. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200224222232.13807-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insnRichard Henderson
We now have proper ISA checks within each trans_* function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224222232.13807-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmacRichard Henderson
All remaining tests for VFP4 are for fused multiply-add insns. Since the MVFR1 field is used for both VFP and NEON, move its adjustment from the !has_neon block to the (!has_vfp && !has_neon) block. Test for vfp of the appropraite width alongside the test for simdfmac within translate-vfp.inc.c. Within disas_neon_data_insn, we have already tested for ARM_FEATURE_NEON. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200224222232.13807-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Add missing checks for fpsp_v2Richard Henderson
We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224222232.13807-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3Richard Henderson
Sort this check to the start of a trans_* function. Merge this with any existing test for fpdp_v2. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224222232.13807-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Perform fpdp_v2 check firstRichard Henderson
Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224222232.13807-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfpRichard Henderson
We cannot easily create "any" functions for these, because the ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero. Which means that an aarch32-only cpu will return incorrect results when testing the aarch64 registers. To use these, we must either have context or additionally test vs ARM_FEATURE_AARCH64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200224222232.13807-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3}Richard Henderson
We will shortly use these to test for VFPv2 and VFPv3 in different situations. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224222232.13807-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Rename isar_feature_aa32_fpdp_v2Richard Henderson
The old name, isar_feature_aa32_fpdp, does not reflect that the test includes VFPv2. We will introduce another feature tests for VFPv3. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200224222232.13807-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Add isar_feature_aa32_vfp_simdRichard Henderson
Use this in the places that were checking ARM_FEATURE_VFP, and are obviously testing for the existance of the register set as opposed to testing for some particular instruction extension. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20200224222232.13807-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28cpu/arm11mpcore: Set number of GIC priority bits to 4Sai Pavan Boddu
The GIC built into the ARM11MPCore is always implemented with 4 priority bits; set the GIC property accordingly. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1582537164-764-4-git-send-email-sai.pavan.boddu@xilinx.com Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: tweaked commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28cpu/a9mpcore: Set number of GIC priority bits to 5Sai Pavan Boddu
All A9 CPUs have a GIC with 5 bits of priority. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1582537164-764-3-git-send-email-sai.pavan.boddu@xilinx.com Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28arm_gic: Mask the un-supported priority bitsSai Pavan Boddu
The GICv2 allows the implementation to implement a variable number of priority bits; unimplemented bits in the priority registers are read as zeros, writes ignored. We were previously always implementing a full 8 bits of priority, which is allowed but not what the real hardware typically does (which is usually to have 4 or 5 bits of priority). Add a new device property to allow the number of implemented property bits to be specified. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Message-id: 1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: improved commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28hw/arm/integratorcp: Map the audio codec controllerPhilippe Mathieu-Daudé
The Linux kernel displays errors why trying to detect the PL041 audio interface: Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018 CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00093177 CPU: VIVT data cache, VIVT instruction cache OF: fdt: Machine model: ARM Integrator/CP ... OF: amba_device_add() failed (-19) for /fpga/aaci@1d000000 Since we have it already modelled, simply plug it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200223233033.15371-2-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfnRichard Henderson
We had set this for aarch32-only in arm_max_initfn, but failed to set the same bit for aarch64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200218190958.745-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28hw/arm: Use TYPE_PL011 to create serial portGavin Shan
This uses TYPE_PL011 when creating the serial port so that the code looks cleaner. Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20200224222223.4128-1-gshan@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28Merge remote-tracking branch ↵Peter Maydell
'remotes/juanquintela/tags/pull-migration-pull-request' into staging Migration pull request # gpg: Signature made Fri 28 Feb 2020 09:21:31 GMT # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full] # gpg: aka "Juan Quintela <quintela@trasno.org>" [full] # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * remotes/juanquintela/tags/pull-migration-pull-request: savevm: Don't call colo_init_ram_cache twice migration/colo: wrap incoming checkpoint process into new helper migration: fix COLO broken caused by a previous commit migration/block: rename BLOCK_SIZE macro migration/savevm: release gslist after dump_vmstate_json test-vmstate: Fix memleaks in test_load_qlist migration/vmstate: Remove redundant statement in vmstate_save_state_v() multifd: Add zstd compression multifd support multifd: Add multifd-zstd-level parameter configure: Enable test and libs for zstd multifd: Add zlib compression multifd support multifd: Add multifd-zlib-level parameter multifd: Make no compression operations into its own structure migration: Add support for modules multifd: Add multifd-compression parameter Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-27-2020' ↵Peter Maydell
into staging MIPS queue for February 27th, 2020 # gpg: Signature made Thu 27 Feb 2020 13:20:55 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full] # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-feb-27-2020: tests/acceptance: Count multiple Tux logos displayed on framebuffer hw/mips: Use memory_region_init_rom() with read-only regions hw/mips/mips_int: Simplify cpu_mips_irq_init_cpu() MAINTAINERS: Reactivate MIPS KVM CPUs MAINTAINERS: Orphan MIPS KVM CPUs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20200227' into ↵Peter Maydell
staging Xen queue 2020-02-27 * fix for xen-block * fix in exec.c for migration of xen guest * one cleanup patch # gpg: Signature made Thu 27 Feb 2020 11:57:12 GMT # gpg: using RSA key F80C006308E22CFD8A92E7980CF5572FD7FB55AF # gpg: issuer "anthony.perard@citrix.com" # gpg: Good signature from "Anthony PERARD <anthony.perard@gmail.com>" [marginal] # gpg: aka "Anthony PERARD <anthony.perard@citrix.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 5379 2F71 024C 600F 778A 7161 D8D5 7199 DF83 42C8 # Subkey fingerprint: F80C 0063 08E2 2CFD 8A92 E798 0CF5 572F D7FB 55AF * remotes/aperard/tags/pull-xen-20200227: Memory: Only call ramblock_ptr when needed in qemu_ram_writeback xen-bus/block: explicitly assign event channels to an AioContext hw/xen/xen_pt_load_rom: Remove unused includes Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-02-28savevm: Don't call colo_init_ram_cache twicezhanghailiang
This helper has been called twice which is wrong. Left the one where called while get COLO enable message from source side. Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2020-02-28migration/colo: wrap incoming checkpoint process into new helperzhanghailiang
Split checkpoint incoming process into a helper. Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2020-02-28migration: fix COLO broken caused by a previous commitzhanghailiang
This commit "migration: Create migration_is_running()" broke COLO. Becuase there is a process broken by this commit. colo_process_checkpoint ->colo_do_checkpoint_transaction ->migrate_set_block_enabled ->qmp_migrate_set_capabilities It can be fixed by make COLO process as an exception, Maybe we need a better way to fix it. Cc: Juan Quintela <quintela@redhat.com> Signed-off-by: zhanghailiang <zhang.zhanghailiang@huawei.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2020-02-28migration/block: rename BLOCK_SIZE macroStefan Hajnoczi
Both <linux/fs.h> and <sys/mount.h> define BLOCK_SIZE macros. Avoiding using that name in block/migration.c. I noticed this when including <liburing.h> (Linux io_uring) from "block/aio.h" and compilation failed. Although patches adding that include haven't been sent yet, it makes sense to rename the macro now in case someone else stumbles on it in the meantime. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2020-02-28migration/savevm: release gslist after dump_vmstate_jsonPan Nengyuan
'list' forgot to free at the end of dump_vmstate_json_to_file(), although it's called only once, but seems like a clean code. Fix the leak as follow: Direct leak of 16 byte(s) in 1 object(s) allocated from: #0 0x7fb946abd768 in __interceptor_malloc (/lib64/libasan.so.5+0xef768) #1 0x7fb945eca445 in g_malloc (/lib64/libglib-2.0.so.0+0x52445) #2 0x7fb945ee2066 in g_slice_alloc (/lib64/libglib-2.0.so.0+0x6a066) #3 0x7fb945ee3139 in g_slist_prepend (/lib64/libglib-2.0.so.0+0x6b139) #4 0x5585db591581 in object_class_get_list_tramp /mnt/sdb/qemu-new/qemu/qom/object.c:1084 #5 0x5585db590f66 in object_class_foreach_tramp /mnt/sdb/qemu-new/qemu/qom/object.c:1028 #6 0x7fb945eb35f7 in g_hash_table_foreach (/lib64/libglib-2.0.so.0+0x3b5f7) #7 0x5585db59110c in object_class_foreach /mnt/sdb/qemu-new/qemu/qom/object.c:1038 #8 0x5585db5916b6 in object_class_get_list /mnt/sdb/qemu-new/qemu/qom/object.c:1092 #9 0x5585db335ca0 in dump_vmstate_json_to_file /mnt/sdb/qemu-new/qemu/migration/savevm.c:638 #10 0x5585daa5bcbf in main /mnt/sdb/qemu-new/qemu/vl.c:4420 #11 0x7fb941204812 in __libc_start_main ../csu/libc-start.c:308 #12 0x5585da29420d in _start (/mnt/sdb/qemu-new/qemu/build/x86_64-softmmu/qemu-system-x86_64+0x27f020d) Indirect leak of 7472 byte(s) in 467 object(s) allocated from: #0 0x7fb946abd768 in __interceptor_malloc (/lib64/libasan.so.5+0xef768) #1 0x7fb945eca445 in g_malloc (/lib64/libglib-2.0.so.0+0x52445) #2 0x7fb945ee2066 in g_slice_alloc (/lib64/libglib-2.0.so.0+0x6a066) #3 0x7fb945ee3139 in g_slist_prepend (/lib64/libglib-2.0.so.0+0x6b139) #4 0x5585db591581 in object_class_get_list_tramp /mnt/sdb/qemu-new/qemu/qom/object.c:1084 #5 0x5585db590f66 in object_class_foreach_tramp /mnt/sdb/qemu-new/qemu/qom/object.c:1028 #6 0x7fb945eb35f7 in g_hash_table_foreach (/lib64/libglib-2.0.so.0+0x3b5f7) #7 0x5585db59110c in object_class_foreach /mnt/sdb/qemu-new/qemu/qom/object.c:1038 #8 0x5585db5916b6 in object_class_get_list /mnt/sdb/qemu-new/qemu/qom/object.c:1092 #9 0x5585db335ca0 in dump_vmstate_json_to_file /mnt/sdb/qemu-new/qemu/migration/savevm.c:638 #10 0x5585daa5bcbf in main /mnt/sdb/qemu-new/qemu/vl.c:4420 #11 0x7fb941204812 in __libc_start_main ../csu/libc-start.c:308 #12 0x5585da29420d in _start (/mnt/sdb/qemu-new/qemu/build/x86_64-softmmu/qemu-system-x86_64+0x27f020d) Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2020-02-28test-vmstate: Fix memleaks in test_load_qlistChen Qun
There is memleak in test_load_qlist().It's not a big deal, but test-vmstate will fail if sanitizers is enabled. In addition, "ret" is written twice with the same value in test_gtree_load_iommu(). Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2020-02-28migration/vmstate: Remove redundant statement in vmstate_save_state_v()Chen Qun
The "ret" has been assigned in all branches. It didn't need to be assigned separately. Clang static code analyzer show warning: migration/vmstate.c:365:17: warning: Value stored to 'ret' is never read ret = 0; ^ ~ Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com>
2020-02-28multifd: Add zstd compression multifd supportJuan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Acked-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2020-02-28multifd: Add multifd-zstd-level parameterJuan Quintela
This parameter specifies the zstd compression level. The next patch will put it to use. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Acked-by: Markus Armbruster <armbru@redhat.com>
2020-02-28configure: Enable test and libs for zstdJuan Quintela
Add it to several build systems to make testing good. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2020-02-28multifd: Add zlib compression multifd supportJuan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Acked-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-21 09:06:23 +0000