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2022-06-28semihosting: Move common-semi.h to include/semihosting/Richard Henderson
This header is not private to the top-level semihosting directory, so place it in the public include directory. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Return void from do_common_semihostingRichard Henderson
Perform the cleanup in the FIXME comment in common_semi_gdb_syscall. Do not modify guest registers until the syscall is complete, which in the gdbstub case is asynchronous. In the synchronous non-gdbstub case, use common_semi_set_ret to set the result. Merge set_swi_errno into common_semi_cb. Rely on the latter for combined return value / errno setting. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Clean up common_semi_open_cbRichard Henderson
Use common_semi_cb to return results instead of calling set_swi_errno and common_semi_set_ret directly. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Clean up common_semi_flen_cbRichard Henderson
Do not read from the gdb struct stat buffer if the callback is reporting an error. Use common_semi_cb to finish returning results. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Adjust error checking in common_semi_cbRichard Henderson
The err parameter is non-zero if and only if an error occured. Use this instead of ret == -1 for determining if we need to update the saved errno. This fixes the errno setting of SYS_ISTTY, which returns 0 on error, not -1. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Inline set_swi_errno into common_semi_cbRichard Henderson
Do not store 'err' into errno only to read it back immediately. Use 'ret' for the return value, not 'reg0'. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Split out guestfd.cRichard Henderson
In arm-compat-semi.c, we have more advanced treatment of guest file descriptors than we do in other implementations. Split out GuestFD and related functions to a new file so that they can be shared. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Simplify softmmu_lock_user_stringRichard Henderson
We are not currently bounding the search to the 1024 bytes that we allocated, possibly overrunning the buffer. Use softmmu_strlen_user to find the length and allocate the correct size from the beginning. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Add target_strlen for softmmu-uaccess.hRichard Henderson
Mirror the interface of the user-only function of the same name. Use probe_access_flags for the common case of ram, and cpu_memory_rw_debug for the uncommon case of mmio. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v3: Use probe_access_flags (pmm)
2022-06-28accel/stubs: Add tcg stub for probe_access_flagsRichard Henderson
Reviewed-by: Luc Michel <lmichel@kalray.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Move softmmu-uaccess.h functions out of lineRichard Henderson
Rather that static (and not even inline) functions within a header, move the functions to semihosting/uaccess.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Improve condition for config.c and console.cRichard Henderson
While CONFIG_SEMIHOSTING is currently only set for softmmu, this will not continue to be true. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Return failure from softmmu-uaccess.h functionsRichard Henderson
We were reporting unconditional success for these functions; pass on any failure from cpu_memory_rw_debug. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Move exec/softmmu-semi.h to semihosting/softmmu-uaccess.hRichard Henderson
We have a subdirectory for semihosting; move this file out of exec. Rename to emphasize the contents are a replacement for the functions in linux-user/bsd-user uaccess.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-27Merge tag 'pull-target-arm-20220627' of ↵Richard Henderson
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * sphinx: change default language to 'en' * Diagnose attempts to emulate EL3 in hvf as well as kvm * More SME groundwork patches * virt: Fix calculation of physical address space size for v7VE CPUs (eg cortex-a15) # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmK5hKEZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3lggEACtE2balVHrVCeSQkRW+FnS # avm5i54MIGf3cgNhTKwD9ED3hl03Xm49yQkaq0gB6Qa4wQPEcYQLSyzP+UYIILO5 # 3xoWEw0nbtKWBuCzdiolynL1VFht6GV+Ga8lShoBiQsI/eARC6ZELvBv7gbApf4p # DpDq1ty7fXMmMCNM5vgX9fu/LXahSONDXbYMpHpohnaLXCEF9MwqpO5TJf65Bgze # z2+NO4R5u26mCcad7ltoiz3OKkq4Bq+b+QXrm6LmvSCIkvk6MUZuU1NwHSiqUoV/ # nOwhJriOVl8JG0sX0xzNZADYBt0YlcVuDZzyxP8eOiQ54CVK7rJOJSi+aiGkg2Mn # YC4CkFZY9iM5YTA6y6T5mye7kLb/pJ746rLM1ia6Ng3rUwoE9bdvruqTMfPPJuoo # XxMBQrjRjY6BzESG0NbjLgg80dPtqeOipjglYI7GCvh0i2yQVmKLQon5TK9DsScC # 7Gu6IPVWZAb3axGEuqjJ4E+7PyyEW7zYgWNOpZoQW958WHDK0KSPrOwqxAC+QdEi # vagKJGCQPuZiOARpXm6F/nscEDcy7P33z120O9/R6HuticGaM/oBaWy89CR4hbHB # NWx5+0h5M/je8hJFJJVfHldR3nIpvnUtb4KEVoiNuxkrGZoejgTlBdKNL4Nph0U0 # E+CQyMuBBQ88LEbyCjJS5w== # =GILG # -----END PGP SIGNATURE----- # gpg: Signature made Mon 27 Jun 2022 03:51:21 PM +0530 # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20220627' of https://git.linaro.org/people/pmaydell/qemu-arm: (25 commits) target/arm: Check V7VE as well as LPAE in arm_pamax target/arm: Extend arm_pamax to more than aarch64 target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h target/arm: Add SVL to TB flags target/arm: Introduce sve_vqm1_for_el_sm target/arm: Add cpu properties for SME target/arm: Unexport aarch64_add_*_properties target/arm: Move arm_cpu_*_finalize to internals.h target/arm: Generalize cpu_arm_{get, set}_default_vec_len target/arm: Generalize cpu_arm_{get,set}_vq target/arm: Create ARMVQMap target/arm: Move error for sve%d property to arm_cpu_sve_finalize target/arm: Implement SMSTART, SMSTOP target/arm: Add the SME ZA storage to CPUARMState target/arm: Add PSTATE.{SM,ZA} to TB flags target/arm: Add SMIDR_EL1, SMPRI_EL1, SMPRIMAP_EL2 target/arm: Add SMCR_ELx target/arm: Add SVCR target/arm: Add ARM_CP_SME target/arm: Add syn_smetrap ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-27target/arm: Check V7VE as well as LPAE in arm_pamaxRichard Henderson
In machvirt_init we create a cpu but do not fully initialize it. Thus the propagation of V7VE to LPAE has not been done, and we compute the wrong value for some v7 cpus, e.g. cortex-a15. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1078 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reported-by: He Zhe <zhe.he@windriver.com> Message-id: 20220619001541.131672-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Extend arm_pamax to more than aarch64Richard Henderson
Move the code from hw/arm/virt.c that is supposed to handle v7 into the one function. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reported-by: He Zhe <zhe.he@windriver.com> Message-id: 20220619001541.131672-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.hRichard Henderson
We will need these functions in translate-sme.c. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Add SVL to TB flagsRichard Henderson
We need SVL separate from VL for RDSVL et al, as well as ZA storage loads and stores, which do not require PSTATE.SM. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Introduce sve_vqm1_for_el_smRichard Henderson
When Streaming SVE mode is enabled, the size is taken from SMCR_ELx instead of ZCR_ELx. The format is shared, but the set of vector lengths is not. Further, Streaming SVE does not require any particular length to be supported. Adjust sve_vqm1_for_el to pass the current value of PSTATE.SM to the new function. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Add cpu properties for SMERichard Henderson
Mirror the properties for SVE. The main difference is that any arbitrary set of powers of 2 may be supported, and not the stricter constraints that apply to SVE. Include a property to control FEAT_SME_FA64, as failing to restrict the runtime to the proper subset of insns could be a major point for bugs. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220620175235.60881-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Unexport aarch64_add_*_propertiesRichard Henderson
These functions are not used outside cpu64.c, so make them static. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Move arm_cpu_*_finalize to internals.hRichard Henderson
Drop the aa32-only inline fallbacks, and just use a couple of ifdefs. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Generalize cpu_arm_{get, set}_default_vec_lenRichard Henderson
Rename from cpu_arm_{get,set}_sve_default_vec_len, and take the pointer to default_vq from opaque. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Generalize cpu_arm_{get,set}_vqRichard Henderson
Rename from cpu_arm_{get,set}_sve_vq, and take the ARMVQMap as the opaque parameter. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Create ARMVQMapRichard Henderson
Pull the three sve_vq_* values into a structure. This will be reused for SME. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Move error for sve%d property to arm_cpu_sve_finalizeRichard Henderson
Keep all of the error messages together. This does mean that when setting many sve length properties we'll only generate one error, but we only really need one. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Implement SMSTART, SMSTOPRichard Henderson
These two instructions are aliases of MSR (immediate). Use the two helpers to properly implement svcr_write. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Add the SME ZA storage to CPUARMStateRichard Henderson
Place this late in the resettable section of the structure, to keep the most common element offsets from being > 64k. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-10-richard.henderson@linaro.org [PMM: expanded comment on zarray[] format] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Add PSTATE.{SM,ZA} to TB flagsRichard Henderson
These are required to determine if various insns are allowed to issue. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Add SMIDR_EL1, SMPRI_EL1, SMPRIMAP_EL2Richard Henderson
Implement the streaming mode identification register, and the two streaming priority registers. For QEMU, they are all RES0. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Add SMCR_ELxRichard Henderson
These cpregs control the streaming vector length and whether the full a64 instruction set is allowed while in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Add SVCRRichard Henderson
This cpreg is used to access two new bits of PSTATE that are not visible via any other mechanism. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Add ARM_CP_SMERichard Henderson
This will be used for controlling access to SME cpregs. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Add syn_smetrapRichard Henderson
This will be used for raising various traps for SME. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Add SMEEXC_EL to TB flagsRichard Henderson
This is CheckSMEAccess, which is the basis for a set of related tests for various SME cpregs and instructions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Implement TPIDR2_EL0Richard Henderson
This register is part of SME, but isn't closely related to the rest of the extension. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620175235.60881-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27target/arm: Catch invalid kvm state also for hvfAlexander Graf
Some features such as running in EL3 or running M profile code are incompatible with virtualization as QEMU implements it today. To prevent users from picking invalid configurations on other virt solutions like Hvf, let's run the same checks there too. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1073 Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620192242.70573-2-agraf@csgraf.de [PMM: Allow qtest accelerator too; tweak comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27accel: Introduce current_accel_name()Alexander Graf
We need to fetch the name of the current accelerator in flexible error messages more going forward. Let's create a helper that gives it to us without casting in the target code. Signed-off-by: Alexander Graf <agraf@csgraf.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220620192242.70573-1-agraf@csgraf.de Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27sphinx: change default language to 'en'Martin Liška
Fixes the following Sphinx warning (treated as error) starting with 5.0 release: Warning, treated as error: Invalid configuration value found: 'language = None'. Update your configuration to a valid langauge code. Falling back to 'en' (English). Signed-off-by: Martin Liska <mliska@suse.cz> Message-id: e91e51ee-48ac-437e-6467-98b56ee40042@suse.cz Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-27Merge tag 'qemu-sparc-20220626' of https://github.com/mcayland/qemu into stagingRichard Henderson
qemu-sparc queue # -----BEGIN PGP SIGNATURE----- # # iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmK4moUeHG1hcmsuY2F2 # ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIfaXsH/0+FT9TbHXCplB8h # gvOETq9r5UscYMqUIbRPv7eFIhhZUfq4mCzpthZHYfMA6Tag0jMqaP5ymATm6Jm/ # GgS/7Fx+14uO54Cu4NwIFylRuDt39cESrBHrVjmXmYzOXx7a040+TPxtHHwSRXiQ # Vvx5Oo0P8qQfADQe/Y9iray3JBdFMg4yejO37yrdfP58Nh2dzr9dNKw6apY8dwcv # eTVTqVbYY5AAKOjStpxb0x8dFq/WXttclbeaiSZsK1wnuqhJdUtiMY3UaAfYdMEW # kputMhTZqV/oopUY0mHmBEUK843s8bSQs2aoCSXLamGTWcrm27XNOsX0f4AYwf/y # jWBcSvg= # =0MrK # -----END PGP SIGNATURE----- # gpg: Signature made Sun 26 Jun 2022 11:12:29 PM +0530 # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F * tag 'qemu-sparc-20220626' of https://github.com/mcayland/qemu: (55 commits) artist: set memory region owners for buffers to the artist device ps2: remove update_irq() function and update_arg parameter pckbd: add QEMU interface comment for I8042 device pckbd: switch I8042 device from update_irq() function to PS2 device gpio pckbd: add i8042_reset() function to I8042 device pckbd: add QEMU interface comment for I8042_MMIO device pckbd: switch I8042_MMIO device from update_irq() function to PS2 device gpio lasips2: add QEMU interface comment lasips2: switch over from update_irq() function to PS2 device gpio lasips2: use sysbus IRQ for output IRQ lasips2: implement lasips2_realize() lasips2: add base property lasips2: move initialisation of PS2 ports from lasi_initfn() to lasi_init() lasips2: move mapping of LASIPS2 registers to HPPA machine lasips2: implement lasips2_init() function lasips2: rename lasips2_init() to lasips2_initfn() and update it to return the LASIPS2 device lasips2: move lasips2 QOM types from lasips2.c to lasips2.h lasips2: QOMify LASIPS2State pl050: add QEMU interface comment pl050: switch over from update_irq() function to PS2 device gpio ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-26artist: set memory region owners for buffers to the artist deviceMark Cave-Ayland
This fixes the output of "info qom-tree" so that the buffers appear as children of the artist device, rather than underneath the "unattached" container. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220624160839.886649-1-mark.cave-ayland@ilande.co.uk> Reviewed-by: Helge Deller <deller@gmx.de>
2022-06-26ps2: remove update_irq() function and update_arg parameterMark Cave-Ayland
Now that all the PS2 devices have been converted to use GPIOs the update_irq() callback function and the update_arg parameter can be removed. This allows these arguments to be completely removed from ps2_kbd_init() and ps2_mouse_init(), along with the transitional logic that was added to ps2_raise_irq() and ps2_lower_irq(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-55-mark.cave-ayland@ilande.co.uk>
2022-06-26pckbd: add QEMU interface comment for I8042 deviceMark Cave-Ayland
This describes the I8042 device interface implemented within QEMU. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220624134109.881989-54-mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-26pckbd: switch I8042 device from update_irq() function to PS2 device gpioMark Cave-Ayland
Define a new qdev input gpio for handling incoming PS2 IRQs, and then wire up the PS2 keyboard and mouse devices to use it. At the same time set update_irq() and update_arg to NULL in ps2_kbd_init() and ps2_mouse_init() to ensure that any accidental attempt to use the legacy update_irq() function will cause a NULL pointer dereference. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-53-mark.cave-ayland@ilande.co.uk>
2022-06-26pckbd: add i8042_reset() function to I8042 deviceMark Cave-Ayland
This means that it is no longer necessary to call qemu_register_reset() manually within i8042_realizefn(). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-52-mark.cave-ayland@ilande.co.uk>
2022-06-26pckbd: add QEMU interface comment for I8042_MMIO deviceMark Cave-Ayland
This describes the I8042_MMIO device interface implemented within QEMU. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220624134109.881989-51-mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-26pckbd: switch I8042_MMIO device from update_irq() function to PS2 device gpioMark Cave-Ayland
Define a new qdev input gpio for handling incoming PS2 IRQs, and then wire up the PS2 keyboard and mouse devices to use it. At the same time set update_irq() and update_arg to NULL in ps2_kbd_init() and ps2_mouse_init() to ensure that any accidental attempt to use the legacy update_irq() function will cause a NULL pointer dereference. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220624134109.881989-50-mark.cave-ayland@ilande.co.uk>
2022-06-26lasips2: add QEMU interface commentMark Cave-Ayland
This describes the LASI PS2 device interface implemented within QEMU. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20220624134109.881989-49-mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2022-06-26lasips2: switch over from update_irq() function to PS2 device gpioMark Cave-Ayland
Add a qdev gpio input in lasips2_init() by taking the existing lasips2_port_set_irq() function, updating it accordingly and then renaming to lasips2_set_irq(). Use these new qdev gpio inputs to wire up the PS2 keyboard and mouse devices. At the same time set update_irq() and update_arg to NULL in ps2_kbd_init() and ps2_mouse_init() to ensure that any accidental attempt to use the legacy update_irq() function will cause a NULL pointer dereference. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20220624134109.881989-48-mark.cave-ayland@ilande.co.uk> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-19 08:55:42 +0000