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2020-06-22hw/timer: RX62N 8-Bit timer (TMR)Yoshinori Sato
2020-06-22hw/intc: RX62N interrupt controller (ICUa)Yoshinori Sato
2020-06-22hw/timer/sh_timer: Remove unused 'qemu/timer.h' includePhilippe Mathieu-Daudé
2020-06-22hw/sh4: Extract timer definitions to 'hw/timer/tmu012.h'Philippe Mathieu-Daudé
2020-06-22hw/sh4: Use MemoryRegion typedefPhilippe Mathieu-Daudé
2020-06-22MAINTAINERS: Add an entry for common Renesas peripheralsPhilippe Mathieu-Daudé
2020-06-22MAINTAINERS: Cover sh_intc files in the R2D/Shix machine sectionsPhilippe Mathieu-Daudé
2020-06-22Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...Peter Maydell
2020-06-19Merge remote-tracking branch 'remotes/kraxel/tags/audio-20200619-pull-request...Peter Maydell
2020-06-19qht: Fix threshold rate calculationRichard Henderson
2020-06-19hw/riscv: sifive_u: Add a dummy DDR memory controller deviceBin Meng
2020-06-19hw/riscv: sifive_u: Sort the SoC memmap table entriesBin Meng
2020-06-19hw/riscv: sifive_u: Support different boot source per MSEL pin stateBin Meng
2020-06-19hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004Bin Meng
2020-06-19target/riscv: Rename IBEX CPU init routineBin Meng
2020-06-19hw/riscv: sifive_u: Add a new property msel for MSEL pin stateBin Meng
2020-06-19hw/riscv: sifive_u: Rename serial property get/set functions to a generic nameBin Meng
2020-06-19hw/riscv: sifive_u: Add reset functionalityBin Meng
2020-06-19hw/riscv: sifive_gpio: Do not blindly trigger output IRQsBin Meng
2020-06-19hw/riscv: sifive_u: Hook a GPIO controllerBin Meng
2020-06-19hw/riscv: sifive_gpio: Add a new 'ngpio' propertyBin Meng
2020-06-19hw/riscv: sifive_gpio: Clean up the codesBin Meng
2020-06-19hw/riscv: sifive_u: Generate device tree node for OTPBin Meng
2020-06-19hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bitBin Meng
2020-06-19hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng
2020-06-19hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functionsBin Meng
2020-06-19target/riscv: Use a smaller guess size for no-MMU PMPAlistair Francis
2020-06-19riscv/opentitan: Connect the UART deviceAlistair Francis
2020-06-19riscv/opentitan: Connect the PLIC deviceAlistair Francis
2020-06-19hw/intc: Initial commit of lowRISC Ibex PLICAlistair Francis
2020-06-19hw/char: Initial commit of Ibex UARTAlistair Francis
2020-06-19riscv/opentitan: Fix the ROM sizeAlistair Francis
2020-06-19target/riscv: Implement checks for hfenceAlistair Francis
2020-06-19target/riscv: Move the hfence instructions to the rvh decodeAlistair Francis
2020-06-19target/riscv: Report errors validating 2nd-stage PTEsAlistair Francis
2020-06-19target/riscv: Set access as data_load when validating stage-2 PTEsAlistair Francis
2020-06-19riscv: Keep the CPU init routine names consistentBin Meng
2020-06-19riscv: Generalize CPU init routine for the imacu CPUBin Meng
2020-06-19riscv: Generalize CPU init routine for the gcsu CPUBin Meng
2020-06-19riscv: Generalize CPU init routine for the base CPUBin Meng
2020-06-19sifive_e: Support the revB machineAlistair Francis
2020-06-19riscv: Add helper to make NaN-boxing for FP registerIan Jiang
2020-06-19Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200618' into stagingPeter Maydell
2020-06-19hw/audio/gus: Fix registers 32-bit accessAllan Peramaki
2020-06-18Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into st...Peter Maydell
2020-06-18Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20200617a'...Peter Maydell
2020-06-18net: Drop the NetLegacy structure, always use Netdev insteadThomas Huth
2020-06-18net: Drop the legacy "name" parameter from the -net optionThomas Huth
2020-06-18hw/net/e1000e: Do not abort() on invalid PSRCTL register valuePhilippe Mathieu-Daudé
2020-06-18colo-compare: Fix memory leak in packet_enqueue()Derek Su