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2022-05-24Merge tag 'pull-riscv-to-apply-20220525' of github.com:alistair23/qemu into s...Richard Henderson
2022-05-24hw/core: loader: Set is_linux to true for VxWorks uImageBin Meng
2022-05-24hw/core: Sync uboot_image.h from U-Boot v2022.01Bin Meng
2022-05-24target/riscv: add zicsr/zifencei to isa_stringHongren (Zenithal) Zheng
2022-05-24hw/riscv: virt: Fix interrupt parent for dynamic platform devicesAnup Patel
2022-05-24target/riscv: Set [m|s]tval for both illegal and virtual instruction trapsAnup Patel
2022-05-24target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-modeAnup Patel
2022-05-24target/riscv: Fix csr number based privilege checkingAnup Patel
2022-05-24target/riscv: Fix typo of mimpid cpu optionFrank Chang
2022-05-24target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realizeWeiwei Li
2022-05-24hw/riscv/sifive_u: Resolve redundant property accessorsBernhard Beschow
2022-05-24hw/vfio/pci-quirks: Resolve redundant property gettersBernhard Beschow
2022-05-24target/riscv: Move/refactor ISA extension checksTsukasa OI
2022-05-24target/riscv: FP extension requirementsTsukasa OI
2022-05-24target/riscv: Change "G" expansionTsukasa OI
2022-05-24target/riscv: Disable "G" by defaultTsukasa OI
2022-05-24target/riscv: Fix coding style on "G" expansionTsukasa OI
2022-05-24hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)Tsukasa OI
2022-05-24hw/riscv: Make CPU config error handling generous (virt/spike)Tsukasa OI
2022-05-24target/riscv: Add short-isa-string optionTsukasa OI
2022-05-24target/riscv: Move Zhinx* extensions on ISA stringTsukasa OI
2022-05-24hw/intc: Pass correct hartid while updating mtimecmpAtish Patra
2022-05-24target/riscv: rvv: Fix early exit condition for whole register load/storeeopXD
2022-05-24target/riscv: Fix VS mode hypervisor CSR accessDylan Reid
2022-05-20Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into sta...Richard Henderson
2022-05-19Merge tag 'pull-target-arm-20220519' of https://git.linaro.org/people/pmaydel...Richard Henderson
2022-05-19target/arm: Use FIELD definitions for CPACR, CPTR_ELxRichard Henderson
2022-05-19target/arm: Enable FEAT_HCX for -cpu maxRichard Henderson
2022-05-19target/arm: Fix PAuth keys access checks for disabled SEL2Florian Lugou
2022-05-19ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACYPeter Maydell
2022-05-19hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb nodePeter Maydell
2022-05-19hw/arm/virt: Fix incorrect non-secure flash dtb node namePeter Maydell
2022-05-19target/arm: Make number of counters in PMCR follow the CPUPeter Maydell
2022-05-19target/arm/helper.c: Delete stray obsolete commentPeter Maydell
2022-05-19hw/adc/zynq-xadc: Use qemu_irq typedefPhilippe Mathieu-Daudé
2022-05-19Fix aarch64 debug register names.Chris Howard
2022-05-19hw/intc/arm_gicv3: Provide ich_num_aprs()Peter Maydell
2022-05-19hw/intc/arm_gicv3: Use correct number of priority bits for the CPUPeter Maydell
2022-05-19hw/intc/arm_gicv3: Support configurable number of physical priority bitsPeter Maydell
2022-05-19hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constantPeter Maydell
2022-05-19hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1Peter Maydell
2022-05-19hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parametersPeter Maydell
2022-05-19target/arm: Drop unsupported_encoding() macroPeter Maydell
2022-05-19target/arm: Implement FEAT_IDSTPeter Maydell
2022-05-19target/arm: Enable FEAT_S2FWB for -cpu maxPeter Maydell
2022-05-19target/arm: Implement FEAT_S2FWBPeter Maydell
2022-05-19target/arm: Factor out FWB=0 specific part of combine_cacheattrs()Peter Maydell
2022-05-19target/arm: Postpone interpretation of stage 2 descriptor attribute bitsPeter Maydell
2022-05-18Merge tag 'artist-cursor-fix-final-pull-request' of https://github.com/hdelle...Richard Henderson
2022-05-18capstone: Remove the capstone submoduleThomas Huth
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