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2023-01-20coroutine: Use Coroutine typedef name instead of structure tagMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221221131435.3851212-6-armbru@redhat.com>
2023-01-20coroutine: Split qemu/coroutine-core.h off qemu/coroutine.hMarkus Armbruster
qemu/coroutine.h and qemu/lockable.h include each other. They need each other only in macro expansions, so we could simply drop both inclusions to break the loop, and add suitable includes to files that expand the macros. Instead, move a part of qemu/coroutine.h to new qemu/coroutine-core.h so that qemu/coroutine-core.h doesn't need qemu/lockable.h, and qemu/lockable.h only needs qemu/coroutine-core.h. Result: qemu/coroutine.h includes qemu/lockable.h includes qemu/coroutine-core.h. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221221131435.3851212-5-armbru@redhat.com> [Semantic rebase conflict with 7c10cb38cc "accel/tcg: Add debuginfo support" resolved]
2023-01-19coroutine: Clean up superfluous inclusion of qemu/lockable.hMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20221221131435.3851212-4-armbru@redhat.com>
2023-01-19coroutine: Move coroutine_fn to qemu/osdep.h, trim includesMarkus Armbruster
block/block-hmp-cmds.h and qemu/co-shared-resource.h use coroutine_fn without including qemu/coroutine.h. They compile only if it's already included from elsewhere. I could fix that, but pulling in qemu/coroutine.h and everything it includes just for a macro that expands into nothing feels silly. Instead, move the macro to qemu/osdep.h. Inclusions of qemu/coroutine.h just for coroutine_fn become superfluous. Drop them. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20221221131435.3851212-3-armbru@redhat.com>
2023-01-19coroutine: Clean up superfluous inclusion of qemu/coroutine.hMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20221221131435.3851212-2-armbru@redhat.com>
2023-01-17Merge tag 'pull-tpm-2023-01-17-1' of ↵Peter Maydell
https://github.com/stefanberger/qemu-tpm into staging Merge tpm 2023/01/17 v1 # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEuBi5yt+QicLVzsZrda1lgCoLQhEFAmPGjawACgkQda1lgCoL # QhHOgQf/QxWxhydyj2679bnznCgJXOXKQ1C+MkFvk0ekPJT+bZDwKoohAH3JgbxT # zp3UeMmtqS9JQDcGF6PdIldp4DB7uH+InvVkFFZeD1LN0X6nYHEgZ3Q1obSbf8ut # TGlB6+4TM6ehtk9owDuzlm7/5OFLmEGvGjdVgzZKtwzXGWUKVO7AzzRQBj4QnKq/ # w8cSlZAlF+lJI3IsnCh8EIAdL3SP8dub3yfYJDepbht7IwfkUWPOWBFOSUpo5quX # r1rLKWtjQRsoGDe4iRNrLQu+sgj9npZwj7aYotarJauYBW8qd3jdD4OtiBYj2OMU # LvEIqwNyITivKnapEnDEJV74umzArw== # =lIgU # -----END PGP SIGNATURE----- # gpg: Signature made Tue 17 Jan 2023 11:59:40 GMT # gpg: using RSA key B818B9CADF9089C2D5CEC66B75AD65802A0B4211 # gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B818 B9CA DF90 89C2 D5CE C66B 75AD 6580 2A0B 4211 * tag 'pull-tpm-2023-01-17-1' of https://github.com/stefanberger/qemu-tpm: tests/qtest/tpm-emu: Avoid hangs using abort handlers closing channels tests/qtest: Poll on waitpid() for a while before sending SIGKILL Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-17Merge tag 'pull-tcg-20230116' of https://gitlab.com/rth7680/qemu into stagingPeter Maydell
- Reorg cpu_tb_exec around setjmp. - Use __attribute__((target)) for buffer_is_zero. - Add perfmap and jitdump for perf support. # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmPFtXgdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+62Af/YLdd77+IO8wcPN1n # 2esKNlrrYQ2/x40Hede6L4pp+Qz6M810YgNbhMchBS3u8YGIFzmVLaiz5N4nBGTq # ricOit6Jj2KonlxWaxgma1BW36ydBIwphC20WjrLTVgdNGvxmy4JKbfklTd4oIZ+ # +Kf1VTN1bbt7vfDntd454ck2rhtVZBEvYTynikA3LJ1W7EVN5etDUnrN3VwbaTTK # 0aY8MbDfGUASyrDzmaRcF5F90K+V2STuEUs1whgOuTBusZ6n3+FSDhW8CuDhsy/l # rXtPkQba3rtUWfJ1+o7bx3Gg4nbfn/9lxIfGwhQ79ywD9InjqLqu9etwVyhijx+n # k+tvPw== # =xFfF # -----END PGP SIGNATURE----- # gpg: Signature made Mon 16 Jan 2023 20:37:12 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20230116' of https://gitlab.com/rth7680/qemu: accel/tcg: Split out cpu_exec_{setjmp,loop} util/bufferiszero: Use __attribute__((target)) for avx2/avx512 tcg: add perfmap and jitdump accel/tcg: Add debuginfo support linux-user: Clean up when exiting due to a signal Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-16tests/qtest/tpm-emu: Avoid hangs using abort handlers closing channelsStefan Berger
Install abort handlers that close the TPM control and data channels in case an abort occurs. The purpose of this is to have QEMU terminate under abnormal test case failures to resolve intermittent hangs on s390x hosts running TPM tests for QEMU/x86_64. Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20230111134547.3959604-1-stefanb@linux.ibm.com
2023-01-16tests/qtest: Poll on waitpid() for a while before sending SIGKILLStefan Berger
To prevent getting stuck on waitpid() in case the target process does not terminate on SIGTERM, poll on waitpid() for 30s and if the target process has not changed state until then send a SIGKILL to it. Signed-off-by: Stefan Berger <stefanb@linux.ibm.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-id: 20230112143413.3979057-1-stefanb@linux.ibm.com [PMM: changed TFR to RETRY_ON_EINTR]
2023-01-16accel/tcg: Split out cpu_exec_{setjmp,loop}Richard Henderson
Recently the g_assert(cpu == current_cpu) test has been intermittently failing with gcc. Reorg the code around the setjmp to minimize the lifetime of the cpu variable affected by the setjmp. This appears to fix the existing issue with clang as well. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1147 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-16util/bufferiszero: Use __attribute__((target)) for avx2/avx512Richard Henderson
Use the attribute, which is supported by clang, instead of the #pragma, which is not supported and, for some reason, also not detected by the meson probe, so we fail by -Werror. Include only <immintrin.h> as that is the outermost "official" header for these intrinsics -- emmintrin.h and smmintrin -- are older SSE2 and SSE4 specific headers, while the immintrin.h includes all of the Intel intrinsics. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-16tcg: add perfmap and jitdumpIlya Leoshkevich
Add ability to dump /tmp/perf-<pid>.map and jit-<pid>.dump. The first one allows the perf tool to map samples to each individual translation block. The second one adds the ability to resolve symbol names, line numbers and inspect JITed code. Example of use: perf record qemu-x86_64 -perfmap ./a.out perf report or perf record -k 1 qemu-x86_64 -jitdump ./a.out DEBUGINFOD_URLS= perf inject -j -i perf.data -o perf.data.jitted perf report -i perf.data.jitted Co-developed-by: Vanderson M. do Rosario <vandersonmr2@gmail.com> Co-developed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230112152013.125680-4-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-16accel/tcg: Add debuginfo supportIlya Leoshkevich
Add libdw-based functions for loading and querying debuginfo. Load debuginfo from the system and the linux-user loaders. This is useful for the upcoming perf support, which can then put human-readable guest symbols instead of raw guest PCs into perfmap and jitdump files. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230112152013.125680-3-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-16linux-user: Clean up when exiting due to a signalIlya Leoshkevich
When exiting due to an exit() syscall, qemu-user calls preexit_cleanup(), but this is currently not the case when exiting due to a signal. This leads to various buffers not being flushed (e.g., for gprof, for gcov, and for the upcoming perf support). Add the missing call. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230112152013.125680-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-16Merge tag 'm68k-next-pull-request' of https://github.com/vivier/qemu-m68k ↵Peter Maydell
into staging M68K pull request 20230116 fix FPSR quotient byte # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmPFFmsSHGxhdXJlbnRA # dml2aWVyLmV1AAoJEPMMOL0/L748Dk4P+QH1tlWGWzOiuKZOSUjdJ3NDEw+xpGhH # oS7I7swiz30RCJUJx9R2nL7u5lBN7kcP0duNDp58gwkmReuotrx5HYeN4WwTh/94 # 78CWDKMMT59ag0dA+41WxhXE2sQ6uVgDTtSXTH/1c4rCEm1NuXa+LGBD8oh0IxxW # K0/OHfySQvK3mLRrZtx8h6Ug77Hj5AjYKJZ1tONAe0SkcTe/qXkA4npluVnJl+TQ # /M31uzAD98Td0tSd6YxACkpV++JqEF6Uenbe0iT4A1izRa6GJb56xp+ENeUCavpD # vh5MmJeqTfe/jvdzjWqLv0v88Z+U/TQ8VvvBAUn7aThVo5f/Njclkaxx/i581zpE # pT6jCMxZYKCFdXH+QFqX6B9YBa0fTUxwynWQovIs9bwuWfRYA9IvHLCSWUZHZITi # GQSPbioPcIi4Hc/EJMeRhnZl/9TcGE0tnc+Agib/WI5QaE8Hmj26b7+5v3vxgqQV # vZ3HWOFSZ4sK3MoIsYoKqoRhFX8DtMqXsf70xKBWn5Yx1kol7vz34UYisLaQFJPZ # NBKtVPbyAbMP37h7OMzToiGWw0pitgAERHoj7Qq0juT7U9mjfV/xacdniLMPbSUq # UKzEYgEBNU1728A2TKJUZiXwrdQOx/nZQwJljYMG5RE9ePkhPJ3UvRWMRdxopT+f # 3Lvgvj+qZ8Aq # =VVZK # -----END PGP SIGNATURE----- # gpg: Signature made Mon 16 Jan 2023 09:18:35 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'm68k-next-pull-request' of https://github.com/vivier/qemu-m68k: target/m68k: fix FPSR quotient byte for frem instruction target/m68k: fix FPSR quotient byte for fmod instruction target/m68k: pass sign directly into make_quotient() target/m68k: pass quotient directly into make_quotient() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-16tests/qtest/qom-test: Do not print tested properties by defaultThomas Huth
We're still running into the problem that some logs are cut in the gitlab-CI since they got too big. The biggest part of the log is still the output of the qom-test. Let's stop printing the properties by default to get to a saner size here. The full output can still be enabled by setting V=2 (or higher) in the environment. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221215153036.422362-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-16Merge tag 'mips-20230113' of https://github.com/philmd/qemu into stagingPeter Maydell
MIPS patches queue A bunch of cleanups from various people. - Improved GT64120 on big-endian hosts - GT64120 north bridge and MC146818 RTC devices are now target independent - Bonito64 north bridge converted to 3-phase reset API - PCI refactors around PIIX devices - Support for nanoMIPS in bootloader generator API - New YAMON Malta Avocado test - Removal of 'trap and emulate' KVM support - System-specific QMP commands restricted to system emulation # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmPBekAACgkQ4+MsLN6t # wN4wjxAAtYxyt6WUBpiYfV/LnbQFpAsacues1Vhy9MPYEg5a/iuXWKvWtgRYvGww # qR0GVQH8rH7tgnCZK+ioq9jX+hvfBskP6CnKhxmb5zDGm7vP7jhhu8UFWY/EtBgq # 0zpNeLMXtnRJ6PBqo/nWFCVtcpDRZ6IkSbpGWkVkciRFc5n/2VCnlIj8k2I1oMvL # 11cp2xFQnaPReFXIpMjJHuHv1NObykdlvVg6wQo/A/4qIb8EvJQEPmePjG9Sf0i0 # v2dhnnxG9mze7+uq0dIC16x8Azko3N7dmtNlBU/aGb9OELwx35aux2M4dNDVogwn # DqL/Wsk54TFewECOfS48t/a/TqV8j/ISW1d/JvovBrN2KovmIAbtqHuMUqKVk5l0 # 23ZOIIPIYwmScZwIlkCIGUuIzFig1zhEmQcoEQaFe/B0oLB2eN/x0Bk9Yklo+i2A # WNiyiAj7k5492qEdndOySEEDVt6886F/+CdQ6QYF5Z1L/ELck7XHBH3mGDznWpPn # 6IURyVquPJx7ul62jSGI+Gc+qakNoahIhPo5O7hklOM9GwWNOWXHveyb7xjs7j+O # eWyVcet+o7hoHkCzmfbyTPySI4qCpF9fA42jqPhATwQPwmGXpbr+4BxUq3KtE43y # w9tEigwd4voN3dWLItVh6QE4in70osz3XHp93byvo8bHlS0huVY= # =oXX+ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 13 Jan 2023 15:35:28 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'mips-20230113' of https://github.com/philmd/qemu: (46 commits) scripts/git.orderfile: Display MAINTAINERS changes first target/mips: Restrict 'qapi-commands-machine.h' to system emulation hw/mips/boston: Rename MachineState 'mc' pointer to 'ms' hw/pci-host/bonito: Declare TYPE_BONITO_PCI_HOST_BRIDGE in header hw/pci-host/bonito: Use 'bonito_pci' for PCI function #0 code hw/pci-host/bonito: Use 'bonito_host' for PCI host bridge code hw/pci-host/bonito: Convert to 3-phase reset softmmu/rtc: Emit warning when using driftfix=slew on systems without mc146818 hw/rtc/mc146818rtc: Make the mc146818 RTC device target independent hw/core/qdev-properties-system: Allow the 'slew' policy only on x86 hw/intc: Extract the IRQ counting functions into a separate file hw/intc/i8259: Make using the isa_pic singleton more type-safe hw/usb/hcd-uhci: Introduce TYPE_ defines for device models hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() hw/pci/pci_host: Trace config accesses on unexisting functions mips: Always include nanomips disassembler mips: Remove support for trap and emulate KVM ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-16target/m68k: fix FPSR quotient byte for frem instructionMark Cave-Ayland
The FPSR quotient byte should be set to the value of the quotient and not the result. Manually calculate the quotient in the frem helper in round to nearest even mode (note this is different from the quotient calculated internally for fmod), and use it to set the quotient byte accordingly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Fixes: https://gitlab.com/qemu-project/qemu/-/issues/1314 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230114232959.118224-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-01-16target/m68k: fix FPSR quotient byte for fmod instructionMark Cave-Ayland
The FPSR quotient byte should be set to the value of the quotient and not the result. Switch from using floatx80_mod() to floatx80_modrem() which returns the quotient as a uint64_t which can be used for the quotient byte. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230114232959.118224-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-01-16target/m68k: pass sign directly into make_quotient()Mark Cave-Ayland
This enables the quotient parameter to be changed from int32_t to uint32_t and also allows the extra sign logic in make_quotient() to be removed. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20230114232959.118224-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-01-16target/m68k: pass quotient directly into make_quotient()Mark Cave-Ayland
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230114232959.118224-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2023-01-13scripts/git.orderfile: Display MAINTAINERS changes firstPhilippe Mathieu-Daudé
If we get custom to see MAINTAINERS changes first, we might catch missing MAINTAINERS updates easier. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221216225505.26052-1-philmd@linaro.org>
2023-01-13target/mips: Restrict 'qapi-commands-machine.h' to system emulationPhilippe Mathieu-Daudé
Since commit a0e61807a3 ("qapi: Remove QMP events and commands from user-mode builds") we don't generate the "qapi-commands-machine.h" header in a user-emulation-only build. Extract the QMP functions from cpu.c (which is always compiled) to the new 'sysemu/mips-qmp-cmds.c' unit (which is only compiled when system emulation is selected). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221219211034.70491-4-philmd@linaro.org>
2023-01-13hw/mips/boston: Rename MachineState 'mc' pointer to 'ms'Daniel Henrique Barboza
Follow the QEMU convention of naming MachineState pointers as 'ms' by renaming the instance in create_fdt() where we're calling it 'mc'. Cc: Paul Burton <paulburton@kernel.org> Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20230111172133.334735-1-dbarboza@ventanamicro.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/pci-host/bonito: Declare TYPE_BONITO_PCI_HOST_BRIDGE in headerPhilippe Mathieu-Daudé
Declare the TYPE_BONITO_PCI_HOST_BRIDGE QOM type in a header to be able to access it from board code. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230105130710.49264-8-philmd@linaro.org>
2023-01-13hw/pci-host/bonito: Use 'bonito_pci' for PCI function #0 codePhilippe Mathieu-Daudé
To make it easier to differentiate between the Host Bridge object and its PCI function #0, rename bonito* as bonito_pci*. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230105130710.49264-4-philmd@linaro.org>
2023-01-13hw/pci-host/bonito: Use 'bonito_host' for PCI host bridge codePhilippe Mathieu-Daudé
To make it easier to differentiate between the Host Bridge object and its PCI function #0, rename bonito_pcihost* as bonito_host*. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230105130710.49264-3-philmd@linaro.org>
2023-01-13hw/pci-host/bonito: Convert to 3-phase resetPhilippe Mathieu-Daudé
Convert the TYPE_PCI_BONITO class to use 3-phase reset. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230105130710.49264-2-philmd@linaro.org>
2023-01-13softmmu/rtc: Emit warning when using driftfix=slew on systems without mc146818Thomas Huth
The 'slew' lost tick policy is only available on systems with a mc146818 RTC. On other systems, "-rtc driftfix=slew" is currently silently ignored. Let's emit at least a warning in this case to make the users aware that there is something wrong in their command line settings. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20230110095351.611724-5-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/rtc/mc146818rtc: Make the mc146818 RTC device target independentThomas Huth
The only reason for this code being target dependent was the IRQ-counting related code in rtc_policy_slew_deliver_irq(). Since these functions have been moved into a new, separate file (kvm_irqcount.c) which is now always compiled and linked if necessary, we can get rid of the #ifdef TARGET_I386 switches in mc146818rtc.c and declare it in the softmmu_ss instead of specific_ss, so that the code only gets compiled once for all targets. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20230110095351.611724-4-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/core/qdev-properties-system: Allow the 'slew' policy only on x86Thomas Huth
The 'slew' tick policy is currently enforced to be only available on x86 via some "#ifdef TARGET_I386" statements in mc146818rtc.c. We want to get rid of those #ifdefs, so we need a different way of checking whether the policy is allowed or not. Using the setter function in hw/core/qdev-properties-system.c seems to be a good place, so let's add a check here. Suggested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20230110095351.611724-3-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/intc: Extract the IRQ counting functions into a separate fileThomas Huth
These IRQ counting functions will soon be required in binaries that do not include the APIC code, too, so let's extract them into a separate file that can be linked independently of the APIC code. While we're at it, change the apic_* prefix into kvm_* since the functions are used from the i8259 PIC (i.e. not the APIC), too. Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-Id: <20230110095351.611724-2-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/intc/i8259: Make using the isa_pic singleton more type-safeBernhard Beschow
This even spares some casts in hot code paths along the way. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230109172347.1830-10-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/usb/hcd-uhci: Introduce TYPE_ defines for device modelsBernhard Beschow
Suggested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20221204190553.3274-7-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/mips/Kconfig: Track Malta's PIIX dependencies via KconfigBernhard Beschow
Tracking dependencies via Kconfig seems much cleaner. Note that PIIX4 already depends on ACPI_PIIX4. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20230109172347.1830-8-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specificBernhard Beschow
pci_map_irq_fn's in general seem to be board-specific, and PIIX4's pci_slot_get_pirq() in particular seems very Malta-specific. So move the latter to malta.c to 1/ keep the board logic in one place and 2/ avoid PIIX4 to make assumptions about its board. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230109172347.1830-7-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specificBernhard Beschow
pci_map_irq_fn's in general seem to be board-specific. So move PIIX3's pci_slot_get_pirq() to board code to not have PIIX3 make assuptions about its board. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230109172347.1830-6-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs()Bernhard Beschow
pci_bus_irqs() coupled together the assignment of pci_set_irq_fn and pci_map_irq_fn to a PCI bus. This coupling gets in the way when the pci_map_irq_fn is board-specific while the pci_set_irq_fn is device- specific. For example, both of QEMU's PIIX south bridge models have different pci_map_irq_fn implementations which are board-specific rather than device-specific. These implementations should therefore reside in board code. The pci_set_irq_fn's, however, should stay in the device models because they access memory internal to the model. Factoring out pci_bus_map_irqs() from pci_bus_irqs() allows the assignments to be decoupled, resolving the problem described above. Note also how pci_vpb_realize() which gets touched in this commit assigns different pci_map_irq_fn's depending on the board. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230109172347.1830-5-shentey@gmail.com> [PMD: Factor out in vfu_object_set_bus_irq()] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13hw/pci/pci_host: Trace config accesses on unexisting functionsPhilippe Mathieu-Daudé
Currently we only emit trace events for existing PCI functions. In order to ease debugging PCI enumeration process, also emit for unexisting functions: $ qemu-system-foo -trace pci_cfg_\* ... pci_cfg_read empty 00:0a.4 @0x0 -> 0xffffffff pci_cfg_read empty 00:0a.5 @0x0 -> 0xffffffff pci_cfg_read empty 00:0a.6 @0x0 -> 0xffffffff pci_cfg_read empty 00:0a.7 @0x0 -> 0xffffffff pci_cfg_read pcnet 00:0b.0 @0x0 -> 0x20001022 pci_cfg_read empty 00:0c.0 @0x0 -> 0xffffffff pci_cfg_read empty 00:0d.0 @0x0 -> 0xffffffff pci_cfg_read empty 00:0e.0 @0x0 -> 0xffffffff pci_cfg_read empty 00:0f.0 @0x0 -> 0xffffffff pci_cfg_read empty 00:10.0 @0x0 -> 0xffffffff pci_cfg_read empty 00:11.0 @0x0 -> 0xffffffff pci_cfg_read cirrus-vga 00:12.0 @0x0 -> 0xb81013 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230104133935.4639-2-philmd@linaro.org>
2023-01-13mips: Always include nanomips disassemblerPaolo Bonzini
Since the nanomips disassembler is not C++ code anymore, it need not depend on link_language == cpp. Always include it and remove the CONFIG_NANOMIPS_DIS symbol. Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20230110084942.299460-1-pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-01-13Merge tag 'pull-target-arm-20230113' of ↵Peter Maydell
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: hw/arm/stm32f405: correctly describe the memory layout hw/arm: Add Olimex H405 board cubieboard: Support booting from an SD card image with u-boot on it target/arm: Fix sve_probe_page target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled various code cleanups # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmPBZmYZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3rDdD/9GlrH14yP/2WQZJVJxzXkf # ltO1pvX/AfeNPGy3F8T+kncKspIUeJ8BQNrZKYPWkH1WgAAT3lVH/cUbAlr8UD6W # p2t64ZdQAURuEw3kqtyUVOUeIxzg29cEQyW/9uchA3QPb9xDtiq6KLpAzifDzo6o # 2JE4/NytUJSKxFr5hnyxRTtOYPEMLShBSPvPzU0/BPq7VPyPhT4rqojhpx9uZpVc # h4mfVm9cpF0y3ThBR37M0nhEGJywB/6zOsZ49bm06MFFTwasZ4P0w0fcKhbvrFvX # PHVlNOvyT1oxch5ErN+KULZLByiWy0/Nw85V8P9R+1hU6nncQPM5paB6Y5HUCTKv # wa9gp38V8323fsHg2EEV/PYRdcmRWSBHOq9HPDjIIJlG9nvfXn9O69kDlhnst44b # Fz27XiGJOKY+f20l0J0KzaOnnjw54aeo5tc5WUDbBiZ/btsAHBGQAg7JghmoLkhb # rlvJFgGdG99IuBqJH69dJQ8n/R9bGDRu6X0i1ir3d3C2nY9HYaWUZMyyxOw9dV43 # igQHupOzyYbSyy9+40xz611P0h2k2d90P61Vi41D9ig4Du+I4Vftjqj9mi/Z829k # W1JE5wpKWcDeIXFYLWCZuiOyTCCFBWiWgDJz/zQf7AYma0AWA9gpKrTh2+3EFfqy # VsvMR2T6kmS3FId50bW5OQ== # =D+ib # -----END PGP SIGNATURE----- # gpg: Signature made Fri 13 Jan 2023 14:10:46 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20230113' of https://git.linaro.org/people/pmaydell/qemu-arm: (38 commits) target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled hw/timer/xilinx_timer: Use XpsTimerState instead of 'struct timerblock' hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic' hw/misc/sbsa_ec: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() hw/misc/sbsa_ec: Rename TYPE_SBSA_EC -> TYPE_SBSA_SECURE_EC hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() hw/arm/bcm2836: Remove definitions generated by OBJECT_DECLARE_TYPE() hw/arm/stellaris: Use CamelCase for STELLARIS_ADC type name hw/arm/stellaris: Drop useless casts from void * to pointer hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP2_GPIO type name hw/gpio/omap_gpio: Use CamelCase for TYPE_OMAP1_GPIO type name hw/arm/omap: Drop useless casts from void * to pointer hw/gpio/omap_gpio: Add local variable to avoid embedded cast hw/arm/pxa: Avoid forward-declaring PXA2xxI2CState hw/arm: Remove unreachable code calling pflash_cfi01_register() hw/arm/vexpress: Remove dead code in vexpress_common_init() hw/arm/z2: Use the IEC binary prefix definitions hw/arm/omap_sx1: Use the IEC binary prefix definitions hw/arm/omap_sx1: Remove unused 'total_ram' definitions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-13target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabledEvgeny Iakovlev
ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3 write, and that mask doesn't include SCR_EL3.HXEn bit even if FEAT_HCX is enabled and exposed to the guest. As a result EL3 writes of that bit are ignored. Cc: qemu-stable@nongnu.org Signed-off-by: Evgeny Iakovlev <eiakovlev@linux.microsoft.com> Message-id: 20230105221251.17896-4-eiakovlev@linux.microsoft.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-01-13mips: Remove support for trap and emulate KVMPaolo Bonzini
This support was limited to the Malta board, drop it. I do not have a machine that can run VZ KVM, so I am assuming that it works for -M malta as well. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221221091718.71844-1-philmd@linaro.org>
2023-01-13hw/isa/piix4: Correct IRQRC[A:D] reset valuesPhilippe Mathieu-Daudé
IRQRC[A:D] registers reset value is 0x80. We were forcing the MIPS Malta machine routing to be able to boot a Linux kernel without any bootloader. We now have these registers initialized in the Malta machine write_bootloader(), so we can use the correct reset values. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20221027204720.33611-4-philmd@linaro.org>
2023-01-13hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloaderPhilippe Mathieu-Daudé
Linux kernel expects the northbridge & southbridge chipsets configured by the BIOS firmware. We emulate that by writing a tiny bootloader code in write_bootloader(). Upon introduction in commit 5c2b87e34d ("PIIX4 support"), the PIIX4 configuration space included values specific to the Malta board. Set the Malta-specific IRQ routing values in the embedded bootloader, so the next commit can remove the Malta specific bits from the PIIX4 PCI-ISA bridge and make it generic (matching the real hardware). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20221027204720.33611-3-philmd@linaro.org>
2023-01-13hw/mips/malta: Introduce PIIX4_PCI_DEVFN definitionPhilippe Mathieu-Daudé
The PIIX4 PCI-ISA bridge function is always located at 10:0. Since we want to re-use its address, add the PIIX4_PCI_DEVFN definition. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20221027204720.33611-2-philmd@linaro.org>
2023-01-13hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel()Philippe Mathieu-Daudé
Merge common code shared between write_bootloader() and write_bootloader_nanomips() into bl_setup_gt64120_jump_kernel(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-12-philmd@linaro.org>
2023-01-13hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (5/5)Philippe Mathieu-Daudé
Part 5/5: Convert jumping to kernel Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-11-philmd@linaro.org>
2023-01-13hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5)Philippe Mathieu-Daudé
Part 4/5: Convert GT64120 ISD base address setup Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-10-philmd@linaro.org>
2023-01-13hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5)Philippe Mathieu-Daudé
Part 3/5: Convert PCI0 I/O BAR setup Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-9-philmd@linaro.org>
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