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2021-01-19hw/m68k/next-cube: Add vmstate for NeXTPC devicePeter Maydell
Add the vmstate for the new NeXTPC devic; this is in theory a migration compatibility break, but this machine doesn't have working migration currently anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-11-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Remove unused fields from NeXTStatePeter Maydell
The fields scsi_irq, scsi_dma, scsi_reset and fd_irq in NeXTState are all unused, except in commented out "this should do something like this" code. Remove the unused fields. As and when the functionality that might use them is added, we can put in the correct kind of wiring (which might or might not need to be a qemu_irq, but which in any case will need to be in the NeXTPC device, not in NeXTState). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-10-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move rtc into NeXTPC structPeter Maydell
Move the rtc into the NeXTPC struct. Since this is the last use of the 'backdoor' NextState pointer we can now remove that. Probably the RTC should be its own device at some point: in hardware there is a separate MCS1850 RTC chip connected to the Peripheral Controller via a 1-bit serial interface. That goes beyond the remit of the current refactoring, though. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-9-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Make next_irq GPIO inputs to NEXT_PC devicePeter Maydell
Make the next_irq function be GPIO inputs to the NEXT_PC device, rather than a freestanding set of qemu_irq lines. This fixes a minor Coverity issue where it correctly points out the trivial memory leak of the memory allocated in the call to qemu_allocate_irqs(). Fixes: CID 1421962 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-8-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move int_status and int_mask to NeXTPC structPeter Maydell
All the code which accesses int_status and int_mask is now doing so via the NeXTPC->NeXTState indirection, so we can move these fields into the NeXTPC struct where they belong. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-7-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Make next_irq take NeXTPC* as its opaquePeter Maydell
Make the next_irq function take a NeXTPC* as its opaque rather than the M68kCPU*. This will make it simpler to turn the next_irq function into a gpio input line of the NeXTPC device in the next commit. For this to work we have to pass the CPU to the NeXTPC device via a link property, in the same way we do in q800.c (and for the same reason). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-6-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move scr_ops into NeXTPC devicePeter Maydell
Move the registers handled by the scr_ops struct into the NeXTPC device. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-5-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move mmio_ops into NeXTPC devicePeter Maydell
Move the registers handled by the mmio_ops struct into the NeXTPC device. This allows us to also move the scr1 and scr2 data fields. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-4-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Move register/interrupt functionality into a devicePeter Maydell
Currently the next-cube board code open-codes a lot of handling of interrupts and some miscellaneous registers. Move this into a proper QOM device. In the real hardware this functionality seems to be the responsibility of the Peripheral Controller (PC) chip, so name the device that. There are several different things that will need to be moved into this device: * the mmio_iops register set * the scr_ops register set * the next_irq IRQ handling To ease review, we structure the change as a sequence of commits: in this first commit we create the skeleton of the NeXTPC device with no content, but with a backdoor pointer to the NeXTState machine's state struct so we can move parts of the code and still have refactored and non-refactored code using the same struct data fields. Further commits will move functionality into the new device piece by piece. At the end we will be able to remove the backdoor pointer because all the data fields will be in the NeXTPC struct and not the NeXTState struct. We'll add the VMState for the new device at the end of all that; this is in theory a migration compatibility break but this machine does not currently support migration at all anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-3-peter.maydell@linaro.org> [huth: Add a comment in front of struct NeXTPC] Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-19hw/m68k/next-cube: Make next_irq() function staticPeter Maydell
The next_irq() function is global, but isn't actually used anywhere outside next-cube.c. Make it static. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210115201206.17347-2-peter.maydell@linaro.org> Signed-off-by: Thomas Huth <huth@tuxfamily.org>
2021-01-18Merge remote-tracking branch ↵Peter Maydell
'remotes/vivier2/tags/trivial-branch-for-6.0-pull-request' into staging Trivial patches 20210118 Fix memory leaks Use qemu_log_mask(GUEST_ERROR) rather than error_report(). # gpg: Signature made Mon 18 Jan 2021 11:31:10 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/trivial-branch-for-6.0-pull-request: hw/ide/ahci: Replace fprintf() by qemu_log_mask(GUEST_ERROR) misc/mos6522: Use timer_free() in the finalize function to avoid memleak pl031: Use timer_free() in the finalize function to avoid memleaks hw/virtio-pci: Replace error_report() by qemu_log_mask(GUEST_ERROR) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-18Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-testing-and-misc-180121-2' into staging Testing, gdbstub and semihosting patches: - clean-ups to docker images - drop duplicate jobs from shippable - prettier tag generation (+gtags) - generate browsable source tree - more Travis->GitLab migrations - fix checkpatch to deal with commits - gate gdbstub tests on 8.3.1, expand tests - support Xfer:auxv:read gdb packet - better gdbstub cleanup - use GDB's SVE register layout - make arm-compat-semihosting common - add riscv semihosting support - add HEAPINFO, ELAPSED, TICKFREQ, TMPNAM and ISERROR to semihosting # gpg: Signature made Mon 18 Jan 2021 10:09:11 GMT # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-and-misc-180121-2: (30 commits) semihosting: Implement SYS_ISERROR semihosting: Implement SYS_TMPNAM semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ riscv: Add semihosting support for user mode riscv: Add semihosting support semihosting: Support SYS_HEAPINFO when env->boot_info is not set semihosting: Change internal common-semi interfaces to use CPUState * semihosting: Change common-semi API to be architecture-independent semihosting: Move ARM semihosting code to shared directories target/arm: use official org.gnu.gdb.aarch64.sve layout for registers gdbstub: ensure we clean-up when terminated gdbstub: drop gdbserver_cleanup in favour of gdb_exit gdbstub: drop CPUEnv from gdb_exit() gdbstub: add support to Xfer:auxv:read: packet gdbstub: implement a softmmu based test Revert "tests/tcg/multiarch/Makefile.target: Disable run-gdbstub-sha1 test" configure: gate our use of GDB to 8.3.1 or above test/guest-debug: echo QEMU command as well scripts/checkpatch.pl: fix git-show invocation to include diffstat gitlab: migrate the minimal tools and unit tests from Travis ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # default-configs/targets/riscv32-linux-user.mak # default-configs/targets/riscv64-linux-user.mak
2021-01-18hw/ide/ahci: Replace fprintf() by qemu_log_mask(GUEST_ERROR)Philippe Mathieu-Daudé
Replace fprintf() calls by qemu_log_mask(LOG_GUEST_ERROR). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210112112955.1849212-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-18misc/mos6522: Use timer_free() in the finalize function to avoid memleakGan Qixin
When running device-introspect-test, a memory leak occurred in the mos6522_init function, this patch use timer_free() in the finalize function to fix it. ASAN shows memory leak stack: Direct leak of 96 byte(s) in 2 object(s) allocated from: #0 0xfffd5fe9e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) #1 0xfffd5f7b6800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) #2 0xaaae50303d0c in timer_new_full qemu/include/qemu/timer.h:523 #3 0xaaae50303d0c in timer_new qemu/include/qemu/timer.h:544 #4 0xaaae50303d0c in timer_new_ns qemu/include/qemu/timer.h:562 #5 0xaaae50303d0c in mos6522_init qemu/hw/misc/mos6522.c:490 #6 0xaaae50b77d70 in object_init_with_type qemu/qom/object.c:371 #7 0xaaae50b7ae84 in object_initialize_with_type qemu/qom/object.c:515 #8 0xaaae50b7b0f8 in object_new_with_type qemu/qom/object.c:729 #9 0xaaae50bb6d58 in qmp_device_list_properties qemu/qom/qom-qmp-cmds.c:153 #10 0xaaae50d7e1dc in qmp_marshal_device_list_properties qemu/qapi/qapi-commands-qdev.c:59 #11 0xaaae50dc87a0 in do_qmp_dispatch_bh qemu/qapi/qmp-dispatch.c:110 #12 0xaaae50d931a0 in aio_bh_call qemu/util/async.c:136 Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Gan Qixin <ganqixin@huawei.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210112112705.380534-3-ganqixin@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-18pl031: Use timer_free() in the finalize function to avoid memleaksGan Qixin
When running device-introspect-test, a memory leak occurred in the pl031_init function, this patch use timer_free() in the finalize function to fix it. ASAN shows memory leak stack: Direct leak of 48 byte(s) in 1 object(s) allocated from: #0 0xffffab97e1f0 in __interceptor_calloc (/lib64/libasan.so.5+0xee1f0) #1 0xffffab256800 in g_malloc0 (/lib64/libglib-2.0.so.0+0x56800) #2 0xaaabf5621cfc in timer_new_full qemu/include/qemu/timer.h:523 #3 0xaaabf5621cfc in timer_new qemu/include/qemu/timer.h:544 #4 0xaaabf5621cfc in timer_new_ns qemu/include/qemu/timer.h:562 #5 0xaaabf5621cfc in pl031_init qemu/hw/rtc/pl031.c:194 #6 0xaaabf6339f6c in object_initialize_with_type qemu/qom/object.c:515 #7 0xaaabf633a1e0 in object_new_with_type qemu/qom/object.c:729 #8 0xaaabf6375e40 in qmp_device_list_properties qemu/qom/qom-qmp-cmds.c:153 #9 0xaaabf5a95540 in qdev_device_help qemu/softmmu/qdev-monitor.c:283 #10 0xaaabf5a96940 in qmp_device_add qemu/softmmu/qdev-monitor.c:801 #11 0xaaabf5a96e70 in hmp_device_add qemu/softmmu/qdev-monitor.c:916 #12 0xaaabf5ac0a2c in handle_hmp_command qemu/monitor/hmp.c:1100 Reported-by: Euler Robot <euler.robot@huawei.com> Signed-off-by: Gan Qixin <ganqixin@huawei.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210112112705.380534-2-ganqixin@huawei.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-18hw/virtio-pci: Replace error_report() by qemu_log_mask(GUEST_ERROR)Philippe Mathieu-Daudé
Replace I/O write error reported with error_report() by qemu_log_mask(GUEST_ERROR) which allow filtering. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-Id: <20201210172834.178052-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-01-18Merge remote-tracking branch ↵Peter Maydell
'remotes/alistair/tags/pull-riscv-to-apply-20210117-3' into staging First RISC-V PR for 6.0 This PR: - Fixes some issues with the m25p80 - Improves GDB support for RISC-V - Fixes some Linux boot issues, specifiaclly 32-bit boot failures - Enforces PMP exceptions correctly - Fixes some Coverity issues # gpg: Signature made Sun 17 Jan 2021 21:53:19 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210117-3: riscv: Pass RISCVHartArrayState by pointer target/riscv: Remove built-in GDB XML files for CSRs target/riscv: Generate the GDB XML file for CSR registers dynamically target/riscv: Add CSR name in the CSR function table target/riscv: Make csr_ops[CSR_TABLE_SIZE] external hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type target/riscv/pmp: Raise exception if no PMP entry is configured RISC-V: Place DTB at 3GB boundary instead of 4GB gdb: riscv: Add target description hw/block: m25p80: Implement AAI-WP command support for SST flashes hw/block: m25p80: Don't write to flash if write is disabled Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-18semihosting: Implement SYS_ISERRORKeith Packard
Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210107170717.2098982-10-keithp@keithp.com> Message-Id: <20210108224256.2321-21-alex.bennee@linaro.org>
2021-01-18semihosting: Implement SYS_TMPNAMKeith Packard
Part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210107170717.2098982-9-keithp@keithp.com> Message-Id: <20210108224256.2321-20-alex.bennee@linaro.org>
2021-01-18semihosting: Implement SYS_ELAPSED and SYS_TICKFREQKeith Packard
These are part of Semihosting for AArch32 and AArch64 Release 2.0 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210107170717.2098982-8-keithp@keithp.com> Message-Id: <20210108224256.2321-19-alex.bennee@linaro.org>
2021-01-18riscv: Add semihosting support for user modeKito Cheng
This could made testing more easier and ARM/AArch64 has supported on their linux user mode too, so I think it should be reasonable. Verified GCC testsuite with newlib/semihosting. Signed-off-by: Kito Cheng <kito.cheng@sifive.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Keith Packard <keithp@keithp.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210107170717.2098982-7-keithp@keithp.com> Message-Id: <20210108224256.2321-18-alex.bennee@linaro.org>
2021-01-18riscv: Add semihosting supportKeith Packard
Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-6-keithp@keithp.com> Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org>
2021-01-18semihosting: Support SYS_HEAPINFO when env->boot_info is not setKeith Packard
env->boot_info is only set in some ARM startup paths, so we cannot rely on it to support the SYS_HEAPINFO semihosting function. When not available, fallback to finding a RAM memory region containing the current stack and use the base of that. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210107170717.2098982-5-keithp@keithp.com> Message-Id: <20210108224256.2321-16-alex.bennee@linaro.org>
2021-01-18semihosting: Change internal common-semi interfaces to use CPUState *Keith Packard
This makes all of the internal interfaces architecture-independent and renames the internal functions to use the 'common_semi' prefix instead of 'arm' or 'arm_semi'. To do this, some new architecture-specific internal helper functions were created: static inline target_ulong common_semi_arg(CPUState *cs, int argno) Returns the argno'th semihosting argument, where argno can be either 0 or 1. static inline void common_semi_set_ret(CPUState *cs, target_ulong ret) Sets the semihosting return value. static inline bool common_semi_sys_exit_extended(CPUState *cs, int nr) This detects whether the specified semihosting call, which is either TARGET_SYS_EXIT or TARGET_SYS_EXIT_EXTENDED should be executed using the TARGET_SYS_EXIT_EXTENDED semantics. static inline target_ulong common_semi_rambase(CPUState *cs) Returns the base of RAM region used for heap and stack. This is used to construct plausible values for the SYS_HEAPINFO call. In addition, several existing functions have been changed to flag areas of code which are architecture specific: static target_ulong common_semi_flen_buf(CPUState *cs) Returns the current stack pointer minus 64, which is where a stat structure will be placed on the stack #define GET_ARG(n) This fetches arguments from the semihosting command's argument block. The address of this is available implicitly through the local 'args' variable. This is *mostly* architecture independent, but does depend on the current ABI's notion of the size of a 'long' parameter, which may need run-time checks (as it does on AARCH64) #define SET_ARG(n, val) This mirrors GET_ARG and stores data back into the argument block. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-4-keithp@keithp.com> Message-Id: <20210108224256.2321-15-alex.bennee@linaro.org>
2021-01-18semihosting: Change common-semi API to be architecture-independentKeith Packard
The public API is now defined in hw/semihosting/common-semi.h. do_common_semihosting takes CPUState * instead of CPUARMState *. All internal functions have been renamed common_semi_ instead of arm_semi_ or arm_. Aside from the API change, there are no functional changes in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210107170717.2098982-3-keithp@keithp.com> Message-Id: <20210108224256.2321-14-alex.bennee@linaro.org>
2021-01-18semihosting: Move ARM semihosting code to shared directoriesKeith Packard
This commit renames two files which provide ARM semihosting support so that they can be shared by other architectures: 1. target/arm/arm-semi.c -> hw/semihosting/common-semi.c 2. linux-user/arm/semihost.c -> linux-user/semihost.c The build system was modified use a new config variable, CONFIG_ARM_COMPATIBLE_SEMIHOSTING, which has been added to the ARM softmmu and linux-user default configs. The contents of the source files has not been changed in this patch. Signed-off-by: Keith Packard <keithp@keithp.com> [AJB: rename arm-compat-semi, select SEMIHOSTING] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210107170717.2098982-2-keithp@keithp.com> Message-Id: <20210108224256.2321-13-alex.bennee@linaro.org>
2021-01-18target/arm: use official org.gnu.gdb.aarch64.sve layout for registersAlex Bennée
While GDB can work with any XML description given to it there is special handling for SVE registers on the GDB side which makes the users life a little better. The changes aren't that major and all the registers save the $vg reported the same. All that changes is: - report org.gnu.gdb.aarch64.sve - use gdb nomenclature for names and types - minor re-ordering of the types to match reference - re-enable ieee_half (as we know gdb supports it now) - $vg is now a 64 bit int - check $vN and $zN aliasing in test Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luis Machado <luis.machado@linaro.org> Message-Id: <20210108224256.2321-11-alex.bennee@linaro.org>
2021-01-18gdbstub: ensure we clean-up when terminatedAlex Bennée
If you kill the inferior from GDB we end up leaving our socket lying around. Fix this by calling gdb_exit() first. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210108224256.2321-10-alex.bennee@linaro.org>
2021-01-18gdbstub: drop gdbserver_cleanup in favour of gdb_exitAlex Bennée
Despite it's name it didn't actually clean-up so let us document gdb_exit() better and use that. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210108224256.2321-9-alex.bennee@linaro.org>
2021-01-18gdbstub: drop CPUEnv from gdb_exit()Alex Bennée
gdb_exit() has never needed anything from env and I doubt we are going to start now. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210108224256.2321-8-alex.bennee@linaro.org>
2021-01-18gdbstub: add support to Xfer:auxv:read: packetLirong Yuan
This allows gdb to access the target’s auxiliary vector, which can be helpful for telling system libraries important details about the hardware, operating system, and process. Signed-off-by: Lirong Yuan <yuanzi@google.com> [AJB: minor tweaks to test case, update MAINTAINERS, restrict to Linux] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200730193932.3654677-1-yuanzi@google.com> Message-Id: <20210108224256.2321-7-alex.bennee@linaro.org>
2021-01-18gdbstub: implement a softmmu based testAlex Bennée
This adds a new tests that allows us to test softmmu only features including watchpoints. To do achieve this we need to: - add _exit: labels to the boot codes - write a memory.py test case - plumb the test case into the build system - tweak the run_test script to: - re-direct output when asked - use socket based connection for all tests - add a small pause before connection Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210108224256.2321-6-alex.bennee@linaro.org>
2021-01-18Revert "tests/tcg/multiarch/Makefile.target: Disable run-gdbstub-sha1 test"Alex Bennée
We won't attempt to run the test now it's gated on a newer version of gdb. This reverts commit a930cadd83b4681a98ce72abf530a791ee2e42a6. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210108224256.2321-5-alex.bennee@linaro.org>
2021-01-18configure: gate our use of GDB to 8.3.1 or aboveAlex Bennée
The support of socket based debugging which we need for linux-user testing is only really stable as of 8.3.1 so lets gate our use of GDB on having a relatively modern version. For direct testing you can just point to a locally compiled version of gdb via configure, e.g.: ../../configure --gdb=$HOME/src/binutils-gdb.git/builds/all/install/bin/gdb Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210108224256.2321-4-alex.bennee@linaro.org>
2021-01-18test/guest-debug: echo QEMU command as wellAlex Bennée
This helps with debugging. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210108224256.2321-3-alex.bennee@linaro.org>
2021-01-18scripts/checkpatch.pl: fix git-show invocation to include diffstatAlex Bennée
Without this checkpatch keeps complaining about new/changed files even when MAINTAINERS has been updated. Normal invocations of checkpatch on patch files rather than commit IDs are unaffected. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210114165730.31607-13-alex.bennee@linaro.org>
2021-01-18gitlab: migrate the minimal tools and unit tests from TravisAlex Bennée
These tests are good at shaking out missing stubs which otherwise work if we have built targets. Rather than create a new job just add the checks to the existing tools-and-docs build. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210114165730.31607-12-alex.bennee@linaro.org>
2021-01-18Fix build with new yank feature by adding stubsLukas Straub
Fixes: 50186051f42 ("Introduce yank feature") Signed-off-by: Lukas Straub <lukasstraub2@web.de> [AJB: tweak MAINTAINERS] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210114141918.5201cc9c@gecko.fritz.box> Message-Id: <20210114165730.31607-11-alex.bennee@linaro.org>
2021-01-18gitlab: move docs and tools build across from TravisAlex Bennée
While we are at it we might as well check the tag generation. For bonus points we run GNU globals htags into the public pages directory for publishing with the auto generated pages. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210114165730.31607-10-alex.bennee@linaro.org>
2021-01-18docker: expand debian-amd64 image to include tag toolsAlex Bennée
This is going to be helpful when we want to both test the tool integration and in the case of global generate a xref doc build. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210114165730.31607-9-alex.bennee@linaro.org>
2021-01-18Makefile: wrap cscope in quiet-command callsAlex Bennée
For prettier output. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210114165730.31607-8-alex.bennee@linaro.org>
2021-01-18Makefile: wrap etags in quiet-command callsAlex Bennée
For prettier output. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210114165730.31607-7-alex.bennee@linaro.org>
2021-01-18Makefile: wrap ctags in quiet-command callsAlex Bennée
For prettier output. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210114165730.31607-6-alex.bennee@linaro.org>
2021-01-18Add newline when generating DockerfileAlessandro Di Federico
Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1610080146-14968-36-git-send-email-tsimpson@quicinc.com> Message-Id: <20210114165730.31607-5-alex.bennee@linaro.org>
2021-01-18shippable.yml: Remove jobs duplicated on Gitlab-CIPhilippe Mathieu-Daudé
The following jobs are duplicated on Gitlab-CI since commit 6bcb5fc0f7a ("gitlab-ci: Add cross-compiling build tests"): - IMAGE=debian-armel-cross TARGET_LIST=arm-softmmu -> cross-armel-system TARGET_LIST=arm-linux-user -> cross-armel-user TARGET_LIST=armeb-linux-user -> cross-armel-user - IMAGE=debian-armhf-cross TARGET_LIST=arm-softmmu -> cross-armhf-system TARGET_LIST=arm-linux-user -> cross-armhf-user TARGET_LIST=armeb-linux-user -> cross-armhf-user - IMAGE=debian-arm64-cross TARGET_LIST=aarch64-softmmu -> cross-arm64-system TARGET_LIST=aarch64-linux-user -> cross-arm64-user - IMAGE=debian-s390x-cross TARGET_LIST=s390x-softmmu -> cross-s390x-system TARGET_LIST=s390x-linux-user -> cross-s390x-user - IMAGE=debian-mips-cross TARGET_LIST=mipsel-linux-user -> cross-mips-user - IMAGE=debian-mips64el-cross TARGET_LIST=mips64el-softmmu -> cross-mips64el-system TARGET_LIST=mips64el-linux-user -> cross-mips64el-user - IMAGE=debian-ppc64el-cross TARGET_LIST=ppc64-softmmu -> cross-ppc64el-system TARGET_LIST=ppc64-linux-user -> cross-ppc64el-user TARGET_LIST=ppc64abi32-linux-user -> cross-ppc64el-user Remove them from Shippable CI. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210108145103.269353-1-f4bug@amsat.org> Message-Id: <20210114165730.31607-4-alex.bennee@linaro.org>
2021-01-18Makefile: add GNU global tags supportAlex Bennée
GNU Global is another tags engine which is more like cscope in being able to support finding both references and definitions. You will be un-surprised to know it also integrates well with Emacs. The main benefit of integrating it into find-src-path is it takes less time to rebuild the database from scratch when you have a lot of build directories under your source tree. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210114165730.31607-3-alex.bennee@linaro.org>
2021-01-18tests/docker: Remove Debian 9 remnant linesPhilippe Mathieu-Daudé
Debian 9 base container has been removed in commits e3755276d1f and c9d78b06c06. Remove the last remnants. Fixes: e3755276d1f ("tests/docker: Remove old Debian 9 containers") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Message-Id: <20210107072933.3828450-1-f4bug@amsat.org> Message-Id: <20210114165730.31607-2-alex.bennee@linaro.org>
2021-01-17Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell
pc,pci,virtio: fixes, features Fixes all over the place. PXB support for ARM. boot index for vhost-user-fs. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 17 Jan 2021 11:44:55 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: acpi: Update _DSM method in expected files acpi: Enable pxb unit-test for ARM virt machine Kconfig: Compile PXB for ARM_VIRT acpi/gpex: Exclude pxb's resources from PCI0 acpi/gpex: Inform os to keep firmware resource map acpi: Add addr offset in build_crs acpi: Fix unmatched expected DSDT.pxb file acpi: Allow DSDT acpi table changes vhost-user-fs: add the "bootindex" property pci/shpc: don't push attention button when ejecting powered-off device Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-01-17acpi: Update _DSM method in expected filesJiahui Cen
A new _DSM #5 method is added. Update expected DSDT files accordingly, and re-enable their testing. Full diff of changed files disassembly: tests/data/acpi/microvm/DSDT.pcie.dsl: @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/microvm/DSDT.pcie, Thu Jan 14 13:39:35 2021 + * Disassembly of tests/data/acpi/microvm/DSDT.pcie, Thu Jan 14 13:51:13 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x00000BCF (3023) + * Length 0x00000BD7 (3031) * Revision 0x02 - * Checksum 0x29 + * Checksum 0x99 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) @@ -1302,9 +1302,14 @@ { Return (Buffer (One) { - 0x01 // . + 0x21 // ! }) } + + If ((Arg2 == 0x05)) + { + Return (Zero) + } } Return (Buffer (One) tests/data/acpi/virt/DSDT.dsl: @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/virt/DSDT, Thu Jan 14 13:39:35 2021 + * Disassembly of tests/data/acpi/virt/DSDT, Thu Jan 14 13:51:13 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x0000144C (5196) + * Length 0x00001454 (5204) * Revision 0x02 - * Checksum 0xF0 + * Checksum 0x60 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) @@ -1838,9 +1838,14 @@ { Return (Buffer (One) { - 0x01 // . + 0x21 // ! }) } + + If ((Arg2 == 0x05)) + { + Return (Zero) + } } Return (Buffer (One) tests/data/acpi/virt/DSDT.memhp.dsl: @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/virt/DSDT.memhp, Thu Jan 14 13:39:35 2021 + * Disassembly of tests/data/acpi/virt/DSDT.memhp, Thu Jan 14 13:51:13 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x0000199D (6557) + * Length 0x000019A5 (6565) * Revision 0x02 - * Checksum 0x11 + * Checksum 0x90 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) @@ -1840,9 +1840,14 @@ { Return (Buffer (One) { - 0x01 // . + 0x21 // ! }) } + + If ((Arg2 == 0x05)) + { + Return (Zero) + } } Return (Buffer (One) tests/data/acpi/virt/DSDT.numamem.dsl: @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/virt/DSDT.numamem, Thu Jan 14 13:39:35 2021 + * Disassembly of tests/data/acpi/virt/DSDT.numamem, Thu Jan 14 13:51:13 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x0000144C (5196) + * Length 0x00001454 (5204) * Revision 0x02 - * Checksum 0xF0 + * Checksum 0x60 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) @@ -1838,9 +1838,14 @@ { Return (Buffer (One) { - 0x01 // . + 0x21 // ! }) } + + If ((Arg2 == 0x05)) + { + Return (Zero) + } } Return (Buffer (One) tests/data/acpi/virt/DSDT.pxb.dsl: @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/virt/DSDT.pxb, Thu Jan 14 13:39:35 2021 + * Disassembly of tests/data/acpi/virt/DSDT.pxb, Thu Jan 14 13:51:13 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x00001DF9 (7673) + * Length 0x00001E09 (7689) * Revision 0x02 - * Checksum 0x42 + * Checksum 0x30 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) @@ -1810,9 +1810,14 @@ { Return (Buffer (One) { - 0x01 // . + 0x21 // ! }) } + + If ((Arg2 == 0x05)) + { + Return (Zero) + } } Return (Buffer (One) @@ -3025,9 +3030,14 @@ { Return (Buffer (One) { - 0x01 // . + 0x21 // ! }) } + + If ((Arg2 == 0x05)) + { + Return (Zero) + } } Return (Buffer (One) Acked-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com> Message-Id: <20210114100643.10617-9-cenjiahui@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2021-01-17acpi: Enable pxb unit-test for ARM virt machineJiahui Cen
No matter whether the pxb is enabled or not, the CONFIG_PXB macro in test would keep undefined. And since pxb is now enabled for ARM Virt machine by default, let's enable pxb unit-test by removing the CONFIG_PXB. Acked-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Jiahui Cen <cenjiahui@huawei.com> Message-Id: <20210114100643.10617-8-cenjiahui@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-13 10:07:38 +0000