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2023-11-06target/hppa: Implement DEPD, DEPDIRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement LDD, LDCD, LDDA, STD, STDARichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode ADDB double-wordRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode CMPIB double-wordRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for cmpb instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for bb instructionsRichard Henderson
Manipulate the shift count so that the bit to be tested is always placed at the MSB. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for sub instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for add instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for cmpclr instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for unit instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for logical instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove TARGET_HPPA64Richard Henderson
Allow both user-only and system mode to run pa2.0 cpus. Avoid creating a separate qemu-system-hppa64 binary; force the qemu-hppa binary to use TARGET_ABI32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Drop attempted gdbstub support for hppa64Richard Henderson
There is no support for hppa64 in gdb. Any attempt to provide the data for the larger hppa64 registers results in an error from gdb. Mask CR_SAR writes to the width of the register: 5 or 6 bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06linux-user/hppa: Fixes for TARGET_ABI32Richard Henderson
Avoid target_ulong and use abi_* types. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_unit_condRichard Henderson
Hoist the resolution of d up one level above do_unit_cond. All computations are logical, and are simplified by using a mask of the correct width, after which the result may be compared with zero. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_sed_condRichard Henderson
Hoist the resolution of d up one level above do_sed_cond. The MOVB comparison and the existing shift/extract/deposit are all 32-bit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_log_condRichard Henderson
Hoist the resolution of d up one level above do_log_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_sub_condRichard Henderson
Hoist the resolution of d up one level above do_sub_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass d to do_condRichard Henderson
Hoist the resolution of d up one level above do_cond. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: sar register allows only 5 bits on 32-bit CPUHelge Deller
The sar shift amount register is limited to 5 bits when running a 32-bit CPU. Strip off the remaining bits. The interesting part is, that this register allows to detect at runtime if a physical CPU is capable to execute PA2.0 (64-bit) instructions. Signed-off-by: Helge Deller <deller@gmx.de>
2023-11-06target/hppa: Mask inputs in copy_iaoq_entryRichard Henderson
Ensure that the destination is always a valid GVA offset. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Use copy_iaoq_entry for link in do_ibranchRichard Henderson
We need to make sure the link is masked properly along the use_nullify_skip path. The other three settings of a link register already use this. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb]Richard Henderson
This will be how we ensure that the IAOQ is always valid per PSW.W, therefore all stores to these two variables must be done with this function. Use third argument -1 if the destination is always dynamic, and fourth argument NULL if the destination is always static. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Pass DisasContext to copy_iaoq_entryRichard Henderson
Interface change only, no functional effect. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix hppa64 addressingRichard Henderson
In form_gva and cpu_get_tb_cpu_state, we must truncate when PSW_W == 0. In space_select, the bits that choose the space depend on PSW_W. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Adjust hppa_cpu_dump_state for hppa64Richard Henderson
Dump all 64 bits for pa2.0 and low 32 bits for pa1.x. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Handle absolute addresses for pa2.0Richard Henderson
With pa2.0, absolute addresses are not the same as physical addresses, and undergo a transformation based on PSW_W. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Update cpu_hppa_get/put_psw for hppa64Richard Henderson
With 64-bit registers, there are 16 carry bits in the PSW. Clear reserved bits based on cpu revision. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement hppa_cpu_class_by_nameRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement cpu_listRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Make HPPA_BTLB_ENTRIES variableRichard Henderson
Depend on hppa_is_pa20. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Introduce TYPE_HPPA64_CPURichard Henderson
Prepare for the qemu binary supporting both pa10 and pa20 at the same time. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix extrw and depw with sar for hppa64Richard Henderson
These are 32-bit operations regardless of processor. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix bb_sar for hppa64Richard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix do_add, do_sub for hppa64Richard Henderson
Select the proper carry bit for input to the arithmetic and for output for the condition. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix trans_ds for hppa64Richard Henderson
This instruction always uses the input carry from bit 32, but produces all 16 output carry bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Truncate rotate count in trans_shrpw_sarRichard Henderson
When forcing rotate by i32, the shift count must be as well. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix load in do_load_32Richard Henderson
The destination is TCGv_i32, so use tcg_gen_qemu_ld_i32 not tcg_gen_qemu_ld_reg. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix hppa64 case in machine.cRichard Henderson
Typo of VMSTATE_UINTTR_V and VMSTATE_UINTTR_ARRAY_V macros. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove load_constRichard Henderson
Replace with tcg_constant_reg. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove get_temp_tlRichard Henderson
Replace with tcg_temp_new_tl without recording into ctx. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove get_tempRichard Henderson
Replace with tcg_temp_new without recording into ctx. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Populate an interval tree with valid tlb entriesRichard Henderson
Complete the data structure conversion started earlier. This reduces the perf overhead of hppa_get_physical_address from ~5% to ~0.25%. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Split out hppa_flush_tlb_rangeRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Always report one page to tlb_set_pageRichard Henderson
No need to trigger the large_page_mask code unnecessarily. Drop the now unused HPPATLBEntry.page_size field. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Use IntervalTreeNode in HPPATLBEntryRichard Henderson
Replace the va_b and va_b fields with the interval tree node. The actual interval tree is not yet used. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Rename hppa_tlb_entry to HPPATLBEntryRichard Henderson
Rename to CamelCase per coding style. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Include PSW_P in tb flags and mmu indexRichard Henderson
Use a separate mmu index for PSW_P enabled vs disabled. This means we can elide the tlb flush in cpu_hppa_put_psw when PSW_P changes. This turns out to be the majority of all tlb flushes. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi
target/sparc: Explicitly compute condition codes # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmVH9oodHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV/M8QgAgPTp/wFLVnSRFLaN # fBoelVhM4WTWMQ+SUwZMtCvqcMHaBxIMu+hyk5MI11hFOUi9N+vWvRb+NZ6JbK+1 # sqWcx0NdYfNdOeoi1dgzGgcCkFA8u9zW/K7Ih0W8WuU20uiJ4Zw/qmnEELIl/mZR # 5Ft1mhLMhQSYsH0KSypugLWBxR9SFNH1cV3C1SG2q+6snm/mhKk9NN18zJGFdmmY # 4CQThx159P/DaPUONZbSAMN94opu6K8FSymELPDUZBYwJRq7fyGKYuDUGRvN1kxx # I8p/MF1V5Vcth9lvGyBYulFWjo9BDMpkIdmWzXZLOWfzZVAed8PcglxoQqgMbU5u # eyY/Cw== # =Tv1h # -----END PGP SIGNATURE----- # gpg: Signature made Mon 06 Nov 2023 04:09:46 HKT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu: (21 commits) target/sparc: Check for invalid cond in gen_compare_reg target/sparc: Implement UDIV inline target/sparc: Implement UDIVX and SDIVX inline target/sparc: Discard cpu_cond at the end of each insn target/sparc: Record entire jump condition in DisasContext target/sparc: Merge gen_op_next_insn into only caller target/sparc: Pass displacement to advance_jump_cond target/sparc: Merge advance_jump_uncond_{never,always} into advance_jump_cond target/sparc: Merge gen_branch2 into advance_pc target/sparc: Do flush_cond in advance_jump_cond target/sparc: Always copy conditions into a new temporary target/sparc: Change DisasCompare.c2 to int target/sparc: Remove DisasCompare.is_bool target/sparc: Remove CC_OP leftovers target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD target/sparc: Remove CC_OP_DIV target/sparc: Remove CC_OP_LOGIC target/sparc: Split psr and xcc into components ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-06Merge tag 'migration-20231103-pull-request' of ↵Stefan Hajnoczi
https://gitlab.com/juan.quintela/qemu into staging Migration Pull request (20231103) Hi In this PULL: - dirty limit fixes (hyman) - coverity issues (juan) Please apply. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEGJn/jt6/WMzuA0uC9IfvGFhy1yMFAmVE4dgACgkQ9IfvGFhy # 1yPBgxAAvrsCHwU6/m9y+XGokyHTKKKIVysLip/14jAjDL+viLYgxdVyOGQKQGBa # +yV+XHTaEyKdihKG4Z5nWuC0yM+sdZQpWXQAcHJLPaPs5wDGICICpdAFY2LbAWSK # jtX9uq7crywIL4mVKiX+HOjRUPCAYUx/2TcqJf2+0+MKDEVC33ikxNbcx8ZELY+Q # +hGyOws3mkHSQjyaNUVgnnQtGzikYqcNO2efa+zVPdXYd+TUWW2e9I++Qf48r0Hv # OqeZAB7bSAb39PNRuj0I1gt4d3WTHzHt7BSpX1OuFqQnzLw8vS5iDQH943WAyGkY # NblZVb8pyzSg1Jy18H/SmrJDXeufRwqFwD+1NHyxGjsF89KOuVUqGrGpRXhMBtmA # DSzdgn5jqW5lI1po9FqGdlPTFlhstpMH3DSfPQWurvJh42oM38gmSEHLBNpc4tXo # 8udMYI09H/kHUoNMTZNGjnZO9LfarGsag6eOJP1bMMublhRlKCaL9RIyV9oOHycE # IeOeQFeBP/BmYFLWbVPeZej7uiqsEc7VPDJK2QXns210UYanaWmggkmpdAr0I0EV # pEKHSfVv1qlIlFH4d7MhcJzP2/rY62EC5tYQjT0UaBnCRcDInKrNWa3kbDL0akwr # 0aJgpbT5ipknVChtwnMWJlbqpeW/VUF5g0jVpYQ3jbe/Zf+OtmU= # =Pv8z # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Nov 2023 20:04:40 HKT # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full] # gpg: aka "Juan Quintela <quintela@trasno.org>" [full] # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * tag 'migration-20231103-pull-request' of https://gitlab.com/juan.quintela/qemu: migration: Unlock mutex in error case docs/migration: Add the dirty limit section tests/migration: Introduce dirty-limit into guestperf tests/migration: Introduce dirty-ring-size option into guestperf tests: Add migration dirty-limit capability test system/dirtylimit: Drop the reduplicative check system/dirtylimit: Fix a race situation Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-12 06:16:12 +0000